1 See discussions, stats, and author profiles for this publication at: Advanced Packaging Using Liquid Crystalline Polymer (LCP) Substrates Article January 2002 CITATIONS 7 READS 1,078 4 authors, including: Tan Zhang Apple Inc. 18 PUBLICATIONS 157 CITATIONS SEE PROFILE R. Wayne Johnson Tennessee Technological University 241 PUBLICATIONS 3,694 CITATIONS SEE PROFILE Brian Farrell 13 PUBLICATIONS 106 CITATIONS SEE PROFILE Some of the authors of this publication are also working on these related projects: Lead Free Aging View project Long Term Isothermal Aging on Alternate High Reliability Solder Materials View project All content following this page was uploaded by Brian Farrell on 24 July The user has requested enhancement of the downloaded file.
2 Advanced Packaging Using Liquid Crystalline Polymer (LCP) Substrates Tan Zhang & Wayne Johnson Auburn University 162 Broun Hall/ECE Dept Auburn, AL Brian Farrell Foster Miller, Inc 195 Bear Hill Rd Waltham, MA Abstract Michael St. Lawrence Rogers Corporation One Technology Drive Rogers, CT m Liquid crystalline polymer (LCP) substrates offer a number of advantages for high-density packaging. These properties include high temperature capability (>250 o C), low coefficient of thermal expansion (8ppm/ o C), low moisture permeability (comparable to glass), smooth surface, and good high frequency characteristics. LCP substrates can be fabricated as flexible films (2mil thick) or as rigid multilayer substrates. In this paper the processing of rigid and flexible LCP substrates are first discussed including etching, drilling, and plating. Next, the compatibility of LCP substrates with wire bond and flip chip assembly processes and materials are examined. Specific tests include solderability with eutectic Sn/Pb and lead-free alloys, surface insulation resistance with no-clean fluxes, gold wire bondability and flow/wetting of underfills for flip chip assembly. The high temperature capability of the LCP is compatible with the higher reflow temperatures associated with lead free solders and also allows thermosonic gold wire bonding at a substrate temperature of 200 o C. Solder dips in lead free alloys at 274 o C have shown no delamination of the copper foil. Gold ball shear test results demonstrate average shear strength of 62.4 grams with a standard deviation of 4.3 grams when bonded at 200 o C.. Optical fibers can be molded into the LCP substrate for optical connections and optical fibers can also be molded into the package sidewall for optical connections. Finally, hermetic packages have been fabricated and shown to pass fine and gross leak tests. Key Words: Liquid Crystalline Polymer, Printed Wiring Boards, Packages LCP Properties and Applications LCPs are so called because their molecules can be mutually aligned and organized (crystal), yet the bulk LCP can flow (liquid) in the molten state. This behavior is unlike ordinary polymers, which are randomly configured in the melt or in solution. The liquid crystal state results from the rigid nature of segments of the LCP molecules (Figure 1). When LCP flows in the liquid crystal state, the rigid segments of the molecules align next to one another in the shear flow direction, creating locally oriented domains. The domains, in turn, create macroscopic-oriented regions. Once the oriented regions are formed, their direction and structure persist, even when the LCP approaches the melt temperature because of the long relaxation time of the stiff chain LCP molecules. Figure 1 - Liquid crystal polymers have rigid segments, which tend to align in shear flow Although thermotropic LCPs possess a variety of properties that make them attractive candidates for electronic substrates, standard LCP processing techniques result in films with anisotropic in-plane properties. For example, extruded uniaxial LCP film has machine direction mechanical properties that are about one order of magnitude higher than those in the transverse direction. By having highly anisotropic tear and impact behavior, traditional processing of LCPs has not resulted in a product suitable for electronic packaging applications. Foster-Miller developed a proprietary processing technology that permits control of the fibrillar LCP orientation to any desired value, including quasi-isotropic, simply by varying the processing parameters (1). By utilizing a novel annular die, sheet and films can be produced with controlled directions of orientation. A combination of rotational shear and elongational flow during the extrusion process orients the LCP molecules. This controlled biaxial orientation, which is compared with uniaxially oriented films in Figure 2, is accomplished with an innovative counterrotating die that aligns the LCP molecules along two distinct axes within a single ply. Figure 3 shows how biaxial orientation is achieved with a counter-rotating circular die, which takes advantage of LCP's propensity to self-align in shear flow by using transverse shear to produce transverse orientation. A combination of processing parameters, including rotation rate, blow-up ratio and draw rate, can be used to control the film orientation rate and, subsequently, critical film properties such as CTE, tensile strength and tensile modulus.
3 Figure 2 - Comparison of uniaxially and biaxially oriented LCP film LCPs have a unique combination of properties that make them ideally suited for high density electronic substrate and packaging applications, including: Excellent electrical properties even up to millimeter wave frequencies (dielectric constant, 2.9; loss tangent, at 20 GHz). Extraordinary barrier properties, comparable to that of glass; LCPs are virtually impermeable to moisture, oxygen and other gases and liquids. Low coefficient of thermal expansion (CTE) 8 or 17 ppm/ o C. Very low moisture absorption, <0.04% by weight. Excellent dimensional stability (< 0.1%). for microwave multichip modules, advanced surface mount printed wiring boards and optoelectronic applications. Kuraray Co. Ltd. (Osaka, Japan) (7,8) has licenced Foster-Miller s LCP film technology and has developed a commercially viable LCP film. Rogers Corporation, a specialty materials manufacturer, has been working closely with Kuraray and has introduced its line of Zyvexä Liquid Crystalline Polymer circuit materials based on Kuraray s film. Having successfully help establish this commercial supply of LCP substrates, Foster-Miller is currently being funded by the US Army (9) to work closely with the PWB industry to develop a commercial capability for the fabrication of LCP-based PWBs. This effort is complemented by ongoing efforts at Rogers Corporation to work with the PWB industry to introduce their new line of Zyvexä circuit materials. Both companies have been working very closely together to document and pool their respective results and significant progress has been made to date. This paper will present detailed results of these critical process developments. PCB Processing Image and Etch: In a subtractive circuit patterning process, the key requirements of the base laminate are to enable adequate adhesion of the photoresist and not absorb process chemicals. Once the circuit pattern has been defined via the resist, the actual circuit is defined by etching the exposed copper away, using chemistries like Cupric Chloride. The key requirements of the base laminate are to have good adhesion between the copper and polymer, good resistance to etching chemistry, and a copper foil compatible with etching. When using industry standard practices, such as a 1.5mil aqueous dry film photoresist and a Cupric Chloride etchant at 125 C, lines as small as 1.5mils with copper foil as thick as 18μm have been demonstrated. Mound Flextek Inc. was able to demonstrate this in a continuous, roll-to-roll process. The key to LCP s success is its inherent chemical/moisture resistance, preventing any undercutting at the polymer/copper interface (see Figures 4 & 5) as well as the specific copper foil selected. Figure 3 - Biaxial orientation is achieved using the counter rotating circular die Foster-Miller has been developing an electronic packaging technology based on these innovative LCPs (2-6) Figure 4 Cross-Section LCP Circuit Traces (Courtesy of Mound Flextek)
4 Figure 5 LCP Circuitry Traces and Pads (Courtesy of Mound Flextek) Mechanical Drilling: For hole sizes 8 mils or greater, the standard industry practice is to use mechanical drilling techniques. It is important that a set of optimal drill conditions must be determined for any new material system. A study was performed, varying rotational speed ( SFM), infeed rate (2-8 mils/in), and retraction rate ( IPM) using a single drill size (20mils). Figures 6 8 show that infeed rate is the most critical factor for hole wall quality with retract rate second, and drill rotational speed having almost no effect. It is clear that lower infeed rate (sometimes referred to as chip load) combined with high retract rates, produced the best hole quality. Figure 6 Drilled Hole Wall vs. Infeed Rate (slowest is shown in upper left) Laser Drilling: Lasers are typically used for holes and vias less than 8 mils in diameter. The most common lasers used for PCB hole making are CO 2 or YAG. A study was performed comparing LCP to an all-polyimide, FR-4, and epoxy resin-coated-copper (RCC) product. For the YAG (355nm) experimentation, a single set of laser conditions was used 1W of power and a 1 mil beam size Results are shown in Figure 9. Figure 8 Drilled Hole Wall vs. Rotational Speed (slowest is shown in in upper left) Figure 7 Drilled Hole Wall vs. Retraction Rate (slowest is shown in in upper left) For the CO 2 drilling work (Table 1), some optimization of conditions was performed. Holding power constant, the pulse length, rate, and total number of pulses were varied to make the best vias in the materials. For the LCP material, the best vias were made with shorter, more frequent pulses and higher number of pulses than some of the other materials.
5 Power 6000W Pressure 350mtorr Desmear: After Gas 80% N 2 /20% O 2 drilling, the vias Time 15 minutes or holes typically require a cleaning step prior to metallization. This step removes debris while preparing the polymer surface for metal deposition. The most common desmear method is a wet chemical, permanganate exposure. As shown in Figure 10, this method is not effective with the LCP material due to LCP s extreme chemical resistance. Parameters LCP API FR-4 RCC Power 40W 40W 40W 40W # of pulse Metallization: Two seed layer metallization approaches were evaluated: electroless copper plating and the Shadow direct metallization process from Electrochemicals, Inc. The seed layer s role is to provide a well-adhered, conductive layer for copper to be electrolytically plated onto. Electroless copper plating results showed good coverage and adhesion when combined with a plasma desmear. Figure 12 below shows a 5 mil blind via fully plated. Pulse width Pulse period Table 1 Via drilling conditions for various materials CO 2 laser LCP Vs. FR4 Weight Change in Permanganate 0-1 Wt Change (%) LCP FR-4 Begin 1 Cycle 2 Cycle 3 Cycle Permanganate Cycles Figure 12 Metallized via with electroless followed by electrolytic copper plating The Shadow direct metallization process showed excellent coverage and adhesion, as illustrated in Figure 13. With the LCP material, Shadow appeared to be much less sensitive to drilling and desmear conditions than the electroless approach. Figure 10 Weight loss through permanganate exposure In contrast, plasma treatment is very effective at cleaning holes and preparing the LCP metallization. The SEM photographs in Figure 11 show a drilled via before and after plasma. The conditions used are presented in Table 2. Figure 13 Metallized via with Shadow followed by electrolytic copper plating Table 2 Typical plasma desmear cycle
6 Finish Metallization: Typical printed circuits require that some of the circuitry remain uncovered without solder mask and remain exposed for access to connections. Typically these exposed areas have a metallic finish applied to protect the copper from corrosion. Common finishes are various tin/lead solders, immersion tin, or electroless nickel/immersion gold. The solder is often applied using the hot air solder leveling (HASL) process which exposes the PCB material to very high temperatures. The other two finishes are applied using processes which expose the PCB material to very corrosive chemistries. The LCP circuit material was compatible with all three finishes. Assembly Processing For surface mount assembly, solderability and surface insulation resistance (SIR) are important considerations, particularly with no clean flux. Solderability: Solderability test coupons were fabricated according to IPC J-STD-003 with an electroless nickel/immersion gold finish. The solderability was measured using a 6-Sigma Wetting Balance Tester. Aim no clean flux was used with 63Sn/37Pb and 96.5Sn/2.25Ag/0.75Cu/0.5Sb solder alloys. A characteristic wetting curve is shown in Figure 14. The key wetting balance parameters measured were T a and F max. T a is the time to the buoyancy corrected force line. At this time the solder contact angle to the test coupon is 90 o and the wetting forces pulling the coupon into the molten solder equals the buoyancy force pushing the less dense coupon out of the molten solder. The smaller the T a, the quicker the solder wets to the coupon. F max is the maximum wetting force exerted by the solder on the coupon and is directly proportional to the height the solder climbs up the coupon. F max is the sum of the buoyancy force and the maximum force, F inst, recorded by the wetting balance during a particular test as illustrated in Figure 14. indicating the compatibility of LCP with higher temperature lead-free soldering. T a (Sec) F max (N/mm) Eutectic Sn/Pb Sn2.25Ag/0.75Cu/0.5Sb Solder Temperature ( o C) Figure 15. T a as a Function of Temperature for the Two Solder Alloys Eutectic Sn/Pb Sn/2.25Ag/0.75Cu/SnPb/0.5Sb Solder Temperature ( o C) Figure 16. F max as a Function of Temperature for the Two Solder Alloys. Figure 14. Characteristic wetting force vs. time graph. The solder pot temperature was varied and the variables T a and F max as a function of solder temperature are plotted in Figures 15 and 16, respectively. The dip depth was 5mm and the dip time was 5 seconds. As expected, T a decreases and F max increases with temperature. The lead-free alloy requires higher soldering temperatures due to its higher melting point, but exhibits excellent solder wetting. There was no evidence of damage to the LCP test coupon at the maximum solder temperature, Surface Insulation Resistance (SIR): The SIR coupons were designed per IPC-B-24 and the test method was per IPC- TM-650, Number Coupons were cleaned in a 50:50 deionized water/alcohol bath prior to testing to remove any contamination from the coupon fabrication process or handling. A low residue, low viscosity, no-clean flux was sprayed on one set of samples that were then passed through a standard eutectic Sn/Pb reflow cycle. The second set of coupons was tested as-cleaned. The coupons were stored for 168 hours with a 45 Vdc bias at 85%Rh/85 o C. Periodic insulation measurements were made by applying a 100Vdc reversed bias and measuring the resulting current flow. The minimum surface insulation (12 samples per condition) is plotted in Figure 17. In both cases the coupons exceed the 10 9
7 Ohm specification. There is no indication of chemical interaction between the flux and the LCP As-Cleaned Flux Minimum Resistance (10 9 Ohms) Time at 85%RH/85 o C/45Vdc (hours) Figure 17. Minimum SIR Test Results (a) Assembly: For advanced packaging applications, compatibility with flip chip and wire bond assembly is required. A flip chip test vehicle was fabricated using the PB- 8 flip chip test die (0.200 x with bump pitch). The LCP board had an electroless nickel/immersion gold surface finish. A die site is shown in Figure 18. There is no solder mask beneath the area on which the die will be placed. The flip chip die were assembled with a Siemens F5 pick and place machine using Kester 6502 dip flux. The boards were reflowed in a nitrogen atmosphere with a Heller 1800 reflow oven. The peak temperature for the eutectic Sn/Pb was 220 o C and for the eutectic SnAgCu was 245 o C. After reflow, the die were x-rayed with a Phoenix micro-focus x-ray and good alignment and wetting were observed (Figure 19). Next the die were underfilled with Loctite 3563 (a fast flow, snap cure underfill) using a Camalot 3700 dispense system. After underfill cure (165 o C for 5 minutes), a Sonix scanning acoustic microscope was used to examine the underfill. As seen in Figure 20, no voids were observed, indicating good flow of the underfill over the LCP substrate. (b) Figure 19. X-ray Images after Reflow (a) Eutectic Sn/Pb and, (b) Eutectic SnAgCu. Figure 20. Typical C-SAM Image After Underfill and Cure. Figure 18. Flip Chip Assembly Site. Figure 21 shows cross sections with the eutectic Sn/Pb and eutectic SnAgCu solder bumps. Good solder wetting and no underfill settling or de-wetting were observed.
8 (a) low moisture permeability of LCP makes it an ideal candidate for fabrication of low cost, near-hermetic cavity packages for electronics and MEMS devices. CTE Matching: The use of an all-lcp construction eliminates stresses induced by different packaging materials. In addition, the LCP can provide a close CTE match to either silicon or copper. Dimensional Stability: LCP s excellent dimensional stability makes it a viable solution for passive alignment packaging systems for optical microsystems. Localized Thermoplastic Sealing: Thermoplastic sealing, such as ultrasonic welding or laser welding, have shown great promise with LCPs. Low-Cost Optical Feedthroughs: Optical feedthroughs can be integrated into LCP packages by reflowing the LCP around the glass-clad fibers. The following paragraphs highlight some more in-depth background and details on some of our recent LCP-based packaging activities: (b) Figure 21. Cross-section Images (a) Eutectic Sn/Pb and, (b) Eutectic SnAgCu. A Palomar Product 2460 Model V automatic thermosonic wire bonder was used to evaluate the wire bondability of an LCP test board with an electroless nickel/electroless gold finish. The wire diameter was and the stage temperature was 200 o C. The high temperature capability of the LCP allowed a higher stage temperature than is typical with laminate substrates. With metal leadframes, 200 o C is commonly used. Shear tests were performed. The results are summarized in Table 3. LCPs Barrier Properties: Thermoplastic LCP films offer the potential of near hermetic packaging due to their low moisture and oxygen permeability, especially with films extruded with Foster-Miller's unique biaxial orienting dies. LCP film samples were submitted to MOCON/Modern Controls, Inc., for permeability testing. The permeant was water (100% RH at 40oC) and the carrier gas was nitrogen at ambient pressure. The results are given in Table 4. The moisture permeability value corresponds to common glass and is substantially lower than typical polymers. Figure 22 highlights the moisture permeability of oriented LCP film in comparison to hermetic materials (metals, ceramics and glasses) and non-hermetic polymers. The data shows that LCP offers the potential of a hermetic plastc package, a hitherto unimaginable concept. Table 3. Wire Bond Shear Test Results. Shear Strength (g-f) Average 62.4 Standard Deviation 4.3 Packaging Developments: In addition to its excellent properties as a PCB substrate material, LCP offers the systems designer a complete packaging solution wherin the material can be used both as the interconnect substrate and the lid assembly. An all-lcp package assembly offers several key performance advantages, including: Excellent Barrier Properties: LCPs have excellent barrier properties, comparable to glass (Figure 22), that offer the potential of near-hermeticity of the sealed package. The Figure 22. Permeability of LCP and General Packaging Related Materials.
9 Table 4. Moisture Properties of LCP Films Thickness (mil) WVTR (g/m 2 - day) Permeability (g-mil/m 2 - day) Diffusivit y (cm 2 /sec) Package Sealing:: Three approaches for sealing LCP packages are under investigation namely solder, ultrasonic, and laser sealing: Solder Sealing is readily achievable using a metalized lid, a solder preform and a seal frame on the interconenct substrate. Molded LCP lids have been metallized via plating and deposition processes and, subsequently, soldered sealed to a seal frame on the interconnect substrate. To prove the reliability of solder-sealed LCP packages, a solder-sealed cavity package was designed using an LCP substrate for a MEMS humidity sensor. The package design concept utilized a double-sided LCP printed circuit board that had patterned copper on both sides. Press fit nickel/gold plated kovar pins were inserted into drilled through-holes and soldered to copper landings on both sides of the LCP board. The top side of the board had traces that ran from the copper landings to bond pads for the MEMS humidity sensor. Also, on the top side of the board was a copper ring that encircled the pins and components. The package lid was a machined copper lid, nickel and gold plated. The lid was vacuum solder sealed to the copper ring using Sn/Pb solder. The package is shown in Figure 23. Figure 23. LCP MEMS Package. Solubility (g/cc) x x Five sealed packages were submitted to the Reliability Analysis Laboratory at Raytheon (Lexington, MA) for fine and gross leak testing. The packages were helium pressure bombed at 3 atmospheres for 90 hours for fine leak testing. Three packages started at 4x10-8 Atm cc/sec, decayed to 1.3x10-8 Atm cc/sec over 6 hours and to 3.5 x10-9 Atm cc/sec over 22 hours. The fourth package started at 4x10-8 Atm cc/sec, decayed to 2x10-8 Atm cc/sec over 6 hours and to 1.8x10-8 Atm cc/sec over 22 hours. These four packages passed fine and gross leak testing. The He decay rates for the four packages were consistent with He being absorbed by LCP during pressure bombing and desorbed during the leak test. The fifth package showed a steady leak rate of 2.5x10 7 for 4 hours, consistent with a fine leak in the solder seal. Ultrasonic sealing is accomplished by applying ultrasonic heating to the sealing edge of the lid while the lid is in place on the substrate. An ultrasonic horn was designed to be used in a standard "plunge welding" ultrasonic welding system. Ultrasonic welding has shown some promising results for rugged LCP package designs, but, due to the intensity of the process, may not be the optimum welding technique for sensitive component applications. Delicate wirebonds and surface mount components have been damaged or broken by the ultrasonic process. The final package sealing approach, and likely the most attractive and promising is laser welding. Laser welding is a high-speed and efficient method for the joining of thermoplastics. However, with common, high power laser systems, the laser energy tends to decompose the thermoplastic. The key is to use lower power laser systems combined with a suitable absorbing material at the bondline. The presence of an absorbing material at the bondline will provide enough absorption of the laser energy to form a robust weld. Nearly all polymers are transparent to infrared energy in the near infrared optical spectrum. Even polymers that are opaque to visible light, such as LCP, are highly transparent and can be welded using appropriate absorbing layers. The welding process works when laser radiation is passed through a transparent polymer to an absorbing interface that is in contact with the transparent polymer, as shown in Figure 24 (10). Heat generation at the interface melts the transparent polymer. The heat source is outside the weld zone. The work part can be moved, on an x-y table, under the laser beam to generate the desired weld pattern. Figure 25 shows a specially designed LCP package that was designed for laser welding. The package design for laser welding incorporates an extended lip on the sealing edge of the package lid. The LCP material is transparent to the IR radiation and therefore requires the introduction of an IR susceptor. This IR susceptor absorbs the IR energy and produces localized heating to melt and seal the LCP at that specific point. This IR susceptor may come in a variety of materials including, but not limited to iyanocyanine green and ClearWeld (10). The IR susceptor is applied to the welding seam by printing, screening, or painting the material to the substrate at the mating point to the package lid. Laser sealing of LCP packages offer many advantages in emerging markets such as temperature sensitive MEMS and optical components. Laser welding creates only localized heat and therefore does not harm the components being packaged, whereas, current solder reflow processes create potentially harmful heat through the entire package assembly. Also, laser sealing is environmentally friendly.. Market and environmental pressures are pushing for the lead-free initiative adoptation. Laser sealing of LCP is a clean, safe, and environmentally friendly solution for near hermetic packaging needs.
10 (a) Figure 24. Laser Welding of Thermoplastics (10) (b) Figure 25. LCP Lid Designed for Laser Sealing Optical Packaging: Perhaps the most immediate market to benefit from this developing LCP packaging technology lies in the area of optoelectronic subsystems. The dramatic expense associated with optoelectronic subsystem packaging can, potentially, be greatly reduced using lower cost LCP materials and packaging methodologies. Initial experiments have yielded some interesting results and processes that should open up new and interesting design options for optoelectronic packaging. We have demonstrated some initial optical packaging processes. Optical fibers can be laminated between layers of LCP to form optical interconnects that can be embedded in the substrate or can be embedded into package sidewalls to provide optical I/O. Figure 26(a) is a cross section of an optical fiber laminated inside an LCP substrate, while Figure 26(b) shows light transmitted to the exposed end of the fiber. Figure 27 shows a final image of a fiber embedded into the sidewall of a package. Given the near-hermeticity of LCP packages and the ease with which opical fibers can be laminated into the LCP, LCP is being investigated for packaging of optical components including MOEMS. Figure 26. Cross Section of Optical Fiber Laminated within an LCP Substrate (a) and Light Emission from Fiber (b). Figure 27. Scanning Electron Micrograph of Optical Fibers Through LCP Package Wall
11 Summary After many years of development, Liquid Crystalline Polymer circuit materials are now commercially viable. Combining attractive electrical and physical properties with commercially viable PCB and package fabrication processes should enable LCP materials to be used for the next generation of high performance electronics. Acknowledgments The authors would like to thank the following people and companies for their ongoing assistance: Pete Black U.S. Army Aviation and Missile Command Bill Payne - PMTEC Ron Carter - PMTEC Kuraray Co. LTD. Rick McConnell - Mound Flextek Dale Wesselmann - Mult-Fineline Electronix Lance Riley - Unicircuit Rachel Matthews - Unicircuit Jim Martin - Electrochemicals Jim Keating - PhotoMachining Gabor Kardos - Photo Machining Mike Kuszaj - Rogers Corporation Cliff Roseen - Rogers Corporation Jerry Green - Soldering Technology International John Gregory - STS ATL Corp Jerry Zybko Leister USA Steve Kocheny Leister USA References 1. Blizard, K.K., Wilson, T.S. and Baird, D.G., International Polymer Processing, V. 53, K. Jayaraj and B. Farrell, Liquid Crystal Polymers and Their Role in Electronic Packaging, Advancing Microelectronics, Volume 25, No. 4., B. Farrell, K. Jayaraj and L. Felton, Low Cost, Multichip Modules Based on Liquid Crystal Polymers, 16 th Digital Avionics Systems Conference, 1997, Irvine, California. 4. K. Jayaraj, L. Felton, B. Farrell, and T. Tiano, The Preliminary Development of a Novel Corrosion Resistant Plastic Package, InterPACK 97, Hawaii. 5. T. Noll, K. Jayaraj, B. Farrell, and R. Larmouth, Lowcost, Near-hermetic Multichip Module Based on Liquid Crystal Polymer Dielectrics, Proceedings of the International Conference on Multichip Modules, 1996, Denver, Colorado. 6. T. Noll, K. Jayaraj, B. Farrell, T. Perkins and D. Glynn, Low-cost Phased Array Antenna Packaging Technology, Twentieth Annual Antenna Applications Symposium, 1996, University of Illinois, Monticello, Illinois. 7. Y. Tanaka and M. Onodera, Liquid Crystal Polymer Materials for LSI Mounting, Journal of the Japanese Society for Electronics Mounting, Volume 2, No. 2., M. St.Lawrence and Y. Tanaka, Adhesion of Metal to Polymer A Comparison Between Adhesiveless Polyimide, Adhesive-Based Polyimide, and Liquid Crystal Polymer Substrates, IMAPS 99, Chicago. 9. Army Contract # DAAH01-00-C-R066, Development of advanced printed circuit board technology using Liquid Crystal Polymers View publication stats
Lead Free Solder for Flip Chip Zhenwei Hou & R. Wayne Johnson Laboratory for Electronics Assembly & Packaging Auburn University 162 Broun Hall, ECE Dept. Auburn, AL 36489 USA 334-844-1880 firstname.lastname@example.org
Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Zaheed S. Karim 1 and Jim Martin 2 1 Advanced Interconnect Technology Ltd. 1901 Sunley Centre, 9 Wing Yin Street, Tsuen Wan, Hong
General Introduction to Microstructure Technology p. 1 What is Microstructure Technology? p. 1 From Microstructure Technology to Microsystems Technology p. 9 The Parallels to Microelectronics p. 15 The
Building HDI Structures using Thin Films and Low Temperature Sintering Paste Catherine Shearer, James Haley and Chris Hunrath Ormet Circuits Inc. - Integral Technology California, USA email@example.com
Qualification and Performance Specification for High Frequency (Microwave) Printed Boards Developed by the High Speed/High Frequency Board Performance Subcommittee (D-22) of the High Speed/High Frequency
Fundamentals of Sealing and Encapsulation Sealing and Encapsulation Encapsulation and sealing are two of the major protecting functions of IC packaging. They are used to protect IC devices from adverse
ESPANEX L Series Technical data sheet This sheet will be changed without any information in advance. The data on this sheet are solely for your reference and are not to be constructed as constituting a
Flip Chip - Integrated In A Standard SMT Process By Wilhelm Prinz von Hessen, Universal Instruments Corporation, Binghamton, NY This paper reviews the implementation of a flip chip product in a typical
Processor Performance, Packaging and Reliability Utilizing a Phase Change Metallic Alloy Thermal Interface System Chris G. Macris, Thomas R. Sanderson, Robert G. Ebel, Christopher B. Leyerle Enerdyne Solutions,
ICDs (InterConnect Defects) What are they? Where do they come from? How can we make them go away? Doug Trobough Suixin Zhang Definition of ICD ICDs are any defect that occurs adjacent to the innerlayer
Innovative MID Plating Solutions High Reliability Wire Bond Technique for MIDs Jordan Kologe MacDermid Electronics Solutions firstname.lastname@example.org 1 MacDermid: Specialty Chemical Solutions Over 2000 Worldwide
ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES Qualification and Performance Specification for Organic Multichip Module (MCM-L) Mounting and Interconnecting Structures February 1998 A standard developed
Plasma for Underfill Process in Flip Chip Packaging Jack Zhao and James D. Getty Nordson MARCH 2470-A Bates Avenue Concord, California 94520-1294 USA Published by Nordson MARCH www.nordsonmarch.com 2015
Optimizing Immersion Silver Chemistries For Copper Ms Dagmara Charyk, Mr. Tom Tyson, Mr. Eric Stafstrom, Dr. Ron Morrissey, Technic Inc Cranston RI Abstract: Immersion silver chemistry has been promoted
Optimizing Immersion Silver Chemistries For Copper Ms Dagmara Charyk, Mr. Tom Tyson, Mr. Eric Stafstrom, Dr. Ron Morrissey, Technic Inc Cranston RI Abstract: Immersion silver chemistry has been promoted
New Technology for High-Density Mounting in Consumer Products V Hidehiko Kira V Akira Takashima V Yukio Ozaki (Manuscript received May 29, 2006) The ongoing trend toward downsizing and the growing sophistication
IPC-AJ-820A Assembly and Joining Handbook The How and Why of All Things PCB & PCA 1 Scope To provide guidelines and supporting info for the mfg of electronic equipment To explain the HOW TO and WHY Discussions
Fabrication Technical Articles Notes RO4835T Core/RO4450T Bonding Layers Multi-Layer Board Processing Guidelines These guidelines were developed to provide fabricators basic information on processing core
THE EFFECT OF GLUE BOND LINE THICKNESS (BLT) AND FILLET HEIGHT ON INTERFACE DELAMINATION Raymund Y. Agustin Janet M. Jucar Jefferson S. Talledo Corporate Packaging & Automation/ Q&R STMicroelectronics,
~ CLAD MATERIAL ~ FINE CLAD is a solution for high density, low cost PWB. Principle of bonding technique Principle of bonding technique Step 1 Material A, B In vacuum Step 2 Surface activated treatment
Thermosonic Gold Ball Bonding to Immersion Gold/Electroless Nickel Plating Finishes on Laminate MCM Substrates Chris Dunn, R. Wayne Johnson Mike Bozack Auburn University 200 Broun Hall, EE Dept. Auburn,
Original Author: Steve Babiuch Process Owner: Steve Babiuch Page 2 of 8 1.0 Purpose This specification establishes the NEO Tech fabrication requirements for printed circuit boards. The order of precedence
As originally published in the SMTA Proceedings ELECTROPLATED COPPER FILLING OF THROUGH HOLES INFLUENCE OF HOLE GEOMETRY Ron Blake, Andy Oh, Carmichael Gugliotti, Bill DeCesare, Don DeSalvo, Rich Bellemare
Ag plating in HBLED packaging improves reflectivity and lowers costs JONATHAN HARRIS, President, CMC Laboratories, Inc., Tempe, AZ Various types of Ag plating technology along with the advantages and limitations
THE EFFECTS OF PLATING MATERIALS, BOND PAD SIZE AND BOND PAD GEOMETRY ON SOLDER BALL SHEAR STRENGTH Keith Rogers and Craig Hillman CALCE Electronic Products and Systems Center University of Maryland College
Bungard Surfaces Page 1 / 8 This flyer is supposed to inform you about the different kinds of surfaces for your pcb. We hope to provide interesting information. If you encounter any questions or you need
Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip SzePei Lim (Presenter), Jason Chou, Maria Durham, and Dr. Andy Mackie Indium Corporation 1 Outline of Presentation Roadmaps and challenges
Challenges for Embedded Device Technologies for Package Level Integration Kevin Cannon, Steve Riches Tribus-D Ltd Guangbin Dou, Andrew Holmes Imperial College London Embedded Die Technology IMAPS-UK/NMI
Component Palladium Lead Finish - Specification Approved by Executive Board 1997-xx-xx August 22 Version Appendices 1. User Commitment Form 2. Supplier Compliance Form Table of contents 1. Background 2.
As originally published in the SMTA Proceedings. EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS Neil Poole, Ph.D., Elvira Vasquez, and Brian J. Toleno, Ph.D. Henkel Electronic
IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION Frank Grano, Felix Bruno Huntsville, AL Dana Korf, Eamon O Keeffe San Jose, CA Cheryl Kelley Salem, NH Joint Paper by Sanmina-SCI Corporation EMS, GTS
A Multilayer Process for 3D-Molded-Interconnect-Devices to Enable the Assembly of Area-Array Based Package Types T. Leneke and S. Hirsch TEPROSA Otto-von-Guericke University Magdeburg, Germany email@example.com
Effect of Process Variations on Solder Joint Reliability for Nickel-based Surface Finishes Hugh Roberts Atotech USA Inc., Rock Hill, SC, USA Sven Lamprecht, Gustavo Ramos and Christian Sebald Atotech Deutschland
Advances in Printing nano Cu and Using Existing Cu Based Manufacturing Processes Michael J. Carmody Chief Scientist, Intrinsiq Materials Why Use Copper? Lower Cost than Silver. Print on Numerous Substrates.
VOLUME 4 - ELECTROFORMING Leveraging the Precision of over Alternative Processes When Developing Nano-scale Structures Electrical and mechanical component and subsystem designers generally have five techniques
2/14 Unit mm L a a Code letter Dimension L 2..2 W 1.25.2 W t a b.220.127.116.11.4.2 t b b Fig.1 Construction and dimensions NOTE : Resistive element Electrode Protective coat Substrate Nichrome alloy thin film
Welcome to Streamline Circuits Lunch & Learn Design for Reliability & Cost Reduction of Advanced Rigid-Flex/Flex PCB Technology Accurate PCB data is critical to the tooling process. Here are some key items
LEAD-FREE ASSEMBLY COMPATIBLE PWB FABRICATION AND ASSEMBLY PROCESSING GUIDELINES. TECHNICAL BULLETIN As the industry has moved to lead-free assembly processing, the performance demands on the lead free
Development of a Fluxless Flip Chip Bonding Process for Optical Military Electronics Michael Girardi, Daric Laughlin, Philip Abel, Steve Goldammer, John Smoot NNSA s Kansas City Plant managed by Honeywell
Advances in Printing nano Cu and Using Existing Cu Based Manufacturing Processes Michael J. Carmody Chief Scientist, Intrinsiq Materials Why Use Copper? Lower Cost than Silver. Print on Numerous Substrates.
WF637 A superactive low-volatile/high heat-resistant water-soluble flux for ball soldering Low viscosity and high tacking power stabilize ball holding force and ensures excellent solder wettability Easy
ELEC 6740 Electronics Manufacturing Chapter 5: Surface Mount Design Considerations R. Wayne Johnson Alumni Professor 334-844 844-1880 firstname.lastname@example.org. @eng.auburn.eduedu Outline System Design Issues
ELEC 6740 Electronics Manufacturing Chapter 5: Surface Mount Design Considerations R. Wayne Johnson Alumni Professor 334-844-1880 email@example.com. @eng.auburn.eduedu Outline System Design Issues Package
Beam Leads The vast majority of chips are intended for connection with thermosonic bonds: all other methods require some modification to the wafer. As early as 1972, Jordan described three gang-bonding
ALTERNATIVES TO SOLDER IN INTERCONNECT, PACKAGING, AND ASSEMBLY Herbert J. Neuhaus, Ph.D., and Charles E. Bauer, Ph.D. TechLead Corporation Portland, OR, USA firstname.lastname@example.org ABSTRACT Solder
High Frequency Circuit Materials Attributes John Coonrod, Rogers Corporation Specialty high frequency circuit materials have been used in the PCB industry for decades and for many different reasons. There
PRINTED CIRCUITS HANDBOOK Clyde F. Coombs, Jr. Sixth Edition Me Graw New York Chicago San Francisco Lisbon London Madrid Mexico City Milan New Delhi San Juan Seoul Singapore Sydney Toronto CONTENTS List
TIN-BASED LEAD-FREE SOLDER BUMPS FOR FLIP-CHIP APPLICATION S. Yaakup, H. S. Zakaria, M. A. Hashim and A. Isnin Advanced Materials Research Centre (AMREC), SIRIM Berhad, Lot 34, Jalan Hi-Tech 2/3, Kulim
Presented at IPC SMEMA Council APEX SM 2001 For additional information, please email email@example.com Reliability of Lead-Free Solder Connections for Area-Array Packages Ahmer Syed Amkor Technology,
Supporting Information: Model Based Design of a Microfluidic Mixer Driven by Induced Charge Electroosmosis Cindy K. Harnett, Yehya M. Senousy, Katherine A. Dunphy-Guzman #, Jeremy Templeton * and Michael
Cu electroplating in advanced packaging March 12 2019 Richard Hollman PhD Principal Process Engineer Internal Use Only Advancements in package technology The role of electroplating Examples: 4 challenging
Using PDMS Micro-Transfer Moulding for Polymer Flip Chip Packaging on MEMS Edward K.L. Chan, Cell K.Y. Wong, M. Lee, Matthew M.F. Yuen, Yi-Kuen Lee Department of Mechanical Engineering Hong Kong University
1 Material based challenge and study of 2.1, 2.5 and 3D integration Toshihisa Nonaka Packaging Solution Center R&D Headquarters Hitachi Chemical Co., Ltd., Sep. 8, 2016 Hitachi Chemical Co., Ltd. 2010.
Construction Analysis EM25VC Communication Controller Report Number: SCA 9711-562 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:
Two Chips Vertical Direction Embedded Miniaturized Package Shunsuke Sato, 1 Koji Munakata, 1 Masakazu Sato, 1 Atsushi Itabashi, 1 and Masatoshi Inaba 1 Continuous efforts have been made to achieve seemingly
Aluminum Silicon Carbide (AlSiC) for Advanced Microelectronic Packages Mark Occhionero, Richard Adams, Kevin Fennessy, and Robert A. Hay Ceramics Process Systems, Corp. Chartley, MA 02712 Abstract Aluminum
www.ko-ki.co.jp Ver. 42004.5 Prepared on Mar. 7, 2005 Koki no-clean LEAD FREE solder paste Hi-performance Product information 0.4mm pitch 0.3mm diameter This Product Information contains product performance
Super High Density Two Metal Layer Ultra-Thin Organic Substrates for Next Generation System-On-Package (SOP), SIP and Ultra-Fine Pitch Flip-Chip Packages Venky Sundaram, Hunter Chan, Fuhan Liu, and Rao
Palladium as diffusion barrier - a way to a multifunctional printed circuit board finish Dr. Norbert Sitte, Schwaebisch Gmuend, Umicore Galvanotechnik GmbH 1. Introduction Due to the continuing miniaturization
Electroplated Copper Filling of Through Holes on Varying Substrate Thickness Kesheng Feng a, Bill DeCesare a, Mike Yu b, Don DeSalvo c, Jim Watkowski a a MacDermid, 227 Freight Street, Waterbury, CT 06702
Basic PCB Level Assembly Process Methodology for 3D Package-on-Package Vern Solberg STC-Madison Madison, Wisconsin USA Abstract The motivation for developing higher density IC packaging continues to be
Designing With High-Density BGA Packages for Altera Devices December 2007, ver. 5.1 Application Note 114 Introduction As programmable logic devices (PLDs) increase in density and I/O pins, the demand for
Question: Are RO4 materials compatible with lead-free processes? Answer: RO4 cores and prepregs are among the most temperature stable products available. They easily meet or exceed all expectations for
!"#$#%&#'(() ) **+,-./01)2-,-.3)456,1) /0!7.5853-09**) B 2 IT is a Toshiba Process Technology 1. Conductive Ag bumps are printed on a sheet of Cu foil. 2. Prepreg is pierced through by the bumps 3. Another
. Adaption to scientific and technical progress under Directive 2002/95/EC Results previous evaluation Exemption No. 7 a a) Lead in high melting temperature type solders (i.e. lead-based alloys containing
Effect of Die Bonding Condition for Die Attach Film Performance in 3D QFN Stacked Die. A. JALAR, M. F. ROSLE, M. A. A. HAMID. School of Applied Physics, Faculty of Science and Technology Universiti Kebangsaan
PWB Dielectric Substrates for Lead-Free Electronics Manufacturing Douglas Leys and Steven P. Schaefer* Park Electrochemical Corp. Anaheim, CA *Lake Success, NY Abstract In order to safely accommodate the
PSR-4000 MP Series UL Name: PSR-4000MP/CA-40MP LIQUID PHOTOIMAGEABLE SOLDER MASK Screen or Spray Application Green or Black Matte Finish DI version available for both Green and Black Designed specifically