Card/PCB Damage in No-Pb Assembly. Test Plan

Transcription

1 Card/PCB Damage in No-Pb Assembly Test Plan Submitted to the Area Array Consortium By Brian Roggeman Process Research Engineer Wayne Jones Process Research Engineer Surface Mount Technology Laboratory Universal Instruments Corporation Binghamton, NY October 2005

2 ABSTRACT This document serves to provide goals and objectives associated with evaluation of the robustness and process sensitivity of various laminate materials and structures in Pbfree assembly. The overall goals are to: 1) Generate an experimental basis and understanding for proper materials and structure testing protocols. 2) Identify and obtain currently available robust PWB materials and components. 3) Design and build appropriate test board(s) which effectively evaluate material damage at Pb-Free temperatures. ABSTRACT CARD / PCB DAMAGE DAMAGE OBSERVATIONS DAMAGE & TEST DISCUSSION CURRENT PCB/ASSEMBLY TESTING TESTING SPECIFICALLY FOR NO-PB PB-FREE BOARD DAMAGE TEST PLAN TABLE OF CONTENTS Laminate and Solder Mask Material Pre-Screening Test Structures Characterization Preconditioning (Damage) TESTS/RESPONSE PARAMETERS INTRODUCTION There is a rapidly growing concern that cards, Printed Circuit Boards (PCB s) and components offered for Pb-free assembly may not all in fact be completely suitable for this, i.e. that some may be subject to latent or maybe infrequent damage unlikely to be detected in current experimentation and process development. One example of this might be the delayed failure of one or a few vias or pads on an entire PCB (or maybe

3 not even on every PCB in a batch) under specific conditions. Our current impression is that, at best, a very limited range of tests is often employed to ascertain that the use of specific materials and structures may be extended to Pb-free assembly. By nature, suppliers may certainly be expected to focus their efforts on the cards/pcbs alone, just as component suppliers are likely to most often test the components by themselves. We therefore have particular concerns as to additional damage and damage mechanisms introduced when one is attached to the other. This might for example occur as a result of the loads exerted on the card/pcb by a particular component or connector, and perhaps only be an issue for a particular combination of component properties (rigidity, expansion and warpage vs. temperature), dimensions and location. A primary goal is to identify materials and structures that are sufficiently robust in no-pb assembly. However, a more immediate and important one is first to learn to understand what our concerns should be, and how to test for them. Our proposed testing is expected to offer ongoing learning in this respect. CARD / PCB DAMAGE As already well established, some materials and structures may be damaged in assembly in a wide variety of ways. Several specific problems that might be expected to exacerbate Pb-free assembly, relative to eutectic Sn/Pb assembly include (in no particular order): 1. Moisture uptake and degradations of insulation and dielectric performance. 2. Inner-post separation (IP SEP) and Innerconnect defects (ICD s). 3. Reduced copper (pad) adhesion. 4. Reduced solder mask adhesion and delamination. 5. Damage to the electroless and electrolytic coppers in PTH s and vias. 6. Reduced mechanical strength and fracture resistance. 7. Reduced chemical resistance. 8. Cracking of the laminate (notably under the pads). 9. Boards are often seen to become discolored and blister in no-pb reflow, and they may be warped more than in Sn/Pb reflow, both temporarily and permanently. DAMAGE OBSERVATIONS The development of a meaningful test plan should rely on a comprehensive review of potential damage mechanisms. Some potential problems known to be enhanced in Pbfree assemblies, notably those associated with metallization phenomena such as 'black pad are considered to fall outside the scope of the present project (addressed as part of other consortium projects). Others may not be properly identified or assessed until after the work has started, so the list is likely to change over time, therefore initial input will be solicited from industry contacts.

4 Like many others we have already seen delamination and blistering in no-pb reflow of some high-t g FR-4 boards after extended ambient storage (and no bake-out to dry). Blistering near/between PTHs and/or vias was reported to increase with decreasing hole pitch, not a surprising trend. Recently, we found no-pb BGA assembly to lead to fine cracks in the laminate under the pads on 4-layer.092 thick high-t g (175C) FR-4 test boards. It appears that these cracks tend to grow substantially in cycling, but that this growth is sensitive to component construction (warpage). This seems to be at least partly associated with the overall resin thickness and low metal layer count. Follow-up experiments with the same component showed no cracking of boards in reflow, i.e. the unusually thick laminate layers were probably a factor. However, Sn/Pb based assembly of the same component with the same reflow profile (245C peak) did not cause cracking of the board either, so the higher flow stress of the Tin, Silver, Copper (SAC) alloy joints seemed to make things worse. While the 245C peak by itself did not cause detectable damage it may have contributed as well. Certainly, raising the peak temperature to 270C (which may occur in some assembly unless special measures are taken) did cause the thick boards to crack as well, even with Sn/Pb solder. Temperatures intermediate between 245C and 270C remain to be tested. DAMAGE & TEST DISCUSSION Even a typical Sn/Pb reflow is likely to weaken laminate structures somewhat. The only question is whether this is enough to be important. Similarly, we would expect no-pb reflows to have a measurably enhanced effect on a number of properties. Our observation of laminate cracking under the pads of even Sn/Pb based assemblies after a 270C peak reflow is one illustration of such weakening. This does not necessarily mean that all weakening effects are of practical concern. We plan to take a mechanistic approach to damage evaluation; working to identify the root causes and quantify the potential consequences in terms of production yields, circuit integrity, and postassembly performance, etc. An important part of many damage concerns is the specific (thermo) mechanical load involved. This load does not always have to be greater than in Sn/Pb assembly for it to become an increased concern. A no-pb reflow profile may simply weaken the structures so much more than a Sn/Pb profile that they can no longer always sustain the load exerted by, say, a rigidly underfilled flip chip or a through-hole component. Some loads will, however, invariably also be greater. Area array solder joints are almost certain to reach their flow stress, as determined by assembly mechanics and the cooling rate, during a substantial part of cool-down from any realistic reflow. Literature data suggest that these stresses may be almost twice as high in typical no-pb joints as in Sn/Pb. In addition, cooling from higher temperatures a component may tend to warp more and thus exert a greater out-of-plane load on the board. Large resistors and capacitors, such as 2512s, may load contact pads and associated vias even more. Non-uniform heating is very likely to be more damaging to both laminate and metal

5 structures than regular mass reflow. Wave soldering induces strong transient temperature gradients through the thickness of the board and selective soldering involves particularly large lateral variations as well. These problems are exacerbated in no-pb soldering where the higher melting points and reduced wetting call for higher temperatures and longer times, a requirement that is further enhanced by power/ground planes shielding layers above them from the heat and thus inhibiting the penetration of solder up the through-holes. Importantly, conventional IST testing of bare via chains after typical no-pb soldering might easily underestimate the potential for damage. A heavy (large thermal mass) through-hole component on the top side may strongly enhance local temperature gradients, as well as calling for higher temperatures and/or longer heating times. In addition, a massive component such as a power transformer may not allow for very effective relaxation after solder solidification and may exert a particularly high load on the board at that particular location during cool-down. To make matters worse no-pb wave soldering is also supposed to require faster cooling to prevent fillet lifting, further raising loads and the risk of cracking or permanent board warpage. Another occasion for strongly non-uniform local heating is that of repair, particularly of large area array component with a heat spreader which may require prolonged heating to ensure good soldering while limiting the maximum component temperature. In addition, repair of field repairs in particular may involve boards that have degraded somewhat after the initial no-pb assembly process. Finally, thermal shock testing may cause significant temperature gradients in thick boards all by itself. In this respect, such testing is completely irrelevant to any service conditions but underfilled flip chip assemblies are often tested in thermal shock and it has become common to require that the board (vias) not become the limiting factor. A somewhat special challenge is the accommodation of compliant pin or press fit connectors. Ensuring sufficient retention force and the long-term stability of a minimum contact resistance requires a significant loading of, and potential interior damage to, the board. In particular, the interior of the board may be damaged during insertion of the connectors and rework. Necessary changes to both solder and metallizations are expected to call for increased loads in no-pb assembly, the effects of which may be further exacerbated by any additional weakening of the laminate structures in the higher temperature reflow. We emphasize that mechanical damage is not confined to cracking of laminates and metallizations. Higher mass reflow temperatures, perhaps after some aging in storage, may reduce pad adhesion even to the extent that the more rigid no-pb solder joints under an imperfectly balanced large component will tend to initiate delamination from the underlying laminate. Potentially more critical, however, because it is even more easily overlooked is further degradation on the shelf or in service afterwards so that the pad, rather than the solder, suddenly becomes the weakest link after some time. In developing tests for such concerns we note that standard peel tests tend to involve rather wide metal strips ( mil, IPC-TM ) and thus are not sufficiently

6 sensitive to address concerns related to moderate and fine pitch assemblies. In general, damage may lead to either opens or shorts. Localized glass-resin debonding, perhaps initiated in hole drilling etc., but enhanced under some of the no-pb assembly conditions discussed above, may for example affect the insulation between closely spaced vias and associated conductors. No-Pb assembly is also likely to lead to enhanced board/card distortion and warpage. As they are heated higher above the laminate T g the multilayer structures are likely to warp more, both temporarily at the high temperature and permanently after subsequent cool-down. Enhanced warpage at reflow may affect assembly yields, and permanent distortion may be a problem in subsequent assembly (double sided or if the card is part of a component) and repair. In addition, of course, distortion may also reflect a greater load on, or already initiated damage to, metallizations. Again, the presence of both through-hole and surface mount components may strongly enhance such problems. Certainly, an underfilled flip chip or CSP is likely to exacerbate distortion in subsequent mass reflows or (selective) wave soldering. Finally, repeated high temperature reflows may lead to degradation in terms of a reduced T g, decomposition temperature or even mechanical properties. We need to consider not only laminates but also solder masks. Solder Masks usually have lower T g ( C) and higher CTE (60-80ppm/C). Thermal degradation may lead to reduced adhesion to the underlying laminate, reduced solvent resistance, or reduced encapsulant or mold adhesion to the surface. Of particular practical concern is the resistance to solder wicking along the copper features. Many people tend to focus on popcorning / delamination as addressed for components in IPC/JEDEC J-STD-020B. The test (moisture exposure followed by 3 reflows) becomes increasingly severe as the peak reflow temperature increases. A 'rule of thumb' in the industry is supposedly that each 10 o C increase reduces the achievable JEDEC level by one. Anyway, like for other adhesive interfaces, we need to recognize that this test is empirical and does not necessarily address the actual damage mechanisms correctly. For example, the procedure assumes that you can 'cancel' the effect of a moisture exposure (without reflow) by simply baking out again. We know, however, that aging and moisture exposure may leave permanent degradation of epoxies even after bake. Aging and moisture exposure will also tend to weaken chemical interfaces, organic bonds, and cross-linking even if not enough to allow popcorning in subsequent reflow. Similarly, we believe that reflows may weaken the interfaces and initiate latent damage as well. A somewhat special concern involves bonding of adhesives during or after no-pb assembly. The higher reflow temperatures might simply modify or contaminate the solder mask surface, thus affecting the adhesion of subsequently deposited die attach adhesives or flip chip underfills. Volatiles evolved in reflow may certainly contaminate a flip chip surface and affect subsequent underfill adhesion there. Even prebaking does not always prevent enhanced outgassing and voiding in no-flow underfills at the higher

7 reflow temperatures involved. CURRENT PCB/ASSEMBLY TESTING Included below is a listing of several of the major, common, commercially available testing capabilities currently employed in the analysis of PCB s to determine both quality of construction and in many cases reliability specific to the circuit board: IST - Innerconnect Stress Testing, typically, a product-specific designed coupon is heated internally by applying DC current. The current is powered onto a circuit net that daisy- chains throughout the entire coupon. Switching the current on and off heats, and subsequently cools, the coupon to predetermined setpoints typically ranging from 260 deg C to room temperature. Repetitively, this thermal cycling induces strain/stress in the plated thru holes and surrounding via structures, which is sensed as a resistance measurement. The number of cycles completed is an assessment of PTH/Via and interconnect performance and bare board reliability. Reference: IPC-TM-650, Acceptability: Typically 500 cycles, but dependent on PWB construction. PCT Pressure Cooker Test or PPOT - Pressure Pot Test, is an empirical reliability assessment to evaluate the ability of a product to withstand severe temperature and humidity conditions. The steam autoclave is the typical instrument used to promote and accelerate corrosion within the test samples, by soaking at 100% relative humidity, and 2 atmospheres (15 PSI) of pressure, as the temperature is controlled at 121 deg C for 168 hours. Failures are monitored typically by resistance readings taken at 48, 96 and hours, as well as end of test. Reference: JESD22-A102-C / EIAJ-IC Acceptability: Passes/Fails after 168 hours. Electrical leakage, attributable to moisture content, must be discerned from true failure mechanisms. LLTS/AATS Liquid to Liquid Thermal Shock/Air to Air Thermal Shock. Either technique, differing primarily by the thermal medium within the test chamber (Air or Liquid) is used to determine the resistance of an assembly or PCB to sudden, drastic changes in temperature. Samples, beginning at room temperature, are exposed and cycled from extremely hot to extremely cold temperatures and back again to ambient within repetitive, predetermined time windows. Varieties of test conditions exist within the reference test methods, dependent on PWB construction and end-use of the electronic assembly. These typically range from 65 deg C to 150 deg C. Samples are normally monitored for resistance changes, continuously during thermal excursions to determine cycles to failure. Reference: JEDEC JESD22-A106, IPC-TM Acceptability: 100 to 500 cycles, dependent on product construction and end use.

8 THB Temperature Humidity Bias (Steady State), differing only from PCT/PPOT testing by the application of bias voltage on the PCB/Assembly and RH/Temp settings, THB testing employs the following, typical, stress conditions: 1000 hours at 85 deg C, 85% RH. The bias voltage applied is usually designed to simulate the conditions of the device in its real-life end use; maximizing variations in the potential levels of the different metallization areas on the component die as much as possible. This is another good candidate method for accelerated corrosion resistance. Reference: JEDEC JESD22-A101-B Acceptability: Passes/Fails after specified test time. HAST - Highly Accelerated Stress Testing, was developed as an alternative to Temperature Humidity Bias (THB) testing as well as being nearly identical to PCT/PPOT testing criteria. Where THB testing takes 1000 hours to complete, HAST results can be attained within 200 hours. Like THB and PCT testing, HAST accelerates corrosion, particularly that of the die metal lines and thin film resistors. HAST however, requires sample preconditioning and is conducted typically with electrical bias 5.5V at 130 deg C and 85% RH for a specified amount of time. It is also used for the reliability assessment of assemblies and PCB s suspected of being prone to corrosion due to ionic contamination. Reference: JEDEC JESD22-A110 Acceptability: Passes/Fails after specified test time. Hi-Pot - or Dielectric Withstanding Voltage, (500V) Reference: IPC-TM-650, Acceptability: Condition A, Passes/Fails based on visual inspection for evidence of dielectric breakdown or whether insulating materials and/ot conductor spaces are adequate. T260/T288 - Time to delamination at 260 or 288 deg C. uses the TMA to measure time to delamination. A 5-gram force is maintained while temperature is ramped up to 260/288 C and held there for 10 minutes. Failure is determined by a measured, permanent thickness increase caused by subsequent blistering/delamination. Reference: IPC-TM Acceptability: Current specifications indicate 5.2 minutes min for T260. Other / Miscellaneous Testing Solder Pot Thermal shock (288C) 10x: defects. Solder float peel strength: (no change after 288C/10 sec) HAST, 100VDC, 96 hours: no change in resistance Humidity effect on capacitance (<10% increase from 0-90%R.H.)

9 High temperature and humidity storage (85/85, 30V bias, 1000 hrs) High temperature storage (150C, 1000hrs) Low temperature storage (-65C, 1000hrs) Solder reflow test (235C, 10s, solderability). TESTING SPECIFICALLY FOR NO-PB Beyond conventional Sn/Pb testing, there has not been much progress towards development of specific Pb-Free analytical methodology. Many of the current Sn/Pb testing techniques still apply to Pb-Free, but it is clear that more can be done to improve specific technique and criteria for evaluation of the thermal extension added to lead-free product. Several of the enhanced analyticals are covered below where simply an upper temperature has been increased or extended: T288 by TMA, IPC test method, Time to Delamination has been developed. Solder float IPC 288C, 10 sec has been developed. Fracture index after 10x floats: wicking length times 2 + crazing length in mils. A typical solder dip test involves moisture preconditioning at 121C/ 100%R.H. for 1, 3 and 6 hours, followed by dipping (submerging) in molten solder at 220C, 250C, and 280C for 5, 10, and 15 sec. In each case the samples are then analyzed for failure mode. A typical solder float test involves preconditioning at 85/85 for long enough to get 50, 75 and 100% saturation, then floating on molten solder at 220C, 250C, and 280C while watching the top for blisters, white spots, etc. The time to such damage is noted. This might be taken to represent wave in some respect. PB-FREE BOARD DAMAGE TEST PLAN A primary concern is the effect of actually populating a board or card with no-pb area array and through-hole components. As discussed above this may strongly exacerbate board/card damage in ways that depend on the specific components and locations. Also, even if present insidious degradation mechanisms may not always be detectable in an unpopulated board. Components exert highly localized mechanical loads on laminate and plating, notably in vias, as well as on solder mask and contact pads through pins, solder joints and underfill. All of this is sensitive to layout, component mechanics, and solder properties. In addition, of course, both mechanical and other weakening (reduced performance) may be sensitive to combinations of product design, aging and actual no-pb assembly process parameters. Notably, non-uniform or local heating in realistic (selective) wave

10 soldering and repair may be more damaging than current accelerated tests. In the long term testing should address both 'general' and HDI applications, i.e. not automatically reject structures that may be sufficient for 'general' applications if such are relevant for those specific structures. Starting out with a moderately thick, multilayer test vehicle as outlined below we shall, however, focus on applications typical of such structures. The plan currently under consideration involves test procedures as outlined below. These tests will, however, be accompanied by mechanistic studies to ensure our understanding of the various damage phenomena and mechanisms. The results are expected to lead to significant revisions of our test procedures as we go. Laminate and Solder Mask Material Pre-Screening Supposedly, laminates have already been characterized by the PCB supplier in terms of a so-called fracture index associated with thermal shock and only materials with a sufficiently high index are considered applicable to no-pb assembly. One might therefore also presume that materials have been inspected for visual damage as reflected in discoloration and blistering. However, we shall not count on any of this. Eventually we propose to pre-screen all laminates and solder masks proposed by suppliers as no-pb compatible, to the extent these are available. This will obviously involve collecting and reviewing available information. For a beginning, however, we recognize that some pre-screening procedures may arise from our initial learning. We therefore plan for the immediate design and acquisition of the first real test structure (below) without any pre-screening before. Pre-screening procedures would of course have to be simple. One might involve 5-10 reflows with a peak temperature of 260 o C or 270 o C followed by visual assessment of damage. We also propose to check for degradations in T g and perhaps enhanced moisture uptake. This step could be based significantly on production scrap structures, if available. We do, however, need to be sensitive to whether a particular performance characteristic may be affected by the specific processing it has undergone. Screening would continue in parallel with further work as new materials are identified and made available, and as new procedures are developed. Test Structures A range of test vehicles will either be acquired as is or specifically designed to identify and address the damage mechanisms of concern. The important criterion is that the vehicle should specifically emphasize problems potentially arising when switching to no- Pb assembly. This means that the vehicle should involve structures and materials that can be expected to perform satisfactorily for Sn/Pb assembly. In fact, a considerable

11 experience and database should preferably exist for corresponding Sn/Pb applications. Notably, the vehicle should not offer any particular challenge to the supplier. It would of course be preferred that some test vehicle would include realistic deviations from perfection such as misregistration of vias, copper thickness or width variations, etc., albeit at a level acceptable for Sn/Pb assembly. If necessary, such deviations might be introduced deliberately to represent variations at a level anticipated across large manufacturing lots. The plan is to include multi layer test vehicles with 5-10 mil thick single-ply layers and thus a relatively high resin content that we would expect to be relatively sensitive to higher reflow temperatures. Efforts should be made to use realistic copper thickness and distribution (both laterally and through the thickness). This is expected to affect the build-up of localized stresses on barrels and IP connections in manufacturing, handling, and cycling. A typical construction would utilize both 1 oz (signal) and 2 oz (P/G) innerlayers is currently planned. When possible test vehicles include insulation resistance test coupons, solder float patterns, daisy-chained via arrays connected by 3 to 8 mil traces on top and bottom surfaces for thermal cycling, and IST coupons. There has also been interest in incorporating populated sites in an IST structure, but we do caution that this would seriously alter the thermal response of the structure to the current loading and thus at the very least require extensive characterization. Preliminary work proposes to use a 256 I/O PBGA as an IST coupon attachable component. It is proposed that different via test patterns include vias down to 6 mil diameter on various pitches down to 0.65mm, allowing for assessment of damage both to the vias themselves and to the often resin rich regions between closely spaced ones. It is emphasized that some of the vias should be connected to realistic ground planes as this offers a particular potential for damage among others in wave soldering. It may also be relevant to include lines routed between arrays of vias on inner signal planes? This should not be tight enough to be a challenge to the supplier, but should represent risks of partial damage in a no-pb reflow which may lead to faster opens or shorts in subsequent cycling. A range of parameter variations should be included for testing. Both DC and pulse plated vias should be tested, as the processes offer quite different copper grain structures. Sn/Cu is proposed as a no-pb alternative to HASL and should be considered. In addition, lamination process parameters should be deliberately varied across a realistic range and the consequences tested for. A number of known defects may also be introduced by deliberately modifying/omitting plating, desmear, etch, and copper clean procedures. Various levels of voiding are for examples easily introduced into the copper. If possible, defects will be introduced into some test vehicles at a level still considered acceptable for Sn/Pb applications and the consequences tested for.

12 Test Board: The first Pb-Free test vehicle designed and produced to promote, enhance, and evaluate the aforementioned failure mechanisms is referred to as the Lead Free Test Board (LFTB-1). The Lead Free Test Board (LFTB-1) is a relatively thick (0.093 ), multilayer (12 layer), test vehicle designed specifically for use in evaluating robustness and process sensitivity of various laminate and dielectric materials, thru hole and via construction, surface patterns, and State-of-the-Art component attachment sites. The design incorporates unique test structures that provide visual, mechanical, chemical, electrical and physical evaluation sites, defining data collection and yielding assignment of overall board performance. Ultimately, the data generated from this test board will provide design, construction, and performance information as well as baseline reliability data for lead free assembly. The functional design of this board was developed by Universal Instruments SMT Lab as a collaborative assortment of project specific issues and requests submitted by numerous Area Array 2004 Consortium members with regards to lead free assembly. As the understanding of material failure mechanisms improves, and the availability of planned production circuits dwindles, it was deemed necessary to pursue all potential sources for acquisition of live product through consortium membership contributions. Many member companies have submitted product for lead free evaluations (multiple reflows, thermal analysis, thermal shock, material characterizations, and subsequent microsectional analysis). Significant data has been collected to date, from these contributions, which has yielded an overall indication of specific material survivability and robustness in Pb-Free applications. Conversely, there have been contributions which represent current material selections that do not survive lead free temperature excursion. To date we have tested 9 resin systems on 20 different supplier s materials. In addition to live product submissions, UIC SMT Lab has been asked to participate in external Design of Experiments (DOE s) where varied lead free, certified ROHS, and certified lead free PCB materials are being used to produce boards which can survive the now famous 260 C Peak Reflow or NEMI profile. We are currently involved with a Material Test Vehicle (MATV) that was designed by Sanmina-SCI, yet includes many of the test structures and component attach sites originally designed into the LFTB-1. We are working with thick, 32 layer product and a thinner 0.093, 16 layer product. Initial evaluations of some Phenolic cured epoxy systems have revealed considerably less robustness than initially promised in sales literature. Components: It is as said critical that parts of the test board be populated with especially selected components. It is proposed that these include a press fit connector offered by Ericsson, as well as possibly one of the compliant pin connectors suggested by IBM (Amp z-pak, FCI AirMax, Teradyne VHDM, Tyco HM-Zd)? In addition, we propose to include a DIP16 and some large through-hole mounted package such as a power transformer on a wave-soldering coupon. As far as surface mounted components we propose to include 2512s, a 1064 I/O area array flip chip, and the 256 I/O BGA which we have already seen to damage some boards in no-pb assembly. In addition, we propose to include a relatively rigid large

13 BGA such as a 35mm package with a 22-23mm chip inside. If possible, commercial samples of this may be procured, but we also propose to build our own generic BGA with the same footprint and daisy chaining. This allows the daisy-chain to bypass the chip and thus not risk internal package failure in testing, but even more importantly is allows the production of vehicles with specifically desired thermomechanical properties. In general, the surface mounted components should be placed as near as possible to and/or over realistic via chains to assess their effects of damage to these. At least one of the large BGA s should also be attached to via-in-pad structures as this may seriously affect local loads on these. Characterization Test vehicles will of course be characterized when initially received. Properties of interest include stiffness and Coefficient of Thermal Expansion (CTE) versus temperature, particularly in the thickness (z-expansion) direction. We shall also measure properties such as glass transition and decomposition/degradation temperatures. In general, we shall also quantify the as-received response of samples to the relevant tests below for comparison with the same after preconditioning. Preconditioning (Damage) Preconditioning procedures that will be considered for potential damage to the boards include the following. One or several cycles of humidity/moisture exposure (such as 100%R.H. for 48 hours, or a week at 50C/80%R.H.) and bake-out (such as 125C for 48hrs). A single cycle is probably the most realistic as far as preconditioning before assembly is concerned. Some samples should also be exposed to longer-term storage on the shelf. We may also consider intermediate humidity/bake out cycles after first assembly steps, but before wave soldering for example. Certainly, humidity exposure and aging after final assembly will be included as an important preconditioning step. Complete preconditioning will of course include realistic mass reflows followed by wave soldering, perhaps selective soldering, and repair. Parameters and combinations will be varied to help understand the effects of the individual ones on damage. Mass reflow profiles will include peak temperatures of 220C (for reference), 260C and 275C (it may be unrealistic to always count on temperatures remaining below this). Both short (45 sec above liquidus) and long (180 sec) profiles with and without a soak will be considered as well. Effects of single as well as five and ten repeated reflows will be assessed. Reflows will include actual component attachment whenever relevant. Preheat and solder bath temperatures, as well as other wave soldering parameters, will also be varied, and in this case the presence of the components is known to be critical. Press fit and compliant pin connectors will be inserted at the appropriate point.

14 Aggressive cleaning may contribute strongly to the further degradation of damaged boards. Manual repair with a handheld point-soldering tool may in fact be the most damaging of them all, but repairs with both a Metcal tool and a semi-automatic rework station with various nozzles will be considered. Importantly, as said, subsequent humidity exposure and aging on the shelf and in service may contribute strongly to degradation of boards initially (but undetectably) damaged in reflow. This may happen before or after handling in shipment and/or a final repair. Different sequences of repair, mechanical stressing, and moisture exposure will therefore be included as well. TESTS/RESPONSE PARAMETERS Damage will be assessed in terms of directly detectable issues and reduced performance or failure in various tests. The latter would include some of the current tests referred to above, such as liquid-to-liquid thermal shock, air-to-air thermal cycling and IST. Directly detectable would, among others, be a reduced T g, enhanced moisture absorption, or degradation in dielectric constant or loss, as well as visible or measurable delamination or warpage. We would expect the time to delamination at 260C and 288C to degrade, but in itself, this is not an indication of a problem. Emphasis will be on damage of direct concern. Board (solder mask) surfaces will be inspected for visual appearance, and samples will obviously be cross-sectioned to inspect for IP separation and partial barrel cracks, etc. Pieces will also be analyzed by TGA, DMA, and DSC for changes in resin properties. Structures will be characterized in terms of insulation, etc. Initially invisible defects may, however, only be detectable as leading to earlier failure in subsequent thermal cycling. Whether this should be a real concern is easiest to assess for populated boards the board should never become the weakest link. Populated boards will therefore be cycled thermally and/or mechanically (torque) or tested in mechanical shock (drop) or deformation (bend). Degradations in solder mask adhesion may be quantified in standard peel tests, but we shall also test for solder penetration from exposed pads along covered traces. We shall also test for adhesion of a typical die attach adhesive and a flip chip underfill to solder mask and exposed laminate surfaces. As far as contact pad adhesion is concerned, standard peel tests such as IPC-TM are of little relevance, particularly for fine components. Degradation in adhesion, particularly if enhanced by ambient exposure and aging, is likely to progress inwards from the individual pad edges so that testing of a mil wide strip will be insensitive to preconditioning that may be fatal to a 3 mil wide trace. A more relevant test involving solder attach to individual pads will therefore be developed and used.