If it moves, chop it in half, then simulate it

Transcription

1 Interactions of Double Patterning Technology with wafer processing, OPC and design flows Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins Synopsys Vincent Wiaux, Staf Verhaegen IMEC, Leuven, Belgium If it moves, chop it in half, then simulate it Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins Synopsys Vincent Wiaux, Staf Verhaegen IMEC, Leuven, Belgium 1

2 Double Patterning additive 1 st trench imaging Hard Mask etch Resist/BARC strip Resist BARC HM LowK Etch stop. 2 nd trench imaging Hard Mask etch Resist/BARC strip transfer to dielectric 26 Synopsys, Inc. (3) See V. Wiaux , next session Outline DPT Lithography & Process Window DPT Mask Synthesis DPT Physical Design Conclusions 26 Synopsys, Inc. (4) 2

3 Lithography Need 3-35nm etched CD ~7nm min final pitch Need highly controlled 14nm pitch single exposure litho PW budget: 5% EL, 1nm DOF RET? No space for retargeting or AFs Need litho sizing + etch downsize Patterning strategy: Poly: ~45nm litho CD (~32nm gen) Cont: ~55nm litho CD (~32nm gen) M1: new resist or ~6nm litho CD All layers require 15nm+ etch shrink Standard for Poly, new for Cont & M1 26 Synopsys, Inc. (5) Min allowed space vs. # DPT conflicts nm upsize 5nm upsize 1nm upsize 15nm upsize Upsizing reduces single exposure litho space. Creates more DPT interactions & conflicts. 26 Synopsys, Inc. (6) 3

4 DPT litho/etch topography 1: n16_1_polysi_depo.tdr 2: n16_2_hm_depo.tdr 3: n16_3_arc_depo.tdr 4: n16_4_resist1.tdr : n16_6_trim1.tdr 6: n16_7_arc1.tdr 7: n16_8_hm.tdr 8: n16_9_strip.tdr : n16_1_lpcvd.tdr 1: n16_11_reflow.tdr 11: n16_12_resist2.tdr 12: n16_13_trim2.tdr Y[um m] Y[um m] Y[um m] Y[um m] : n16_14_arc2.tdr 14: n16_15_poly.tdr 15: n16_16.tdr 26 Synopsys, Inc. (7) Planar vs. Non-planar results Litho2 no Etch1 pattern CD bottom 55nm Litho2 over Etch1 pattern CD bottom 57nm+ 26 Synopsys, Inc. (8) 4

5 DPT Mask Synthesis 26 Synopsys, Inc. (9) DPT Decomposition/OPC/Verify Functions: decomposition (split & color), RET, OPC and error identification. High yield Split creates OPC/RET friendly layouts OPC creates yield friendly wafer patterns through overlay, focus, & dose variations Very high accuracy/predictive OPC models Symmetry, density uniformity Fast turnaround Limits complexity/iterations in decomposition algorithms Must successfully convert all DPT compliant designs 26 Synopsys, Inc. (1) 5

6 Logic contact split example Green lines show network of features to be decomposed Red lines show coloring violations where redesign is necessary. 1D arrays, 2by2 arrays, on grid contact are DPT friendly. 26 Synopsys, Inc. (11) Smart Coloring for Violations Line-end control critical Overlap quality Decomposition must ensure OPC can meet very tight accuracy tolerances - line-end control now critical 26 Synopsys, Inc. (12) 6

7 Yield & process window issues Pinch, sharp corner, overlay sensitive 26 Synopsys, Inc. (13) Std. round corner current density 22nm node Cu feature, max J ~ Synopsys, Inc. (14) 7

8 DPT square corner current density 22nm node Cu feature, max J ~2.3 J is ~2X higher with sharp corners. Black s electromigration Eq.: Mean time to failure (MTTF) can decrease by 3-4X! Local stress at sharp corner could further accelerate failure. 26 Synopsys, Inc. (15) Decomposition algorithm differences Basic approach More complex algorithm DRC violation Small poorly printed polygon Asymmetric with printing issues High # of cuts, risky overlaps Symmetric, fewer cuts, easier to OPC -> better yield 26 Synopsys, Inc. (16) See C. Cork , thurs. PM 8

9 Need for model based decomposition - Sometimes need model to predict and avoid errors MRC limits OPC at LE Looks fine after split but has error on wafer Split Option 1 DPT-aware OPC Looks bad after split but is good on wafer Split Option 2 26 Synopsys, Inc. (17) DPT physical design flow 26 Synopsys, Inc. (18) 9

10 Double Patterning in Design Flow Design Task Std cell creation & characterization Custom layout Place & route Tapeout signoff (DRC) Goals Minimize cell width Maximize timing/leakage g performance No design rule or DPT violations Minimize area No design rule or DPT violations Maximize routability No design rule or DPT violations No design rule or DPT violations in final design 26 Synopsys, Inc. (19) DPT standard cell generation flow GDS Layout Std cell tool GDS Import Layout Rules External analysis DPT Decomp Tool Error Reports FixRule 1 FixRule 2 FixRule N Tune Layout Std cell Setup Design Rules Corrected Layout 26 Synopsys, Inc. (2) 1

11 DPT Correction Flow Example: aoi22x1 with 2 METAL1 conflicts Source GDS GDS analyzed for conflicts 2 Conflicts on METAL1 found Pass 1 Conflicts corrected and cell optimized Corrected GDS 1 New Conflict Pass 2 Conflicts corrected and cell optimized Corrected GDS POLY & METAL1 DPT Analysis Results 26 Synopsys, Inc. (21) DPT standard cell library migration Took a traditional standard cell library and converted to a DPT clean library Made reasonable min-space assumptions for DPT 7 unique standard cells Compared cell area before and after conversion Results: Area shrunk ~1% after conversion (!?) 2 possible reasons A) DPT avoids halation rules min space OK B) Compaction engine improvements since library created Initial conclusion: Area increase is small inside Std cells 26 Synopsys, Inc. (22) 11

12 DPT hot spots in routed metals - typically metal2+ but also on metal1 Different circuit portions on Metal2 internally designed layout Simpler odd-cycle DPT hot Spots can be automatically ti detected using rules. Most can be eliminated by slightly modifying the design rules. This type of error accounts for ~7% of errors in routed metal. 26 Synopsys, Inc. (23) Complex DPT routing hot spots Those situations are too complicated for rules to detect. Must be found using DPT checks. These are passed to auto-fix routine for local jumper or ripup and reroute. These represent ~3% of errors in layouts analyzed. 26 Synopsys, Inc. (24) 12

13 Example: jumper to avoid DPT conflict Metal2 DPT conflict found & jumper section identified. Metal3 landing gpads & vias placed Part of line causing odd cycle in Metal2 was removed using modified DFM auto-fix flow. 26 Synopsys, Inc. (25) Example: jumper to avoid DPT conflict -2 New Vias and connection inserted in Metal4 Metal2 DPT conflict removed by jumper This DPT conflict disappears but others remain to be fixed. 26 Synopsys, Inc. (26) 13

14 Summary and Conclusions Litho CD control requires significant upsizing of target litho patterns Implications for resist, etch & DPT friendly layout DPT has new circuit failure modes to control E.g., corner rounding, overlap & line-end position Complex algorithms improve area, effort & yield E.g., symmetry, error reduction, model-based decomposition Need alignment of DPT methods in design & in mask synthesis to avoid DPT issues being found only at mask data verification. Demonstrated automated DPT clean layout creation 26 Synopsys, Inc. (27) Acknowledgements Ben Painter, Martin Drapeau, Brian Ward, Stephen Jang, Xiaopeng Xu: Synopsys y Eric Hendrickx: IMEC Will Conley: Freescale 26 Synopsys, Inc. (28) 14

15 Interesting backup slides if time 26 Synopsys, Inc. (29) 3 color DPT? C. Cork. PMJ Synopsys, Inc. (3) 15

16 Tone Inversion Example SRAM Positive Tone Many Coloring Violations Negative Tone No coloring violations Remapping the layout problem can solve DPT errors 26 Synopsys, Inc. (31) DPT friendly Std cell boundaries Placed Std cells are DPT friendly if: - layers are gridded and single CD at boundary, OR - single color is < ½ min single expose space to boundary, OR - only left or right has multiple colors near boundary 26 Synopsys, Inc. (32) 16

17 DPT friendly Place & Route flow Std P&R layout DPT Prevention Rules ICC Detail route Metal fill For each ICC Switch Box Local DPTdecomposition (skip if 1 st time) For each DPT Hot Spot Break Odd cycle by removing part of line DPT Error Rules Yes Try to find a Jumper No ICC Convergence Report Full chip DPTdecomposition ICC Switch Box Mark for Reroute 26 Synopsys, Inc. (33) 17