Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga )

Size: px
Start display at page:

Download "Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga )"

Transcription

1 Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga ) Henry M.W. Sze, Marc Papageorge ASAT Limited 14th Floor, QPL Industrial Building, 138 Texaco Road, Tseun Wan, Hong Kong Phone : ; Fax : henry_sze@qplhk.com ABSTRACT Market demand for thin, small and light electronic packaging is on the increase in recent years. This is primarily driven by space limitation in portable computing and consumer products. Fine pitch ball grid array (fpbga ) offers competitive alternative in package miniaturization to true chip scale packaging to meet such demands. This paper outlines encapsulation technique selection, characterization and reliability for fpbga. Both transfer molding and liquid encapsulation techniques were evaluated. Transfer molding technique was selected due to better encapsulation thickness control and lower array warpage. Mold simulation followed by actual mold process characterization was performed. Package reliability equivalent to or surpassed existing PBGA was achieved. The reliability results are outlined in this paper. 1.0 INTRODUCTION According to a semiconductor market research survey (BPA, 1997), 95% of integrated circuit packages had I/O of less than 100 in the year It is estimated that about 90% of integrated circuit packages in the year 2006 will have I/O count of less than 100. This represents a potential electronic packaging market in applying ball grid array technology to satisfy this increasing market demand in electronic package performance and miniaturization. Such demands are reflected on a recent survey (ETP, 1997) that chip scale package (CSP) will grow from 7 million units to 3.5 billion units in the year With market demand in high performance in smaller package, using near-chip and chip scale packages in these low I/O integrated circuit packages will satisfy these demands. Fine pitch ball grid array (fpbga ) is a LBGA/LFBGA family by JEDEC s definition. It is a near-chip scale package type. This is a cost-effective packaging option for integrated circuit devices for low I/O count ranging from 24 to 208 and for medium I/O count up to 400. This will meet today s market requirement for increase performance in small, light, and thin package configurations. Fine pitch BGA (fpbga ) utilizes established PBGA technology. It offers low risk for new product introduction and high potential for reduced time to market capability. It also offers die design revision flexibility without changing substrate design for surface mount. Moreover, it offers reliability equivalent to or surpasses current PBGA package reliability. ASAT LTD.,Hong Kong Page : 1

2 There are two major differences in assembly process flow (Figure 1) between PBGA and fpbga. They are the encapsulation process and the singulation process. ASAT s fpbga package utilizes a saw process to singulate multiple units from a large array whereas PBGA employs either punch or routing process on a single unit. Array package for fpbga is a challenge for encapsulation due to its thin mold profile, multi-chip arrangement and large array area. This paper outlines how the encapsulation process is selected and characterized. The package reliability performance is also included in this paper. Die Attach fpbga PBGA Wire Bond 1) Thin Mold Profile < 1.0mm 2) Large mold cavity 3) Multi-chip (4 to 48) Encapsulation 1) Mold thickness > 1.0mm 2) Small mold cavity 3) Multi-chip (3 maximum) Solder Bumping Multiple units in large array format singulated using a saw process. Singulation Single unit by either a routing process or a punch process. Figure 1 : Ball Grid Array Package Assembly Process Flow 2.0 ENCAPSULATION SELECTION Transfer molding and liquid encapsulation are the most common encapsulation techniques in BGA assembly today. Direct comparison of these two techniques is given in Table 1 below. Based on the information given, transfer molding is the obvious choice for array package encapsulation technique. Table 1 : Comparison between Transfer Molding and Liquid Encapsulation Transfer Molding Liquid Encapsulation 1. Thickness control Excellent Fair 2. Array warpage control Good (low shrinkage compound) Fair (glob top material) 3. Tooling cost Medium Low to none 4. Productivity (UPH) High Medium 5. Water adsorption (85%/85%RH/72 hrs) 0.3% 0.6% Encapsulation thickness control is superior in transfer molding methods when compared to liquid encapsulation. This is because epoxy thickness is predefined accurately by the mold cavity. Liquid encapsulation is less accurate in thickness control due to epoxy shrinkage of glob top material and machine dispensing accuracy. Assembly process benchmarking was conducted to characterize both encapsulation methods for array warpage control. Array warpage using liquid encapsulation was found to be four times greater than transfer molding. This is due to higher shrinkage properties of the glob top material. ASAT LTD.,Hong Kong Page : 2

3 The average warpage for transfer molding is 60 microns compared to 280 microns for liquid encapsulation on the same array size. This would create potential manufacturability and quality problems for solder sphere placement process as well as singulation process. Based on the above comparison, it is obvious transfer molding is the preferred encapsulation technique for array warpage control and finished product quality. 3.0 ENCAPSULATION CHARACTERIZATION Transfer molding of any cavity size and die configuration can be characterized by computational fluid dynamics (CFD) using commercially available simulation software packages. It is a useful engineering tool in establishing initial understanding of system variables effect on any physical and chemical process. Transfer molding process of array package such as fpbga can be characterized first by using such simulation software package. There are three significant factors to be evaluated in this array package simulation. They are die thickness, die size and die array arrangement. These were defined as critical factors at initial stage of product quality planning. They are critical because they may affect encapsulation process yield as a result of thin mold profile and large mold cavity size requirement of fpbga package. Having a thin mold profile would require die thickness to be thin. In today s semiconductor assembly industry, incoming wafer with 200-mm diameter and 450 µm thick is common. Wafer thickness requirement for thin profile transfer molding application can be first established using mold flow simulation software. Two die thickness with different die array configurations formed basis of mold flow simulation (FICO, 1997). Die with thickness greater than 410 µm is considered as thick. Die with thickness smaller than 410 µm is considered as thin. Figure 2 shows two different die array configurations to be used in the simulation. The effect of die thickness on mold compound flow can be noted in Figures 3 and 4. Figure 2 : Die Configurations for Mold Flow Simulation ASAT LTD.,Hong Kong Page : 3

4 Figure 3 : Mold Flow Pattern for Thick Die Configuration (4 Up Array) Figure 4 : Mold Flow Pattern for Thick Die Configuration (20 Up Array) Thicker die would reduce effective flow area above and around the die due to increased flow resistance. Figures 3 and 4 show exactly the modeled case. Mold compound flow was found to be slower in the area above the die when bottom gate is used compared to top gate. This unbalanced flow phenomenon was resulted from the die being thick in relation to the mold cavity. Therefore, a high possibility of external voids could occur above the die. This is as shown in Figure 5 where external voids are predicted. In order to eliminate encapsulation voiding, thinner die of (< 410 µm) is required for thin profile (< 1.0mm) molding. Simulation results using die thickness of less than 410 µm are shown in Figure 6 and 7. Both figures showed balanced flow front in comparison to Figures 3 and 4. The analysis was conducted for both top and bottom gating with similar results. Figure 8 shows no void occurrence above the die. This was confirmed by actual molding using thin die of less than 410 µm. ASAT LTD.,Hong Kong Page : 4

5 Figure 5 : Mold Voids Prediction for Thick Die Configuration Figure 6 : Mold Flow Pattern for Thin Die Configuration (4 Up Array) Figure 7 : Mold Flow Pattern for Thin Die Configuration (20 Up Array) ASAT LTD.,Hong Kong Page : 5

6 Figure 8 : Mold Void Prediction for Thin Die Configuration 4.0 PACKAGE RELIABILITY Package level reliability can be classified into six levels according to JEDEC standard (test method A112-A). Table 2 shows various JEDEC levels that the package can be classified under. This indicates floor life moisture susceptibility prior to surface mount operation. It is normally expected that semiconductor first level assembly operations would achieve at least a JEDEC level 3 classification for their products. Table 2 : JEDEC Moisture Sensitivity Level Classification JEDEC Floor Life Soak Requirement Level (Time) Time Condition 1 Unlimited 168 Hours 85 C / 85% RH 2 1 Year 168 Hours 85 C / 60% RH Hours 192 Hours 30 C / 60% RH 4 72 Hours 96 Hours 30 C / 60% RH 5 24 Hours 48 Hours 30 C / 60% RH 6 6 Hours 6 Hours 30 C / 60% RH ASAT' fpbga utilizes existing PBGA assembly technology using the same construction material as PBGA. It is expected that fpbga package reliability will be able to meet at least equivalent to PBGA s JEDEC level 3 classification. It is also possible that it may surpass PBGA s JEDEC level 3 classification due to the smaller body size of fpbga (6mm to 15mm) in comparison to PBGA (23mm to 35mm). Table 3 shows ASAT s package level reliability achieved to date. It is as predicted that the fpbga package performed to minimum JEDEC level 3 classification. ASAT LTD.,Hong Kong Page : 6

7 Table 3 : Package Level Reliability Data (13mm 144, 10mm 100, 8mm 64 & 6mm 36) Condition Results (Fail / Pass) MSL 2 85 C / 60% RH / 168 Hrs 0 / 385 (5 lots) MSL 3 30 C / 60% RH / 192 Hrs 0 / 308 (4 lots) Autoclave 121 C / 100% RH / 168 Hrs / 1 ATM 0 / 693 Temperature Cycle -65 C to 150 C, 1000 cycles 0 / 693 Thermal Shock -65 C to 150 C, 300 cycles 0 / 693 HTSL 150 C, 500 Hrs 0 / 693 HAST 130 C / 85% RH / 50 and 200 Hrs 0 / CONCLUSION fpbga package is a near chip-scale package. It was developed from existing PBGA assembly technology using the same construction material. The challenge for encapsulation was in its thin mold profile and multiple chip configurations. Transfer molding methodology is the preferred choice for fpbga. This is due to enhanced encapsulation thickness control and reduced array warpage for a given area compared to liquid encapsulation method. When thin die of less than 410 µm is used, the transfer molding process is favored. This is due to a balanced flow front, reduced flow turbulence and zero voiding. The package level reliability for the fpbga achieved a minimum of JEDEC level 3 and passed all the required environmental tests. 6.0 REFERENCES Advanced IC Packaging Markets and Trends, Electronic Trend Publication, California, November BPA Survey, ESEC Road show Booklet, October Mcllellan, N., Papageorge, M., Fan, N., CSP Reliability : Meeting the Challenges, Advanced Packaging, February Roerdink, G., ASAT CSPBGA Simulation Report, Fico Molding Systems BV, November Sze, H., FPBGA Molding Process Evaluation, ASAT Internal Report, January ASAT LTD.,Hong Kong Page : 7

Chips Face-up Panelization Approach For Fan-out Packaging

Chips Face-up Panelization Approach For Fan-out Packaging Chips Face-up Panelization Approach For Fan-out Packaging Oct. 15, 2015 B. Rogers, D. Sanchez, C. Bishop, C. Sandstrom, C. Scanlan, TOlson T. REV A Background on FOWLP Fan-Out Wafer Level Packaging o Chips

More information

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017 Amkor Technology, Inc. White Paper Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017 Abstract Expanding its ChipArray Ball Grid Array (CABGA) package form factor miniaturization

More information

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package Basic PCB Level Assembly Process Methodology for 3D Package-on-Package Vern Solberg STC-Madison Madison, Wisconsin USA Abstract The motivation for developing higher density IC packaging continues to be

More information

Failure Modes in Wire bonded and Flip Chip Packages

Failure Modes in Wire bonded and Flip Chip Packages Failure Modes in Wire bonded and Flip Chip Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, Ca. 92121 mbora@psemi.com Abstract The growth of portable and wireless products is driving the miniaturization

More information

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY B. Rogers, C. Scanlan, and T. Olson Deca Technologies, Inc. Tempe, AZ USA boyd.rogers@decatechnologies.com ABSTRACT Fan-Out Wafer-Level Packaging

More information

MTS Semiconductor Solution

MTS Semiconductor Solution MTS 0 unplanned down time Solution Lowest operating Cost Solution Energy saving Solution Equipment Fine Pitch and UPH Upgrade solution Quality & Yield Improvement Solution Reliability Enhancement Solution

More information

Advancements In Packaging Technology Driven By Global Market Return. M. G. Todd

Advancements In Packaging Technology Driven By Global Market Return. M. G. Todd Advancements In Packaging Technology Driven By Global Market Return M. G. Todd Electronic Materials, Henkel Corporation, Irvine, California 92618, USA Recently, the focus of attention in the IC packaging

More information

EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS

EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS As originally published in the SMTA Proceedings. EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS Neil Poole, Ph.D., Elvira Vasquez, and Brian J. Toleno, Ph.D. Henkel Electronic

More information

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation

Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes. Jason Chou and Sze Pei Lim Indium Corporation Advanced Analytical Techniques for Semiconductor Assembly Materials and Processes Jason Chou and Sze Pei Lim Indium Corporation Agenda Company introduction Semiconductor assembly roadmap challenges Fine

More information

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Institute of Microelectronics

More information

Package Solutions and Innovations

Package Solutions and Innovations Package Solutions and Innovations with Compression Molding IEEE SVC CPMT Aug 2015 Presented by C.H. Ang Towa USA Company Profile www.cpmt.org/scv 1 Corporate Overview Company: Towa Corp., Kyoto Japan Established:

More information

White Paper Quality and Reliability Challenges for Package on Package. By Craig Hillman and Randy Kong

White Paper Quality and Reliability Challenges for Package on Package. By Craig Hillman and Randy Kong White Paper Quality and Reliability Challenges for Package on Package By Craig Hillman and Randy Kong Background Semiconductor technology advances have been fulfilling Moore s law for many decades. However,

More information

3D-WLCSP Package Technology: Processing and Reliability Characterization

3D-WLCSP Package Technology: Processing and Reliability Characterization 3D-WLCSP Package Technology: Processing and Reliability Characterization, Paul N. Houston, Brian Lewis, Fei Xie, Ph.D., Zhaozhi Li, Ph.D.* ENGENT Inc. * Auburn University ENGENT, Inc. 2012 1 Outline Packaging

More information

IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION

IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION Frank Grano, Felix Bruno Huntsville, AL Dana Korf, Eamon O Keeffe San Jose, CA Cheryl Kelley Salem, NH Joint Paper by Sanmina-SCI Corporation EMS, GTS

More information

"ewlb Technology: Advanced Semiconductor Packaging Solutions"

ewlb Technology: Advanced Semiconductor Packaging Solutions "ewlb Technology: Advanced Semiconductor Packaging Solutions" by Sharma Gaurav@, S.W. Yoon, Yap Yok Mian, Shanmugam Karthik, Yaojian Lin, Pandi C. Marimuthu and Yeong J. Lee* STATS ChipPAC Ltd. 5 Yishun

More information

Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology

Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology by Meenakshi Prashant, Seung Wook Yoon, Yaojian LIN and Pandi C. Marimuthu STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442

More information

Design for Flip-Chip and Chip-Size Package Technology

Design for Flip-Chip and Chip-Size Package Technology Design for Flip-Chip and Chip-Size Package Technology Vern Solberg Solberg Technology Consulting Madison, Wisconsin Abstract As new generations of electronic products emerge they often surpass the capability

More information

Selection and Application of Board Level Underfill Materials

Selection and Application of Board Level Underfill Materials Selection and Application of Board Level Underfill Materials Developed by the Underfill Materials Design, Selection and Process Task Group (5-24f) of the Assembly and Joining Committee (5-20) of IPC Supersedes:

More information

Customizing Processes for Hermetic Assembly Of Devices Designed for Plastic Packages (1 of 3)

Customizing Processes for Hermetic Assembly Of Devices Designed for Plastic Packages (1 of 3) Customizing Processes for Hermetic Assembly Of Devices Designed for Plastic Packages (1 of 3) Charlie C. Megia Golden Altos Corporation 402 South Hillview Drive, Milpitas, CA 95035 cmegia@goldenaltos.com

More information

Recent Advances in Die Attach Film

Recent Advances in Die Attach Film Recent Advances in Die Attach Film Frederick Lo, Maurice Leblon, Richard Amigh, and Kevin Chung. AI Technology, Inc. 70 Washington Road, Princeton Junction, NJ 08550 www.aitechnology.com Abstract: The

More information

The Packaging and Reliability Qualification of MEMS Resonator Devices

The Packaging and Reliability Qualification of MEMS Resonator Devices The Packaging and Reliability Qualification of MEMS Resonator Devices Pavan Gupta Vice President, Operations Yin-Chen Lu, Preston Galle Quartz and MEMS Oscillators source: www.ecliptek.com Quartz Oscillators:

More information

Semiconductor IC Packaging Technology Challenges: The Next Five Years

Semiconductor IC Packaging Technology Challenges: The Next Five Years SPAY025 May 2006 White Paper Mario A. Bolanos, Director Semiconductor Group Packaging Technology Development, Texas Instruments In the era of communications and entertainment, growth of consumer electronics

More information

Material Selection and Parameter Optimization for Reliable TMV Pop Assembly

Material Selection and Parameter Optimization for Reliable TMV Pop Assembly Selection and Parameter Optimization for Reliable TMV Pop Assembly Brian Roggeman, David Vicari Universal Instruments Corp. Binghamton, NY, USA Roggeman@uic.com Martin Anselm, Ph.D. - S09_02.doc Lee Smith,

More information

Alternative Approaches to 3-Dimensional Packaging and Interconnection

Alternative Approaches to 3-Dimensional Packaging and Interconnection Alternative Approaches to 3-Dimensional Packaging and Interconnection Joseph Fjelstad SiliconPipe, Inc. www.sipipe.com IC Packaging a Technology in Transition In the past, IC packaging has been considered

More information

Development of Exposed Die Large Body to Die Size Ratio Wafer Level Package Technology

Development of Exposed Die Large Body to Die Size Ratio Wafer Level Package Technology Development of Exposed Die Large Body to Die Size Ratio Wafer Level Package Technology by J. Osenbach 1, S. Emerich1, L. Golick1, S. Cate 2, M. Chan3, S.W. Yoon 3, Y.J. Lin 4 & K. Wong 5, 1LSI Corporation

More information

Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima

Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima Novel Materials and Activities for Next Generation Package Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima 1. Activities of Packaging Solution Center 2. Novel Materials for Next Gen.

More information

Copper Wire Packaging Reliability for Automotive and High Voltage

Copper Wire Packaging Reliability for Automotive and High Voltage Copper Wire Packaging Reliability for Automotive and High Voltage Tu Anh Tran AMPG Package Technology Manager Aug.11.2015 TM External Use Agenda New Automotive Environments Wire Bond Interconnect Selection

More information

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications

Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Lead-Free Solder Bump Technologies for Flip-Chip Packaging Applications Zaheed S. Karim 1 and Jim Martin 2 1 Advanced Interconnect Technology Ltd. 1901 Sunley Centre, 9 Wing Yin Street, Tsuen Wan, Hong

More information

System in Package: Identified Technology Needs from the 2004 inemi Roadmap

System in Package: Identified Technology Needs from the 2004 inemi Roadmap System in Package: Identified Technology Needs from the 2004 inemi Roadmap James Mark Bird Amkor Technology Inc System in package (SiP) technology has grown significantly in the past several years. It

More information

23 rd ASEMEP National Technical Symposium

23 rd ASEMEP National Technical Symposium THE EFFECT OF GLUE BOND LINE THICKNESS (BLT) AND FILLET HEIGHT ON INTERFACE DELAMINATION Raymund Y. Agustin Janet M. Jucar Jefferson S. Talledo Corporate Packaging & Automation/ Q&R STMicroelectronics,

More information

Development of System in Package

Development of System in Package Development of System in Package In recent years, there has been a demand to offer increasingly enhanced performance for a SiP that implements downsized and lower-profile chips at lower cost. This article

More information

Fairchild Semiconductor Application Note January 2001 Revised September Using BGA Packages

Fairchild Semiconductor Application Note January 2001 Revised September Using BGA Packages Introduction AN-5026 Demanding space and weight requirements of personal computing and portable electronic equipment has led to many innovations in IC packaging. Combining the right interface and logic

More information

Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages

Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages by Seng Guan Chow, Yaojian Lin, Bernard Adams * and Seung Wook Yoon** STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442

More information

Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C

Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C EPRC 12 Project Proposal Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C 15 th August 2012 Page 1 Motivation Increased requirements of high power semiconductor device

More information

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip SzePei Lim (Presenter), Jason Chou, Maria Durham, and Dr. Andy Mackie Indium Corporation 1 Outline of Presentation Roadmaps and challenges

More information

QUALIFICATION PLAN RELIABILITY LABORATORY

QUALIFICATION PLAN RELIABILITY LABORATORY QUALIFICATION PLAN RELIABILITY LABORATORY PCN #: CYER-22JGDE810 Date: Aug 9, 2010 Qualification of 28L SOIC package with SG-8300GM mold compound at MTAI assembly site and the 18L SOIC package will qualify

More information

Plasma for Underfill Process in Flip Chip Packaging

Plasma for Underfill Process in Flip Chip Packaging Plasma for Underfill Process in Flip Chip Packaging Jack Zhao and James D. Getty Nordson MARCH 2470-A Bates Avenue Concord, California 94520-1294 USA Published by Nordson MARCH www.nordsonmarch.com 2015

More information

Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design

Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design Yuci Shen *1, Leilei Zhang ** and Xuejun Fan * * Lamar University, Beaumont, Texas ** NVIDIA Corporation, Santa Clara, California

More information

Quality and Reliability Report

Quality and Reliability Report Quality and Reliability Report Product Qualification MASW-007921 2mm 8-Lead Plastic Package QTR-0148 M/A-COM Technology Solutions Inc. 100 Chelmsford Street Lowell, MA 01851 Tel: (978) 656-2500 Fax: (978)

More information

System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb)

System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb) System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb) Steffen Kröhnert, José Campos, Eoin O Toole NANIUM S.A., Vila do Conde, Portugal Outline Short Company Overview NANIUM Introduction

More information

Wafer Level Chip Scale Package (WLCSP)

Wafer Level Chip Scale Package (WLCSP) Freescale Semiconductor, Inc. Application Note Document Number: AN3846 Rev. 4.0, 8/2015 Wafer Level Chip Scale Package (WLCSP) 1 Introduction This application note provides guidelines for the handling

More information

Quality and Reliability Report

Quality and Reliability Report Quality and Reliability Report Product Qualification MAAM-008819 2mm 8-Lead PDFN Plastic Package QTR-0147 M/A-COM Technology Solutions Inc. 100 Chelmsford Street Lowell, MA 01851 Tel: (978) 656-2500 Fax:

More information

High Density PoP (Package-on-Package) and Package Stacking Development

High Density PoP (Package-on-Package) and Package Stacking Development High Density PoP (Package-on-Package) and Package Stacking Development Moody Dreiza, Akito Yoshida, *Kazuo Ishibashi, **Tadashi Maeda, Amkor Technology Inc. 1900 South Price Road, Chandler, AZ 85248, U.S.A.

More information

Three-Dimensional Flow Analysis of a Thermosetting. Compound during Mold Filling

Three-Dimensional Flow Analysis of a Thermosetting. Compound during Mold Filling Three-Dimensional Flow Analysis of a Thermosetting Compound during Mold Filling Junichi Saeki and Tsutomu Kono Production Engineering Research Laboratory, Hitachi Ltd. 292, Yoshida-cho, Totsuka-ku, Yokohama,

More information

WorkShop Audace. INSA ROUEN 8 juin 2012

WorkShop Audace. INSA ROUEN 8 juin 2012 WorkShop Audace INSA ROUEN 8 juin 2012 Global Standards for the Microelectronics Industry JEDEC standards for product level qualification Christian Gautier Content JEDEC overview Environmental reliability

More information

PCB Technologies for LED Applications Application note

PCB Technologies for LED Applications Application note PCB Technologies for LED Applications Application note Abstract This application note provides a general survey of the various available Printed Circuit Board (PCB) technologies for use in LED applications.

More information

TSV CHIP STACKING MEETS PRODUCTIVITY

TSV CHIP STACKING MEETS PRODUCTIVITY TSV CHIP STACKING MEETS PRODUCTIVITY EUROPEAN 3D TSV SUMMIT 22-23.1.2013 GRENOBLE HANNES KOSTNER DIRECTOR R&D BESI AUSTRIA OVERVIEW Flip Chip Packaging Evolution The Simple World of C4 New Flip Chip Demands

More information

1 Thin-film applications to microelectronic technology

1 Thin-film applications to microelectronic technology 1 Thin-film applications to microelectronic technology 1.1 Introduction Layered thin-film structures are used in microelectronic, opto-electronic, flat panel display, and electronic packaging technologies.

More information

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012 Challenges and Solutions for Cost Effective Next Generation Advanced Packaging H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012 Outline Next Generation Package Requirements ewlb (Fan-Out Wafer

More information

Development of Next-Generation ewlb Packaging

Development of Next-Generation ewlb Packaging Development of Next-Generation ewlb Packaging by Seung Wook Yoon, Yaojian Lin, Pandi Chelvam Marimuthu and *Rajendra Pendse STATS ChipPAC Singapore *Fremont, California USA Ganesh V. P, Andreas Bahr and

More information

Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging

Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging Wei Sun, W.H. Zhu, Kriangsak Sae Le and H.B. Tan United Test

More information

Recent Trend of Package Warpage Characteristic

Recent Trend of Package Warpage Characteristic Recent Trend of Package Warpage Characteristic Wei Keat Loh 1, Ron Kulterman 2, Tim Purdie 3, Haley Fu 4, Masahiro Tsuriya 4 1 Intel Technology Sdn. Bhd. Penang, Malaysia 2 Flextronics, Austin, Texas,

More information

Packaging Substrate Workshop Wrap Up. Bob Pfahl, inemi

Packaging Substrate Workshop Wrap Up. Bob Pfahl, inemi Packaging Substrate Workshop Wrap Up Bob Pfahl, inemi Warpage Facilitator: Jie Xue, Cisco Presenter: ML Loke, Intel Breakout Session (ends 10:30 am) Introduction & your expectation Issues & Root cause

More information

Hot Chips: Stacking Tutorial

Hot Chips: Stacking Tutorial Hot Chips: Stacking Tutorial Choon Lee Technology HQ, Amkor Enabling a Microelectronic World Mobile Phone Technology Change Feature Phone Smartphone Smartphones as a Percentage of All Phones Source : The

More information

New Technology for High-Density LSI Mounting in Consumer Products

New Technology for High-Density LSI Mounting in Consumer Products New Technology for High-Density Mounting in Consumer Products V Hidehiko Kira V Akira Takashima V Yukio Ozaki (Manuscript received May 29, 2006) The ongoing trend toward downsizing and the growing sophistication

More information

Flip-Chip Process Improvements for Low Warpage

Flip-Chip Process Improvements for Low Warpage Flip-Chip Process Improvements for Low Warpage Robert L. Hubbard Lambda Technologies, Inc. Morrisville, NC, USA bhubbard@microcure.com Pierino Zappella*, Pukun Zhu Henkel Corporation Irvine, CA, USA Abstract

More information

Silicon Wafer Processing PAKAGING AND TEST

Silicon Wafer Processing PAKAGING AND TEST Silicon Wafer Processing PAKAGING AND TEST Parametrical test using test structures regularly distributed in the wafer Wafer die test marking defective dies dies separation die fixing (not marked as defective)

More information

An Innovative High Throughput Thermal Compression Bonding Process

An Innovative High Throughput Thermal Compression Bonding Process An Innovative High Throughput Thermal Compression Bonding Process Li Ming 2 September 2015 Outline Introduction Throughput improved TCB Process Liquid Phase Contact (LPC) bonding Flux-LPC-TCB under inert

More information

YOUR Strategic TESTING ENGINEERING CONCEPT SMT FLIP CHIP PRODUCTION OPTO PACKAGING PROCESS DEVELOPMENT CHIP ON BOARD SUPPLY CHAIN MANAGEMENT

YOUR Strategic TESTING ENGINEERING CONCEPT SMT FLIP CHIP PRODUCTION OPTO PACKAGING PROCESS DEVELOPMENT CHIP ON BOARD SUPPLY CHAIN MANAGEMENT YOUR Strategic TECHNOLOGY PARTNER Wafer Back-End OPTO PACKAGING PROCESS DEVELOPMENT CONCEPT FLIP CHIP PROTOTYping ENGINEERING TESTING SMT PRODUCTION CHIP ON BOARD SUPPLY CHAIN MANAGEMENT Next Level 0f

More information

Transfer Molding Encapsulation of Flip Chip Array Packages

Transfer Molding Encapsulation of Flip Chip Array Packages Intl. Journal of Microcircuits and Electronic Packaging Transfer Molding Encapsulation of Flip Chip Array Packages Louis P. Rector*, Shaoqin Gong, and Tara R. Miles Dexter Corporation 11 Franklin Street

More information

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan 3D Package Technologies Review with Gap Analysis for Mobile Application Requirements Apr 22, 2014 STATS ChipPAC Japan T.Nishio Contents Package trends and roadmap update Advanced technology update Fine

More information

Close supply chain collaboration enables easy implementation of chip embedded power SiP

Close supply chain collaboration enables easy implementation of chip embedded power SiP Close supply chain collaboration enables easy implementation of chip embedded power SiP Gerald Weidinger, R&D Project Leader, AT&S AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Fabriksgasse13

More information

Flip-Chip Process Improvements for Low Warpage

Flip-Chip Process Improvements for Low Warpage Flip-Chip Process Improvements for Low Warpage Robert L. Hubbard Lambda Technologies, Inc. Morrisville, NC, USA bhubbard@microcure.com Pierino Zappella*, Pukun Zhu Henkel Corporation Irvine, CA, USA Abstract

More information

Package Design Optimization and Materials Selection for Stack Die BGA Package

Package Design Optimization and Materials Selection for Stack Die BGA Package Package Design Optimization and Materials Selection for Stack Die BGA Package Rahul Kapoor, Lim Beng Kuan, Liu Hao United Test & Assembly Center Ltd (UTAC) 5 Serangoon North Ave 5, Singapore 554916 Email:

More information

Project Proposal. Cu Wire Bonding Reliability Phase 3 Planning Webinar. Peng Su June 6, 2014

Project Proposal. Cu Wire Bonding Reliability Phase 3 Planning Webinar. Peng Su June 6, 2014 Project Proposal Cu Wire Bonding Reliability Phase 3 Planning Webinar Peng Su June 6, 2014 Problem Statement Background Work of the inemi Cu wire reliability project identified that bonding quality and

More information

TECHNOLOGIES FOR APPLYING FLUIDS IN SEMICONDUCTOR PACKAGING

TECHNOLOGIES FOR APPLYING FLUIDS IN SEMICONDUCTOR PACKAGING TECHNOLOGIES FOR APPLYING FLUIDS IN SEMICONDUCTOR PACKAGING Alec J. Babiarz Asymtek Carlsbad, CA, USA ajbabiarz@asymtek.com ABSTRACT Jetting fluids in semiconductor packaging and assembly has become an

More information

General company presentation. January 2015

General company presentation. January 2015 General company presentation January 2015 Mission Our mission is to be world class competence center offering development and manufacturing of functional semiconductor assembly solutions. Focus on (MEM

More information

Copper Wire Bonding Technology and Challenges

Copper Wire Bonding Technology and Challenges Copper Wire Bonding Technology and Challenges By Dr Roger Joseph Stierman Date: 21 & 22 October 2013 Venue: SHRDC, Shah Alam, Selangor *2 days training package RM 3,000 per pax [*] * includes hotel accommodation

More information

Semiconductor Packaging and Assembly 2002 Review and Outlook

Semiconductor Packaging and Assembly 2002 Review and Outlook Gartner Dataquest Alert Semiconductor Packaging and Assembly 2002 Review and Outlook During 2002, the industry continued slow growth in unit volumes after bottoming out in September 2001. After a hearty

More information

WF6317. A superactive low-volatile/high heat-resistant water-soluble flux for ball soldering

WF6317. A superactive low-volatile/high heat-resistant water-soluble flux for ball soldering WF637 A superactive low-volatile/high heat-resistant water-soluble flux for ball soldering Low viscosity and high tacking power stabilize ball holding force and ensures excellent solder wettability Easy

More information

14. Designing with FineLine BGA Packages

14. Designing with FineLine BGA Packages 14. Designing with FineLine BGA Packages S51014-1.0 Chapter 14, Designing with FineLine BGA Packages, replaces AN 114: Designing with FineLine BGA Packages. Introduction As programmable logic devices (PLDs)

More information

3.0x2.0mm SMD LED WITH CERAMIC SUBSTRATE. PRELIMINARY SPEC Part Number: AT3020QB24ZS-RV Blue. Features. Material as follows: Package Dimensions

3.0x2.0mm SMD LED WITH CERAMIC SUBSTRATE. PRELIMINARY SPEC Part Number: AT3020QB24ZS-RV Blue. Features. Material as follows: Package Dimensions PRELIMINARY SPEC Part Number: AT3020QB24ZS-RV Blue ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC DISCHARGE SENSITIVE DEVICES Features 1.Dimensions : 3.0mm X 2.0mm X 0.8mm. 2.Higher brightness.

More information

Next Generation ewlb (embedded Wafer Level BGA) Packaging

Next Generation ewlb (embedded Wafer Level BGA) Packaging Next Generation ewlb (embedded Wafer Level BGA) Packaging by Meenakshi Prashant, Kai Liu, Seung Wook Yoon Yonggang Jin, Xavier Baraton, S. W. Yoon*, Yaojian Lin*, Pandi C. Marimuthu*, V. P. Ganesh**, Thorsten

More information

Test Flow for Advanced Packages (2.5D/SLIM/3D)

Test Flow for Advanced Packages (2.5D/SLIM/3D) 1 Test Flow for Advanced Packages (2.5D/SLIM/3D) Gerard John Amkor Technology Inc. Gerard.John@amkor.com 2045 East Innovation Circle, Tempe, AZ 85284, USA Phone: (480) 821-5000 ADVANCED PACKAGE TEST FLOW

More information

GENERALIZATIONS ABOUT COMPONENT FLATNESS AT ELEVATED TEMPERATURE

GENERALIZATIONS ABOUT COMPONENT FLATNESS AT ELEVATED TEMPERATURE GENERALIZATIONS ABOUT COMPONENT FLATNESS AT ELEVATED TEMPERATURE Bev Christian, Linda Galvis, Rick Shelley and Matthew Anthony BlackBerry Cambridge, Ontario, CANADA bchristian@blackberry.com ABSTRACT:

More information

Non-Hermetic Packaging of RF Multi-Chip Modules

Non-Hermetic Packaging of RF Multi-Chip Modules Non-Hermetic Packaging of RF Multi-Chip Modules Matthew Gruber Lockheed Martin MST Moorestown, NJ 1 A Comment about this Presentation In accordance with ITAR restrictions, a few concessions had to be made

More information

Interconnection Reliability of HDI Printed Wiring Boards

Interconnection Reliability of HDI Printed Wiring Boards Presented in the ECWC 10 Conference at IPC Printed Circuits Expo, SMEMA Council APEX and Designers Summit 05 Interconnection Reliability of HDI Printed Wiring Boards Tatsuo Suzuki Nec Toppan Circuit Solutions,

More information

Copper Wire Bonding: the Last Frontier of Cost Savings. Bernd K Appelt Business Development ASE (U.S.) Inc. April 11, 2012

Copper Wire Bonding: the Last Frontier of Cost Savings. Bernd K Appelt Business Development ASE (U.S.) Inc. April 11, 2012 Copper Wire Bonding: the Last Frontier of Cost Savings Bernd K Appelt Business Development ASE (U.S.) Inc. April 11, 2012 Outline Introduction Fundamental Study Reliability Study Monitoring Data High Volume

More information

Prime Technology Inc.(PTI), Engineering Capability

Prime Technology Inc.(PTI), Engineering Capability Technology, Knowhow, Services & Market Segments With large-scale resources and the broadest capital in the Electronics Manufacturing Services (EMS) industry, Prime Technology (PTI) provides services from

More information

Chip Packaging for Wearables Choosing the Lowest Cost Package

Chip Packaging for Wearables Choosing the Lowest Cost Package Chip Packaging for Wearables Choosing the Lowest Cost Package Alan Palesko alanp@savansys.com (512) 402-9943 www.savansys.com Slide - 1 Agenda Introduction Wearable Requirements Packaging Technologies

More information

2.5D and 3D Semiconductor Package Technology: Evolution and Innovation

2.5D and 3D Semiconductor Package Technology: Evolution and Innovation 2.5D and 3D Semiconductor Package Technology: Evolution and Innovation Vern Solberg Solberg Technical Consulting Saratoga, California USA Abstract The electronics industry is experiencing a renaissance

More information

contaminated, or if the location of the assembly house is well above sea level.

contaminated, or if the location of the assembly house is well above sea level. VAPOR PHASE REFLOW S EFFECT ON SOLDER PASTE RESIDUE SURFACE INSULATION RESISTANCE Karen Tellefsen. Mitch Holtzer, Corne Hoppenbrouwers Alpha Assembly Solutions South Plainfield, NJ, USA Roald Gontrum SmartTech

More information

Abstract. Introduction

Abstract. Introduction Accelerating Silicon Carbide Power Electronics Devices into High Volume Manufacturing with Mechanical Dicing System By Meng Lee, Director, Product Marketing and Jojo Daof, Senior Process Engineer Abstract

More information

Die Attach Materials. Die Attach G, TECH. 2U. TECHNICAL R&D DIV.

Die Attach Materials. Die Attach G, TECH. 2U. TECHNICAL R&D DIV. Die Attach Materials Die Attach G, TECH. 2U. TECHNICAL R&D DIV. 2 Topics 3 What it is X 5,000 X 10,000 X 50,000 Si Chip Au Plating Substrate Ag Resin 4 Current Products Characteristics H9890-6A H9890-6S

More information

Modelling Embedded Die Systems

Modelling Embedded Die Systems Modelling Embedded Die Systems Stoyan Stoyanov and Chris Bailey Computational Mechanics and Reliability Group (CMRG) University of Greenwich, London, UK 22 September 2016 IMAPS/NMI Conference on EDT Content

More information

Nondestructive Internal Inspection. The World s Leading Acoustic Micro Imaging Lab

Nondestructive Internal Inspection. The World s Leading Acoustic Micro Imaging Lab Nondestructive Internal Inspection The World s Leading Acoustic Micro Imaging Lab Unmatched Capabilities and Extensive Expertise At Your Service SonoLab, a division of Sonoscan, is the world s largest

More information

BOARD LEVEL ASSEMBLY AND RELIABILITY CONSIDERATIONS FOR QFN TYPE PACKAGES

BOARD LEVEL ASSEMBLY AND RELIABILITY CONSIDERATIONS FOR QFN TYPE PACKAGES BOARD LEVEL ASSEMBLY AND RELIABILITY CONSIDERATIONS FOR QFN TYPE PACKAGES Ahmer Syed and WonJoon Kang Amkor Technology, Inc. 1900 S. Price Road Chandler, Arizona ABSTRACT There is a strong interest in

More information

Power Electronics Packaging Revolution Module without bond wires, solder and thermal paste

Power Electronics Packaging Revolution Module without bond wires, solder and thermal paste SEMIKRON Pty Ltd 8/8 Garden Rd Clayton Melbourne 3168 VIC Australia Power Electronics Packaging Revolution Module without bond wires, solder and thermal paste For some years now, the elimination of bond

More information

Rockwell R RF to IF Down Converter

Rockwell R RF to IF Down Converter Construction Analysis Rockwell R6732-13 RF to IF Down Converter Report Number: SCA 9709-552 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780

More information

Wafer Level Packaging

Wafer Level Packaging 1 IEEE CPMT Meeting, San Jose, CA Wafer Level Packaging L. Nguyen National Semiconductor Corp. Santa Clara, CA Acknowledgments: N. Kelkar, V. Patwardhan, C. Quentin, H. Nguyen, A. Negasi, E. Warner Feb-02

More information

Reliability Evaluation of CIF (chip-in-flex) and COF (chip-on-flex) packages

Reliability Evaluation of CIF (chip-in-flex) and COF (chip-on-flex) packages Reliability Evaluation of CIF (chip-in-flex) and COF (chip-on-flex) packages Jae-Won Jang* a, Kyoung-Lim Suk b, Kyung-Wook Paik b, and Soon-Bok Lee a a Dept. of Mechanical Engineering, KAIST, 335 Gwahangno

More information

An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages

An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages Michael Hertl 1, Diane Weidmann 1, and Alex Ngai 2 1 Insidix, 24 rue du Drac, F-38180 Grenoble/Seyssins,

More information

Topography and Deformation Measurement and FE Modeling Applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs)

Topography and Deformation Measurement and FE Modeling Applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs) Topography and Deformation Measurement and FE Modeling Applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs) M. Hertl Insidix, 24 rue du Drac, 38180 Grenoble/Seyssins,

More information

Parameter Symbol Value Unit. Operating Temperature Top -40 To +100 C. Storage Temperature Tstg -40 To +120 C. Parameter Symbol Value Unit

Parameter Symbol Value Unit. Operating Temperature Top -40 To +100 C. Storage Temperature Tstg -40 To +120 C. Parameter Symbol Value Unit PRELIMINARY SPEC Part Number: KT-3228ZG10ZS-RV Green ATTENTION OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC DISCHARGE SENSITIVE DEVICES Absolute Maximum Ratings at TA = 25 C Parameter Symbol Value Unit

More information

Thermal Management of Die Stacking Architecture That Includes Memory and Logic Processor

Thermal Management of Die Stacking Architecture That Includes Memory and Logic Processor Thermal Management of Die Stacking Architecture That Includes Memory and Logic Processor Bhavani P. Dewan-Sandur, Abhijit Kaisare and Dereje Agonafer The University of Texas at Arlington, Box 19018, TX

More information

Introduction of CSC Pastes

Introduction of CSC Pastes Introduction of CSC Pastes Smart Phones & Conductive Pastes Chip Varistors Chip Inductors LC Filters Flexible Printed Circuit Boards Electronic Molding Compounds ITO Electrodes PCB Through Holes Semiconductor

More information

Change Summary of MIL-PRF Revision K

Change Summary of MIL-PRF Revision K Throughout the document Add class Y. Add class Y non-hermetic for space application QML products to the MIL-PRF-38535., Class Y task group and Space community. Throughout the document Update Non-government

More information

IPC-AJ-820A Assembly and Joining Handbook. The How and Why of All Things PCB & PCA

IPC-AJ-820A Assembly and Joining Handbook. The How and Why of All Things PCB & PCA IPC-AJ-820A Assembly and Joining Handbook The How and Why of All Things PCB & PCA 1 Scope To provide guidelines and supporting info for the mfg of electronic equipment To explain the HOW TO and WHY Discussions

More information

Quality in Electronic Production has a Name: Viscom. System Overview

Quality in Electronic Production has a Name: Viscom. System Overview Quality in Electronic Production has a Name: Viscom System Overview Successful along the whole line with Viscom Circuit board manufacturing Paste print Finish S3070 AFI-Scan S3054QS Paste print Thick film

More information