SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL

Size: px
Start display at page:

Download "SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL"

Transcription

1 2017 IEEE 67th Electronic Components and Technology Conference SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL YoungRae Kim 1, JaeHun Bae 1, MinHwa Chang 1, AhRa Jo 1, Ji Hyun Kim 1, SangEun Park 1, David Hiner 2, Michael Kelly 2, and WonChul Do 1 1 Amkor Technology Korea, Inc., 150, Songdomirae-ro, Yeonsu-gu, Incheon 21991, Korea 2 Amkor Technology, 2045 East Innovation Circle, Tempe, AZ 85284, USA Abstract A novel HD-FO package platform was introduced with a hybrid RDL structure. An HD-FO package with hybrid RDL could enables higher routing density and multi die construction in a planner configuration. The 1-μm and submicron RDL wafers were fabricated at a foundry and then the essential parts of the inorganic RDL were integrated with Amkor s internal organic RDL process making a hybrid structure. Also, the vertical interconnection on a hybrid RDL made 3-dimentional package construction. Key processes including via reveal, top die attach, and vertical package stacking were successfully demonstrated. Technical challenges in HDFO package development was discussed as well as the reliability performance results both in the package and at the board level. Keywords-high density fan-out package, hybrid RDL, diereconstruction, POP I. INTRODUCTION Recently, high-density fan-out (HD-FO) wafer-level packaging has been introduced to the industry for mobile applications. HD-FO is of great interest because of its desirable characteristics of high density routing, good electrical performance, thin profile with Package-on-Package (PoP) construction, and multi die architecture. A key contributor to HD-FO technology is an ultra-thin, fine-pitch redistribution layer (RDL) at the bottom of the HD-FO package replacing traditional substrates which have limited the line and space to 15 μm/15 μm. It is expected that the HD-FO package would provide high functionality in a small form factor, superior electrical performance, and high thermal dissipation requirement to the applications [1]. In this study, a hybrid HD-FO package which uses inorganic and organic RDLs has been introduced. A distinctive characteristic of SLIM TM (Silicon-Less Integrated Module) packaging (as this design is called at Amkor Technology) is that it uses 1-μm and submicron line and space RDL design with an inorganic passivation layer including silicon oxide and silicon nitride. Since the RDL features are more aggressive than organic based RDL, SLIM TM could have much dense RDL and possibility of enabling multi die construction with serpentine structure between the dies. Detailed descriptions of top die bump array, simplified RDL construction, key processes for a hybrid HDFO and technical challenges are described. II. TEST VEHICLE INFORMATION A. Package structure The test vehicle is composed of two dies in a planar configuration with the gap of 0.1 mm. The top dies were placed on inorganic RDL directly with copper (Cu) pillar flip-chip interconnection. SLIM packaging utilizes both inorganic and organic RDL as building blocks for signal and power routing. Mold compounds cover the top die and fanned-out RDLs provide mechanical support for the package. Tall Cu pillars were embedded in mold compound so that these Cu pillars enabled vertical interconnections between RDL and top package. The ball grid array (BGA) balls were placed at the bottom of the package in 0.4-mm pitch. Optionally, four land side capacitors (LSCs) were attached in the backside of the package. The schematic of the SLIM and SLIM POP package is shown in Fig. 1. Figure 1. Schematic representation of (a) SLIM and (b) SLIM POP package structure. B. Top die design One of the primary advantages of SLIM technology is to enable a multi-die construction within a package. In such a construction, the die gap adjacent to each die is connected by serpentine structured RDLs. The 1-μm and submicron inorganic RDL provides high density routing for this requirement. Also, typical bump arrays of multi-chip module in SLIM designs were composed of at least two categories. As shown in Fig. 2, fine pitch and smaller size bumps were arranged in near the die gap and the rest of the area was composed of larger bump pitch and size. Therefore, each single die has mixed bump pitches and sizes of Cu pillar. The size of large top die was 6 x 8 mm and that of small die was 4 x 8 mm. Around 5000 and 4000 Cu pillars were formed in large and small die, respectively /17 $ IEEE DOI /ECTC

2 Figure 2. Schematic representation of bump arrays in multi-chip construction. C. Inorganic and organic RDL The interposer size was 15 x 15 mm on 300-mm wafers. Single or double layers of inorganic RDLs were fabricated on a Si wafer. Dielectrics of inorganic RDLs were silicon nitride and silicon oxide materials which are commonly used in back end of line (BEOL) of wafer fabrication. In addition, one or two organic layers were added onto the inorganic layers making a hybrid RDLs. The line/space of the inorganic RDL varied from submicron to 1/1 μm and that of the organic RDL was 5/5 μm to 10/10 μm. The combination of inorganic and organic RDL is a key feature of SLIM construction. The serpentine RDL for multi die routing and the structure of hybrid RDLs are shown in Fig. 3. D. Test chain design In order to verify the reliability and the integrity of SLIM technology, the test vehicle includes hundreds of test chains throughout the BEOL of the top dies, Cu pillar solder joint, μ-bump via to inorganic RDL, inorganic to organic RDL, and BGA balls. Since SLIM technology uses ultra-thin and stiff inorganic RDL, specific test chains were placed in mechanically weak areas, such as the peripheral areas of the silicon (Si) top die, the gap between top die, and the package edge. Therefore, the chains could detect open/short and crack failure in the electrical test after reliability. Examples of test chains are depicted in Fig. 4. Other test chains including board level reliability (BLR) were connected through BGA balls but also passing into and out of the inorganic and top die BEOL lines. These BLR chains also detect inorganic RDL layer failures during BLR test. Figure 4. Examples of 0 and 45 rotated serpentine and comb structures were embedded onto die edge, die-to-die and package edge for crack and open/short failure detection. Line spacing of these structures were presented in 1/1 μm, 0.5/0.5 μm, and 0.5/1.5 μm. III. SLIM INTEGRATION AND ASSEMBLY Figure 3. (a) Serpentine structure of the inorganic RDL, (b) structure of hybrid RDL with single layer of inorganic RDL and double layers of organic RDLs. A. Organic RDL process The fabrication of organic RDL for SLIM packaging provides an advantage to multiple organic RDLs with fine line spacing. Most of routing requirement can be integrated in the inorganic layer(s), which have superior routing density, and the addition of single or double layers of organic RDL complement this high-density routing to create the final SLIM construction. Thus, the additional fabrication process of organic RDLs can be minimized in an outsourced semiconductor assembly and test (OSAT), which means the cycle time of RDL process can be shorten in a hybrid HD- FO package process. Also, the features of the organic RDL process to SLIM is not aggressive but could accept much complex design in presence of hybrid RDLs. L/S 10/10μm was sufficient so there are no concerns of making fine feature RDLs such as L/S 2/2μm or below. Therefore, the fabrication process in SLIM designs becomes simpler than multiple layers of organic RDLs and this can translate into higher yield. Examples of the fabrication processes in organic RDL which requires only three step mask process and additional under-bump metallization (UBM) pad of single mask process are presented in Fig. 5. 9

3 Figure 7. M1 layer to via connection after dry etching of via and bump pad plating. Figure 5. Typical organic RDL process in SLIM designs: (a) 1st passivation layer, (b) Cu RDL, (c) 2nd passivation, and (d) UBM pads. B. Si removal & via etch To use ultra-thin inorganic RDL from an interposer wafer, the bulk Si should be removed from the interposer wafer during the SLIM process. A traditional wafer back grinding (WBG) process was applied and then followed by a Si etching process to remove the final bulk silicon. Photoresist (PR) was used to define the via and then, the inorganic passivation was opened by a dry etching process resulting in the via opening. Then, the revealed M1 metal openings were connected by plating process of the bump pad materials. Via reveal processes are summarized in Fig. 6. C. Top die bonding Top dies were bonded to SLIM RDL in a chip-last approach. After fabrication of RDL and μ-bump pad, the SLIM interposer wafers were transferred to the assembly process. Only known good SLIM interposer dies were used in assembly with known good top dies attached using mass reflow. This is a key advantage of the chip-last approach, namely that only good SLIM interposer sites receive good functional die. The mass reflow in SLIM process was in Chip on Wafer (CoW) fashion. It is expected that the CoW mass reflow has lower risk of ultra-low dielectric constant (ULK) layer damage compared to laminate-based reflow. Traditional mass reflow uses Si top die bonding to a laminate substrate having a high coefficient of thermal expansion (CTE) mismatch. Thus, the ULK layer damage was often detected after mass reflow or reliability test in mass reflow process [3]. However, CoW mass reflow would have less residual stress because the CTE mismatch between top die and the wafer is minimized. A photo of the top die bonding to the RDL interposer is shown in Fig. 8. Figure 6. Via reveal process flow. Seamless contact via from M1 metal layer to the bump pad is one of the most critical process for the SLIM construction. Typical etch species for dielectric etch process could produce by-products on the wafer surface [2]. Careful selection of etch chemistry has been accomplished so that post etch residues can be adequately cleaned. Once the etching process has been optimized, the bump pad plating follows to form the connection between M1 metal and the bump pad. Fig. 7 shows contamination-free via and seamless interconnection to the bump pad. Figure 8. (a) Chip on Wafer bonding with mass reflow (b) A image of solder joint shape with mass reflow. D. Gap filling for micro solder bump joint Once the top die attached to the hybrid RDLs, the gap filling process was performed to fill the gap. 30-μm pitch Cu pillar solder bump array was successfully filled with capillary underfill (CUF) material. There was no 10

4 delamination between epoxy mold compound and underfill and the interface of the underfill to inorganic passivation layer. Also, the voids were not detected in gap filling process of the SLIM package after assembly and reliability test. Careful material selection was required for the capillary underfill material because of the reliability concern of SLIM. In addition to CUF, the mold underfill (MUF) was evaluated to the same test vehicle. The gap filling performance with MUF process showed good and there was no delamination and void as well. In MUF process, gap filling and wafer molding are performed in a single process so that process cost and cycle time could be reduced than CUF process. Also, MUF could have homogeneous material structure compared to CUF applied SLIM package. The SLIM package with MUF has also passed reliability requirement. Comparative gap filling images from CUF and MUF are shown in Fig. 9. The difference of the filler size distribution can be seen in CUF and MUF cases. Figure 10. (a) A photo of top package attachment at the wafer level and (b) A cross section image of SLIM PoP structure. After top package attach with mass reflow, the gap between the top package and the bottom package of the SLIM design was filled with gap filling material. Gap filling for the top package requires optimization of the gap filling process. The target application of the top package in SLIM designs is an integrated memory package that has a peripheral array with no balls in the center of the package. In these arrangement, the void could be formed in the gap because the capillary force is driven by small gaps of BGA balls resulting in faster flow rate along the peripheral lines [4]. The mechanism of void entrapment has been studied and overcome by optimizing the gap filling process. The mechanism of void entrapment and scanning acoustic tomography (SAT) images are shown in Fig. 11. Figure 9. Cross-section images of the gap filled with; (a) and (b) capillary underfill, (c) and (d) mold underfill. E. Tall pillars for vertical interconnection Tall pillar interconnection was developed for 3D integration called SLIM PoP. Cu tall pillars were plated onto a peripheral ring of SLIM package and then the wafer has been molded. By applying mold grind process to the molded wafer the package height can be controlled to specified height and all the Cu tall pillar can be exposed at the same time. In the process of the co-grinding of mold compound and Cu tall pillar, mold compound layer is remained during mold grind process and there is no direct contact of Cu contaminant to the top die having active device. Then, the exposed tall pillars were bonded with BGA balls of top package resulting in vertical interconnection. High throughput mass reflow was applied in a wafer level process for SLIM top package assembly and showed good solder joint performance. A photo of the top package mass reflow at the wafer level and the structure of SLIM PoP are shown in Fig. 10. Figure 11. Void formation in gap filling process (a) after dispense, (b) mid of the gap filling step, (c) void formation inner area of the package, (d) SAT images of void captured samples, and (e) SAT images of optimized samples. Another concern of tall pillar assembly was mechanical robustness of the Cu tall pillar in reliability test. In SLIM package structure, around 200μm tall Cu pillar is surrounded by epoxy mold compound material and the tall pillar is placed on the inorganic passivation layer directly. The CTE of Cu is known as 16 ppm and typical epoxy mold compound has ~10 ppm below glass transition temperature, T g and ~ 30ppm above the T g. It was expected that the CTE mismatch between tall Cu pillar and mold compound could result in high stress at the bottom of the tall pillar. Therefore, 11

5 the tall pillar bottom area was investigated after assembly and reliability testing to ensure the robustness of the SLIM PoP structure. Fig. 12 shows the cross section of tall pillar area after Temperature Cycle, Condition B (T/C B) 1000 cycles and confirmed no mechanical damage on the inorganic passivation layer. The reliability validation of tall pillar structure has been performed in two different test vehicles and passed reliability requirement in both cases. Table 1 showed the results of package and board level reliability. Hybrid HD-FO package reliability was very promising and passed moisture resistance test (MRT) level 3, temp cycle, high temperature storage (HTS), and Unbiased Highly Accelerated Stress Test (UHAST). A key contributor to the package reliability was material combinations of the HD-FO design. Also, the board level temperature cycle, and drop test were performed and showed outstanding results. Major factors to SLIM BLR performance are the solder ball composition and material combination of SLIM package. The failure mode of temp cycle test was a solder ball crack at the package corners. The failure mode of temp cycle is presented in Fig. 13. Table 1. Reliability test result from: (a) package and (b) board level tests. Figure 12. A section of tall Cu pillar SLIM interface after reliability test of TC 1000 cycles. IV. TECHNICAL CHALLENGES IN SLIM A. Package handling Since SLIM packaging is an extremely thin construction, package handling needs to be optimized. The cross section of the SLIM package s edges is ultra-thin and the package was mainly composed of epoxy molding compound (EMC) and small portion of Cu RDL and passivation material. Package edge crack was detected during unit handling like electrical test, reliability test and arranging in a tray. In an internal mechanical strength test, the thinner HDFO has the less fracture load and the fracture load was a half of that of laminate package. In case of SLIM POP, the fracture load was exceptionally higher than non-pop structure. Also, the weight of HD-FO package is very light and the packages could be lifted up during handling and transporting. The weight of the SLIM package and SLIM PoP design are only 0.2g ±0.1g and 0.46g ±1g, respectively. B. Cost of the interposer wafer SLIM utilizes interposer wafers as a building block for RDL fabrication so the cost of the interposer affects the cost of the SLIM package. In fact, the interposer cost accounts for high portion of total SLIM package. Main driver for fan-out package in the industry was low cost and HD-FO is not an exception. Thus, cost reduction activity for HD-FO is important. V. RELIABILITY PERFORMANCE The reliability performance of SLIM package was evaluated in package and board level testing. Both reliability tests were performed in accordance with JEDEC standard. Figure 13. Failure mode of temperature cycle test. VI. CONCLUSION An HD-FO package with hybrid RDLs has been evaluated and key processes for the hybrid HD-FO were reviewed. The organic RDL process in an OSAT facility requires only four photolithography steps which can provide benefits to yield management. The connections between M1 12

6 metal line to bump pad was well defined with via reveal process. Fine pitch Cu pillar bonding of top dies with mass reflow was also demonstrated and the underfill process with both CUF and MUF showed good gap filling performance in SLIM package. It is also proven that HD-FO with hybrid RDLs can be extended to 3D interconnection with vertical Cu pillars. The reliability of HD-FO met the industry requirement, MRT L3, T/C, UHAST and HTS, and the board level reliability of 15-mm x 15-mm sized HD-FOs showed good performance. ACKNOWLEDGMENTS The authors special thanks to the contributions of Amkor design teams, process engineering teams, material suppliers and technical advisors for SLIM development. REFERENCES [1] V. S. Rao et al., "Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications," 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp [2] S. B. Kim, and H. Jeon, Characteristics of the Post-Etch Polymer Residues Formed at the Via Hole and Polymer Removal Using a Semi-Aqueous Stripper, 2006 Journal of the Korean Physical Society, 49, 5, 2006, pp [3] K. Murayama, M. Aizawa and T. Kurihara, "Low stress bonding for large size die application," 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), San Diego, CA, 2015, pp [4] K. Gilleo, The Chemistry & Physics of Underfill, Jul. 2014, [online] Available: , Amkor Technology, Inc. All rights reserved. SLIM TM is a trademark of Amkor Technology, Inc. 13

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY B. Rogers, C. Scanlan, and T. Olson Deca Technologies, Inc. Tempe, AZ USA boyd.rogers@decatechnologies.com ABSTRACT Fan-Out Wafer-Level Packaging

More information

Chips Face-up Panelization Approach For Fan-out Packaging

Chips Face-up Panelization Approach For Fan-out Packaging Chips Face-up Panelization Approach For Fan-out Packaging Oct. 15, 2015 B. Rogers, D. Sanchez, C. Bishop, C. Sandstrom, C. Scanlan, TOlson T. REV A Background on FOWLP Fan-Out Wafer Level Packaging o Chips

More information

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012 Challenges and Solutions for Cost Effective Next Generation Advanced Packaging H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012 Outline Next Generation Package Requirements ewlb (Fan-Out Wafer

More information

IME Technical Proposal. High Density FOWLP for Mobile Applications. 22 April High Density FOWLP Consortium Forum

IME Technical Proposal. High Density FOWLP for Mobile Applications. 22 April High Density FOWLP Consortium Forum IME Technical Proposal High Density FOWLP for Mobile Applications 22 April 2014 Packaging driver for portable / mobile applications Key drivers/needs Smaller form-factor lower profile, substrate-less Higher

More information

Panel Discussion: Advanced Packaging

Panel Discussion: Advanced Packaging Dr. Steve Bezuk Senior Director IC Packaging Engineering Qualcomm Technologies, Inc. Panel Discussion: Advanced Packaging PAGE 1 Technical Challenges of Packaging (Mobile Focus) Materials Die materials

More information

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan 3D Package Technologies Review with Gap Analysis for Mobile Application Requirements Apr 22, 2014 STATS ChipPAC Japan T.Nishio Contents Package trends and roadmap update Advanced technology update Fine

More information

The Development of a Novel Stacked Package: Package in Package

The Development of a Novel Stacked Package: Package in Package The Development of a Novel Stacked Package: Package in Package Abstract Stacked die Chip Scale Packages (CSPs) or Fine-pitch BGAs (FBGAs) have been readily adopted and integrated in many handheld products,

More information

Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA)

Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA) Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA) Seung Wook Yoon, Yaojian Lin and Pandi C. Marimuthu STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442 E-mail

More information

"ewlb Technology: Advanced Semiconductor Packaging Solutions"

ewlb Technology: Advanced Semiconductor Packaging Solutions "ewlb Technology: Advanced Semiconductor Packaging Solutions" by Sharma Gaurav@, S.W. Yoon, Yap Yok Mian, Shanmugam Karthik, Yaojian Lin, Pandi C. Marimuthu and Yeong J. Lee* STATS ChipPAC Ltd. 5 Yishun

More information

Assembly Challenges in Developing 3D IC Package with Ultra High Yield and High Reliability

Assembly Challenges in Developing 3D IC Package with Ultra High Yield and High Reliability Assembly Challenges in Developing 3D IC Package with Ultra High Yield and High Reliability Raghunandan Chaware, Ganesh Hariharan, Jeff Lin, Inderjit Singh, Glenn O Rourke, Kenny Ng, S. Y. Pai Xilinx Inc.

More information

Challenges of Fan-Out WLP and Solution Alternatives John Almiranez

Challenges of Fan-Out WLP and Solution Alternatives John Almiranez Challenges of Fan-Out WLP and Solution Alternatives John Almiranez Advanced Packaging Business Development Asia Introduction to Fan-Out WLP Introduction World of mobile gadgetry continues to rapidly evolve

More information

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017 Amkor Technology, Inc. White Paper Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017 Abstract Expanding its ChipArray Ball Grid Array (CABGA) package form factor miniaturization

More information

Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima

Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima Novel Materials and Activities for Next Generation Package Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima 1. Activities of Packaging Solution Center 2. Novel Materials for Next Gen.

More information

Material based challenge and study of 2.1, 2.5 and 3D integration

Material based challenge and study of 2.1, 2.5 and 3D integration 1 Material based challenge and study of 2.1, 2.5 and 3D integration Toshihisa Nonaka Packaging Solution Center R&D Headquarters Hitachi Chemical Co., Ltd., Sep. 8, 2016 Hitachi Chemical Co., Ltd. 2010.

More information

Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer

Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer Li Zheng, Student Member, IEEE, and Muhannad S. Bakir, Senior Member, IEEE Georgia Institute of Technology Atlanta,

More information

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Institute of Microelectronics

More information

S/C Packaging Assembly Challenges Using Organic Substrate Technology

S/C Packaging Assembly Challenges Using Organic Substrate Technology S/C Packaging Assembly Challenges Using Organic Substrate Technology Presented by Bernd Appelt ASE Group Nov. 17, 2009 Overview The Packaging Challenge Chip Substrate Interactions Stiffeners for FC-BGA

More information

Next Gen Packaging & Integration Panel

Next Gen Packaging & Integration Panel Next Gen Packaging & Integration Panel ECTC 2012 Daniel Tracy, Sr. Director Industry Research & Statistics SEMI May 29, 2012 Packaging Supply Chain Market Trends Material Needs and Opportunities Market

More information

Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip

Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip EPRC 12 Project Proposal Cu Pillar Interconnect and Chip-Package-Interaction (CPI) for Advanced Cu Low K chip 15 th Aug 2012 Page 1 Introduction: Motivation / Challenge Silicon device with ultra low k

More information

Test Flow for Advanced Packages (2.5D/SLIM/3D)

Test Flow for Advanced Packages (2.5D/SLIM/3D) 1 Test Flow for Advanced Packages (2.5D/SLIM/3D) Gerard John Amkor Technology Inc. Gerard.John@amkor.com 2045 East Innovation Circle, Tempe, AZ 85284, USA Phone: (480) 821-5000 ADVANCED PACKAGE TEST FLOW

More information

Design and Assembly Process Implementation of 3D Components

Design and Assembly Process Implementation of 3D Components IPC-7091 Design and Assembly Process Implementation of 3D Components Developed by the 3-D Electronic Packages Subcommittee (B-11) of the Packaged Electronic Components Committee (B-10) of IPC Users of

More information

Molding materials performances experimental study for the 3D interposer scheme

Molding materials performances experimental study for the 3D interposer scheme Minapad 2014, May 21 22th, Grenoble; France Molding materials performances experimental study for the 3D interposer scheme Y. Sinquin, A. Garnier, M. Argoud, A. Jouve, L. Baud, J. Dechamp, N. Allouti,

More information

A Cost Analysis of RDL-first and Mold-first Fan-out Wafer Level Packaging

A Cost Analysis of RDL-first and Mold-first Fan-out Wafer Level Packaging A Cost Analysis of RDL-first and Mold-first Fan-out Wafer Level Packaging Amy Palesko Lujan 1 1 SavanSys Solutions LLC, Austin, TX 78738, USA Abstract Industry interest in fan-out wafer level packaging

More information

Innovative Substrate Technologies in the Era of IoTs

Innovative Substrate Technologies in the Era of IoTs Innovative Substrate Technologies in the Era of IoTs Dyi- Chung Hu 胡迪群 September 4, 2015 Unimicron Contents Introduction Substrate Technology - Evolution Substrate Technology - Revolution Glass substrate

More information

Hot Chips: Stacking Tutorial

Hot Chips: Stacking Tutorial Hot Chips: Stacking Tutorial Choon Lee Technology HQ, Amkor Enabling a Microelectronic World Mobile Phone Technology Change Feature Phone Smartphone Smartphones as a Percentage of All Phones Source : The

More information

System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb)

System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb) System-in-Package (SiP) on Wafer Level, Enabled by Fan-Out WLP (ewlb) Steffen Kröhnert, José Campos, Eoin O Toole NANIUM S.A., Vila do Conde, Portugal Outline Short Company Overview NANIUM Introduction

More information

A Flexible Vertical MEMs Probe Card Technology for Pre-Bump and ewlp Applications

A Flexible Vertical MEMs Probe Card Technology for Pre-Bump and ewlp Applications June 12 to 15, 2011 San Diego, CA A Flexible Vertical MEMs Probe Card Technology for Pre-Bump and ewlp Applications Mike Slessor Rick Marshall (MicroProbe, Inc.) Vertical MEMS for Pre-Bump Probe Introduction:

More information

White Paper Quality and Reliability Challenges for Package on Package. By Craig Hillman and Randy Kong

White Paper Quality and Reliability Challenges for Package on Package. By Craig Hillman and Randy Kong White Paper Quality and Reliability Challenges for Package on Package By Craig Hillman and Randy Kong Background Semiconductor technology advances have been fulfilling Moore s law for many decades. However,

More information

Glass Carrier for Fan Out Panel Level Package

Glass Carrier for Fan Out Panel Level Package January 25, 2018 NEWS RELEASE Development of HRDP TM Material for Formation of Ultra-Fine Circuits with Glass Carrier for Fan Out Panel Level Package - Aiming for mass production in collaboration with

More information

Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology

Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology by Meenakshi Prashant, Seung Wook Yoon, Yaojian LIN and Pandi C. Marimuthu STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442

More information

Optimization of through-silicon via structures in a fingerprint sensor package

Optimization of through-silicon via structures in a fingerprint sensor package Optimization of through-silicon via structures in a fingerprint sensor package Fingerprint Cards AB Gustaf Onsbring Gustafson 2017 Master s Thesis in Electrical Measurements Faculty of Engineering LTH

More information

Failure Analysis for ewlb-packages Strategy and Failure Mechanisms

Failure Analysis for ewlb-packages Strategy and Failure Mechanisms Company Logo Failure Analysis for ewlb-packages Strategy and Failure Mechanisms Florian Felux Infineon Technologies AG Neubiberg, Germany Purpose Demonstration of adaption and application of various analysis

More information

MEPTEC Semiconductor Packaging Technology Symposium

MEPTEC Semiconductor Packaging Technology Symposium MEPTEC Semiconductor Packaging Technology Symposium Advanced Packaging s Interconnect Technology Process Shift and Direction October 23, 2014 Jay Hayes- Director of Business Development -Bumping and Flip

More information

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding Chapter 4 Fabrication Process of Silicon Carrier and Gold-Gold Thermocompression Bonding 4.1 Introduction As mentioned in chapter 2, the MEMs carrier is designed to integrate the micro-machined inductor

More information

Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages

Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages by Ming-Che Hsieh STATS ChipPAC Taiwan Co. Ltd. Copyright 2013. Reprinted from 2013 International Microsystems,

More information

Recent Advances in Die Attach Film

Recent Advances in Die Attach Film Recent Advances in Die Attach Film Frederick Lo, Maurice Leblon, Richard Amigh, and Kevin Chung. AI Technology, Inc. 70 Washington Road, Princeton Junction, NJ 08550 www.aitechnology.com Abstract: The

More information

ewlb (embedded Wafer Level BGA) Technology: Next Generation 3D Packaging Solutions

ewlb (embedded Wafer Level BGA) Technology: Next Generation 3D Packaging Solutions ewlb (embedded Wafer Level BGA) Technology: Next Generation 3D Packaging Solutions by Seung Wook Yoon and Meenakshi Padmanathan STATS ChipPAC Ltd. Seungwook.yoon@statschippac.com Andreas Bahr Infineon

More information

TSV Interposer Process Flow with IME 300mm Facilities

TSV Interposer Process Flow with IME 300mm Facilities TSV Interposer Process Flow with IME 300mm Facilities Property of Institute of Microelectronics (IME)-Singapore August 17, 2012 Outline 1. TSV interposer (TSI) cross sectional schematic TSI with BEOL,

More information

ENHANCING WLCSP RELIABILITY THROUGH BUILD-UP STRUCTURE IMPROVEMENTS AND NEW SOLDER ALLOYS

ENHANCING WLCSP RELIABILITY THROUGH BUILD-UP STRUCTURE IMPROVEMENTS AND NEW SOLDER ALLOYS ENHANCING WLCSP RELIABILITY THROUGH BUILD-UP STRUCTURE IMPROVEMENTS AND NEW SOLDER ALLOYS B. Rogers, M. Melgo, M. Almonte, S. Jayaraman, C. Scanlan, and T. Olson Deca Technologies, Inc 7855 S. River Parkway,

More information

PoP/CSP Warpage Evaluation and Viscoelastic Modeling

PoP/CSP Warpage Evaluation and Viscoelastic Modeling PoP/CSP Warpage Evaluation and Viscoelastic Modeling Wei Lin, Min Woo Lee Amkor Technology 19 S Price Rd, Chandler, AZ 85286 wlin@amkor.com Abstract The purpose of this paper was to evaluate the critical

More information

Evaluation of Cu Pillar Chemistries

Evaluation of Cu Pillar Chemistries Presented at 2016 IMAPS Device Packaging Evaluation of Cu Pillar Chemistries imaps Device Packaging Conference Spring 2016 Matthew Thorseth, Mark Scalisi, Inho Lee, Sang-Min Park, Yil-Hak Lee, Jonathan

More information

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes Andrew Strandjord, Thorsten Teutsch, and Jing Li Pac Tech USA Packaging Technologies, Inc. Santa Clara, CA USA 95050 Thomas Oppert, and

More information

Flip Chip - Integrated In A Standard SMT Process

Flip Chip - Integrated In A Standard SMT Process Flip Chip - Integrated In A Standard SMT Process By Wilhelm Prinz von Hessen, Universal Instruments Corporation, Binghamton, NY This paper reviews the implementation of a flip chip product in a typical

More information

3DIC Integration with TSV Current Progress and Future Outlook

3DIC Integration with TSV Current Progress and Future Outlook 3DIC Integration with TSV Current Progress and Future Outlook Shan Gao, Dim-Lee Kwong Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research) Singapore 9 September, 2010 1 Overview

More information

The Effect of Fillers in Nonconductive Adhesive on the Reliability of Chip-on-Glass Bonding with Sn/Cu Bumps

The Effect of Fillers in Nonconductive Adhesive on the Reliability of Chip-on-Glass Bonding with Sn/Cu Bumps Materials Transactions, Vol. 52, No. 11 (2011) pp. 2106 to 2110 #2011 The Japan Institute of Metals The Effect of Fillers in Nonconductive Adhesive on the Reliability of Chip-on-Glass Bonding with Sn/Cu

More information

RF System in Packages using Integrated Passive Devices

RF System in Packages using Integrated Passive Devices RF System in Packages using Integrated Passive Devices by Kai Liu, YongTaek Lee, HyunTai Kim, Gwang Kim, and Billy Ahn STATS ChipPAC 1711 W. Greentree Drive, Suite #117, Tempe, AZ 85284, USA Tel: 480-222-1722

More information

Outline. Market Size Industry Trends Material Segment Trends China Summary. Packaging Materials Market Trends, Issues and Opportunities

Outline. Market Size Industry Trends Material Segment Trends China Summary. Packaging Materials Market Trends, Issues and Opportunities Packaging Materials Market Trends, Issues and Opportunities Dan Tracy Sr. Director Industry Research SEMI 8 th December 2015 Outline Market Size Industry Trends Material Segment Trends China Summary 1

More information

Bare Die Assembly on Silicon Interposer at Room Temperature

Bare Die Assembly on Silicon Interposer at Room Temperature Minapad 2014, May 21 22th, Grenoble; France Bare Die Assembly on Silicon Interposer at Room Temperature W. Ben Naceur, F. Marion, F. Berger, A. Gueugnot, D. Henry CEA LETI, MINATEC 17, rue des Martyrs

More information

IME Proprietary. EPRC 12 Project Proposal. 3D Embedded WLP. 15 th August 2012

IME Proprietary. EPRC 12 Project Proposal. 3D Embedded WLP. 15 th August 2012 EPRC 12 Project Proposal 3D Embedded WLP 15 th August 2012 Motivation Factors driving IC market Higher density, lower cost, high yield Fan-out WLP/eWLP advantages Small footprint, low profile Low cost,

More information

5. Packaging Technologies Trends

5. Packaging Technologies Trends 5. Packaging Technologies Trends Electronic products and microsystems continue to find new applications in personal, healthcare, home, automotive, environmental and security systems. Advancements in packaging

More information

AN ANALYSIS OF KEY COST AND YIELD DRIVERS FOR FAN-OUT WAFER LEVEL PACKAGING

AN ANALYSIS OF KEY COST AND YIELD DRIVERS FOR FAN-OUT WAFER LEVEL PACKAGING AN ANALYSIS OF KEY COST AND YIELD DRIVERS FOR FAN-OUT WAFER LEVEL PACKAGING Amy Palesko SavanSys Solutions LLC Austin, TX, USA amyp@savansys.com ABSTRACT Although interest in wafer level packaging has

More information

II. A. Basic Concept of Package.

II. A. Basic Concept of Package. Wafer Level Package for Image Sensor Module Won Kyu Jeung, Chang Hyun Lim, Jingli Yuan, Seung Wook Park Samsung Electro-Mechanics Co., LTD 314, Maetan3-Dong, Yeongtong-Gu, Suwon, Gyunggi-Do, Korea 440-743

More information

A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION

A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION YINCAE Advanced Materials, LLC WHITE PAPER November 2013 2014 YINCAE Advanced Materials, LLC - All Rights Reserved. YINCAE and the YINCAE

More information

Selection and Application of Board Level Underfill Materials

Selection and Application of Board Level Underfill Materials Selection and Application of Board Level Underfill Materials Developed by the Underfill Materials Design, Selection and Process Task Group (5-24f) of the Assembly and Joining Committee (5-20) of IPC Supersedes:

More information

First Demonstration of Panel Glass Fan-out (GFO) Packages for High I/O Density and High Frequency Multi-Chip Integration

First Demonstration of Panel Glass Fan-out (GFO) Packages for High I/O Density and High Frequency Multi-Chip Integration 2017 IEEE 67th Electronic Components and Technology Conference First Demonstration of Panel Glass Fan-out (GFO) Packages for High I/O Density and High Frequency Multi-Chip Integration Tailong Shi, Chintan

More information

ENHANCING MECHANICAL SHOCK PERFORMANCE USING EDGEBOND TECHNOLOGY

ENHANCING MECHANICAL SHOCK PERFORMANCE USING EDGEBOND TECHNOLOGY ENHANCING MECHANICAL SHOCK PERFORMANCE USING EDGEBOND TECHNOLOGY Steven Perng, Tae-Kyu Lee, and Cherif Guirguis Cisco Systems, Inc. San Jose, CA, USA sperng@cisco.com Edward S. Ibe Zymet, Inc. East Hanover,

More information

FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking

FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking Hisada et al.: FEM Analysis on Warpage and Stress at the Micro Joint (1/6) [Technical Paper] FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking Takashi Hisada*, Yasuharu Yamada*,

More information

Flip Chip Bump Electromigration Reliability: A comparison of Cu Pillar, High Pb, SnAg, and SnPb Bump Structures

Flip Chip Bump Electromigration Reliability: A comparison of Cu Pillar, High Pb, SnAg, and SnPb Bump Structures Flip Chip Bump Electromigration Reliability: A comparison of Cu Pillar,,, and SnPb Bump Structures Ahmer Syed, Karthikeyan Dhandapani, Lou Nicholls, Robert Moody, CJ Berry, and Robert Darveaux Amkor Technology

More information

Nanium Overview. Company Presentation

Nanium Overview. Company Presentation Nanium Overview Company Presentation Nanium Overview Our name and logo nano prefix of Greek origin referring to small objects ium suffix of Latin origin that includes the formation of scientific terms

More information

Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages

Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages Bhavesh Varia 1, Xuejun Fan 1, 2, Qiang Han 2 1 Department of Mechanical Engineering Lamar

More information

3D-WLCSP Package Technology: Processing and Reliability Characterization

3D-WLCSP Package Technology: Processing and Reliability Characterization 3D-WLCSP Package Technology: Processing and Reliability Characterization, Paul N. Houston, Brian Lewis, Fei Xie, Ph.D., Zhaozhi Li, Ph.D.* ENGENT Inc. * Auburn University ENGENT, Inc. 2012 1 Outline Packaging

More information

Australian Journal of Basic and Applied Sciences. Pb-Free Solder Ball Robustness Comparison under AC and TC Reliability Test

Australian Journal of Basic and Applied Sciences. Pb-Free Solder Ball Robustness Comparison under AC and TC Reliability Test AENSI Journals Australian Journal of Basic and Applied Sciences ISSN:1991-8178 Journal home page: www.ajbasweb.com Pb-Free Solder Ball Robustness Comparison under AC and TC Reliability Test 1,2 Tan Cai

More information

Assembly Reliability of TSOP/DFN PoP Stack Package

Assembly Reliability of TSOP/DFN PoP Stack Package As originally published in the IPC APEX EXPO Proceedings. Assembly Reliability of TSOP/DFN PoP Stack Package Reza Ghaffarian, Ph.D. Jet Propulsion Laboratory, California Institute of Technology Pasadena,

More information

3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction

3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction 3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction Gilbert Lecarpentier*, Jean-Stéphane Mottet* SET S.A.S. (Smart Equipment Technology), 131 Impasse Barteudet, 74490

More information

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip SzePei Lim (Presenter), Jason Chou, Maria Durham, and Dr. Andy Mackie Indium Corporation 1 Outline of Presentation Roadmaps and challenges

More information

Increasing challenges for size and cost reduction,

Increasing challenges for size and cost reduction, Packageon-Package: The Story Behind This Industry Hit Package-onpackage (PoP) technology is rapidly evolving to keep pace with the demand for faster, higherdensity devices in smaller, thinner stacks. As

More information

Between 2D and 3D: WLFO Packaging Technologies and Applications

Between 2D and 3D: WLFO Packaging Technologies and Applications Between 2D and 3D: WLFO Packaging Technologies and Applications Minghao Shen Altera (now part of Intel) June 9 th, 2016 TFUG/CMPUG 3D Packaging Meeting Outline The 2.n D WLFO technologies Process and architect

More information

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package Basic PCB Level Assembly Process Methodology for 3D Package-on-Package Vern Solberg STC-Madison Madison, Wisconsin USA Abstract The motivation for developing higher density IC packaging continues to be

More information

Flip Chip Challenges

Flip Chip Challenges Flip Chip Challenges By: Steve Bezuk, PH.D. General Manager, Applied Technology Development and Flip Chip Kyocera America, Inc. Introduction Flip Chip packaging has seen an explosive growth in recent years.

More information

Predicting the Reliability of Zero-Level TSVs

Predicting the Reliability of Zero-Level TSVs Predicting the Reliability of Zero-Level TSVs Greg Caswell and Craig Hillman DfR Solutions 5110 Roanoke Place, Suite 101 College Park, MD 20740 gcaswell@dfrsolutions.com 443-834-9284 Through Silicon Vias

More information

An Innovative High Throughput Thermal Compression Bonding Process

An Innovative High Throughput Thermal Compression Bonding Process An Innovative High Throughput Thermal Compression Bonding Process Li Ming 2 September 2015 Outline Introduction Throughput improved TCB Process Liquid Phase Contact (LPC) bonding Flux-LPC-TCB under inert

More information

Failure Modes in Wire bonded and Flip Chip Packages

Failure Modes in Wire bonded and Flip Chip Packages Failure Modes in Wire bonded and Flip Chip Packages Mumtaz Y. Bora Peregrine Semiconductor San Diego, Ca. 92121 mbora@psemi.com Abstract The growth of portable and wireless products is driving the miniaturization

More information

Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C

Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C EPRC 12 Project Proposal Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C 15 th August 2012 Page 1 Motivation Increased requirements of high power semiconductor device

More information

Accurate Predictions of Flip Chip BGA Warpage

Accurate Predictions of Flip Chip BGA Warpage Accurate Predictions of Flip Chip BGA Warpage Yuan Li Altera Corporation 11 Innovation Dr, M/S 422 San Jose, CA 95134 ysli@altera.com, (48)544-758 Abstract Organic flip chip BGA has been quickly adopted

More information

TSV CHIP STACKING MEETS PRODUCTIVITY

TSV CHIP STACKING MEETS PRODUCTIVITY TSV CHIP STACKING MEETS PRODUCTIVITY EUROPEAN 3D TSV SUMMIT 22-23.1.2013 GRENOBLE HANNES KOSTNER DIRECTOR R&D BESI AUSTRIA OVERVIEW Flip Chip Packaging Evolution The Simple World of C4 New Flip Chip Demands

More information

SUSS SOLUTIONS FOR LARGE FORMAT PATTERNING UV Scanning Lithography and Excimer Laser Ablation

SUSS SOLUTIONS FOR LARGE FORMAT PATTERNING UV Scanning Lithography and Excimer Laser Ablation SUSS SOLUTIONS FOR LARGE FORMAT PATTERNING UV Scanning Lithography and Excimer Laser Ablation Kevin Yang, Habib Hichri, Ralph Zoberbier SÜSS MicroTec Photonic Systems Inc. June 18, 2015 MARKET DRIVER Mobile

More information

Journal of Science and Technology The Investigation of Die Back Edge Cracking in Flip Chip Ceramic Ball Grid Array Package (FC-CBGA)

Journal of Science and Technology The Investigation of Die Back Edge Cracking in Flip Chip Ceramic Ball Grid Array Package (FC-CBGA) The Investigation of Die Back Edge Cracking in Flip Chip Ceramic Ball Grid Array Package (FC-CBGA) Zainudin Kornain a, Azman Jalar a, Rozaidi Rasid b, a Institute of Microengineering and Nanoelectronics

More information

EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS

EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS As originally published in the SMTA Proceedings. EPOXY FLUX MATERIAL AND PROCESS FOR ENHANCING ELECTRICAL INTERCONNECTIONS Neil Poole, Ph.D., Elvira Vasquez, and Brian J. Toleno, Ph.D. Henkel Electronic

More information

ROOM TEMPERATURE FAST FLOW REWORKABLE UNDERFILL FOR LGA

ROOM TEMPERATURE FAST FLOW REWORKABLE UNDERFILL FOR LGA As originally published in the SMTA Proceedings ROOM TEMPERATURE FAST FLOW REWORKABLE UNDERFILL FOR LGA Mary Liu, Ph.D., and Wusheng Yin, Ph.D. YINCAE Advanced Materials, LLC Albany, NY, USA wyin@yincae.com

More information

A New 2.5D TSV Package Assembly Approach

A New 2.5D TSV Package Assembly Approach A New 2.5D TSV Package Assembly Approach Yuan Lu 1,2, Wen Yin 1,2, Bo Zhang 1,2, Daquan Yu 1,2, Lixi Wan 2, Dongkai Shangguan 1,2 Guofeng Xia 3, Fei Qin 3, Mao Ru 4, Fei Xiao 4 1 National Center for Advanced

More information

Fan-out Wafer Level ewlb Technology as an Advanced System-in- Package Solution

Fan-out Wafer Level ewlb Technology as an Advanced System-in- Package Solution Fan-out Wafer Level ewlb Technology as an Advanced System-in- Package Solution by Jacinta Aman Lim and Vinayak Pandey, STATS ChipPAC, Inc. Aung Kyaw Oo, Andy Yong, STATS ChipPAC Pte. Ltd. Originally published

More information

TechARENA Packaging Exhibitor Session OCT/08, 2014 New WLP-Technology-Fusion Concept Steffen Kröhnert, Director of Technology, NANIUM S.A. V1.

TechARENA Packaging Exhibitor Session OCT/08, 2014 New WLP-Technology-Fusion Concept Steffen Kröhnert, Director of Technology, NANIUM S.A. V1. TechARENA Packaging Exhibitor Session OCT/08, 2014 New WLP-Technology-Fusion Concept Steffen Kröhnert, Director of Technology, NANIUM S.A. V1.0 EXT Notification NANIUM is highly committed to IP protection.

More information

Figure 1 Embedded Active and Passive Module (EMAP) Cross-section Schematic

Figure 1 Embedded Active and Passive Module (EMAP) Cross-section Schematic Super High Density Two Metal Layer Ultra-Thin Organic Substrates for Next Generation System-On-Package (SOP), SIP and Ultra-Fine Pitch Flip-Chip Packages Venky Sundaram, Hunter Chan, Fuhan Liu, and Rao

More information

Equipment and Process Challenges for the Advanced Packaging Landscape

Equipment and Process Challenges for the Advanced Packaging Landscape Equipment and Process Challenges for the Advanced Packaging Landscape Veeco Precision Surface Processing Laura Mauer June 2018 1 Copyright 2018 Veeco Instruments Inc. Outline» Advanced Packaging Market

More information

FABRICATION AND RELIABILITY OF ULTRA-FINE RDL STRUCTURES IN ADVANCED PACKAGING BY EXCIMER LASER ABLATION

FABRICATION AND RELIABILITY OF ULTRA-FINE RDL STRUCTURES IN ADVANCED PACKAGING BY EXCIMER LASER ABLATION FABRICATION AND RELIABILITY OF ULTRA-FINE RDL STRUCTURES IN ADVANCED PACKAGING BY EXCIMER LASER ABLATION NCCAVS Joint Users Group Technical Symposium San Jose, June 7 th, 2017 Markus Arendt, SÜSS MicroTec

More information

Plasma for Underfill Process in Flip Chip Packaging

Plasma for Underfill Process in Flip Chip Packaging Plasma for Underfill Process in Flip Chip Packaging Jack Zhao and James D. Getty Nordson MARCH 2470-A Bates Avenue Concord, California 94520-1294 USA Published by Nordson MARCH www.nordsonmarch.com 2015

More information

Challenges in Material Applications for SiP

Challenges in Material Applications for SiP Challenges in Material Applications for SiP Sze PeiLim Regional Product Manager for Semiconductor Products Indium Corporation Indium Corporation Materials Supplier: SMT solder pastes and fluxes Power semiconductor

More information

JOINT INDUSTRY STANDARD

JOINT INDUSTRY STANDARD JOINT INDUSTRY STANDARD AUGUST 1999 Semiconductor Design Standard for Flip Chip Applications ASSOCIATION CONNECTING ELECTRONICS INDUSTRIES Semiconductor Design Standard for Flip Chip Applications About

More information

Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste

Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste Cost Analysis of Flip Chip Assembly Processes: Mass Reflow with Capillary Underfill and Thermocompression Bonding with Nonconductive Paste Amy Palesko Lujan SavanSys Solutions LLC 10409 Peonia Court Austin,

More information

Motorola PC603R Microprocessor

Motorola PC603R Microprocessor Construction Analysis Motorola PC603R Microprocessor Report Number: SCA 9709-551 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:

More information

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview Revision 0 2006 Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the

More information

Compression molding encapsulants for wafer-level embedded active devices

Compression molding encapsulants for wafer-level embedded active devices 2017 IEEE 67th Electronic Components and Technology Conference Compression molding encapsulants for wafer-level embedded active devices Wafer warpage control by epoxy molding compounds Kihyeok Kwon, Yoonman

More information

Fundamentals of Sealing and Encapsulation

Fundamentals of Sealing and Encapsulation Fundamentals of Sealing and Encapsulation Sealing and Encapsulation Encapsulation and sealing are two of the major protecting functions of IC packaging. They are used to protect IC devices from adverse

More information

Development of System in Package

Development of System in Package Development of System in Package In recent years, there has been a demand to offer increasingly enhanced performance for a SiP that implements downsized and lower-profile chips at lower cost. This article

More information

Warpage Mechanism of Thin Embedded LSI Packages

Warpage Mechanism of Thin Embedded LSI Packages Nakashima et al.: Warpage Mechanism of Thin Embedded LSI Packages (1/10) [Technical Paper] Warpage Mechanism of Thin Embedded LSI Packages Yoshiki Nakashima*, Katsumi Kikuchi*, Kentaro Mori*, Daisuke Ohshima**,

More information

Development of Super Thin TSV PoP

Development of Super Thin TSV PoP Development of Super Thin TSV PoP by Seung Wook Yoon, *Kazuo Ishibashi, Shariff Dzafir, Meenakshi Prashant, Pandi Chelvam Marimuthu and **Flynn Carson STATS ChipPAC Ltd. 5 Yishu n Street 23, Singapore

More information

THROUGH-SILICON interposer (TSI) is a

THROUGH-SILICON interposer (TSI) is a Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling Fa Xing Che, Masaya Kawano, Mian Zhi Ding, Yong Han, and Surya Bhattacharya

More information

Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages

Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages Board Level Reliability Improvement in ewlb (Embedded Wafer Level BGA) Packages by Seng Guan Chow, Yaojian Lin, Bernard Adams * and Seung Wook Yoon** STATS ChipPAC Ltd. 5 Yishun Street 23, Singapore 768442

More information

Two Chips Vertical Direction Embedded Miniaturized Package

Two Chips Vertical Direction Embedded Miniaturized Package Two Chips Vertical Direction Embedded Miniaturized Package Shunsuke Sato, 1 Koji Munakata, 1 Masakazu Sato, 1 Atsushi Itabashi, 1 and Masatoshi Inaba 1 Continuous efforts have been made to achieve seemingly

More information