2015 Board Assembly Roadmap

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1 2015 Board Assembly Roadmap Jasbir Beth-Rework Chair Dennis Willie-Pressfit Chair Leigh William Gesick, Material Chair Mike Gerner-NPI Chair Brent Fischthal-Placement Chair TWG Chair-Paul Wang, Ph.D, MBA 2015 roadmap Webinar April 9 th, 2015 Rev.05

2 Contain Board Assembly NPI, Assembly Material Press-Fit, Repair and rework ESD challenging vs. HBM and CDM Summary 1

3 New Product Introduction (Chair: Mike Gerner) Functional verification/testing Design verification, Quick turn, less focus on DFM Proof of concept Functional verification on integration of multi-card full system Mfg Readiness Final design release, design rule/dfm, testing verification Ramp to volume Yield optimization and supply chain management 2

4 New Product Introduction (Chair: Mike Gerner) DfR (design for relibaility) Early stage computer-aided design (CAD), Finite element (FEA), thermal simulation (CFD) DRfR (design review for relibaility) Automate design review in design rule data base APQP (advanced product quality planning) CLE2E DFM, D-FMEA, P-FMEA 3D printing Mechanical fiting Rationalize from the concept to product 3

5 New Product Introduction (Chair: Mike Gerner) The CLE2E (Closed-Loop and End to End) product life cycle management (PLM) Maturity of Physical life model and statistic enable robust PLC management 4

6 New Product Introduction (Chair: Mike Gerner) 3D printing Mechanical fitting Rationalization from the concept to Rapid Prototyping Reference: 德芮達科技 Detekt 5

7 Assembly Material (Chair: Leigh William Gesick) Continuous Lead-Free solder and low silver SAC Halogen free prevail overtime for flux Parameter Metric Solder Pastes Wave Solder Fluxes Lead-free NA* Lead-free WW** Halogen-free NA Halogen-free WW Low Temp Lead-free Assembly Alloys (Lead-free) 50% 50% 60% 70% 95% 70% 70% 70% 80% 95% 10% 10% 20% 40% 85% 25% 25% 40% 60% 95% <1% <1% <1% 5% 10% SAC/ SAC/ SAC/ SAC/ SAC/ Modified SnCu/ Low Ag SAC Modified SnCu/ Modified SnCu/ Modified SnCu/ Modified SnCu/ Low Ag SAC/ Low Ag SAC/ Low Ag SAC/ Low Ag SAC/ Low Temp Low Temp VOC free 10% 10% 10% 15% 20% Halogen free 10% 10% 20% 40% 70% 6

8 Assembly Material (Chair: Leigh William Gesick) Underfill two strengthening mechanisms Type CSP / BGA DCA (Direct Chip Attach) Purpose Improved vibration and impact resistance Maintain joint integrity during thermal and power cycling Parameter Metric Underfills Low-k ILD Pre-applied FC Large Die JEDEC 260 JEDEC 260 JEDEC 260 JEDEC nm tech 45 nm tech 45 nm tech 45 nm tech JEDEC L2@ mm lowk JEDEC 260 JEDEC 260 JEDEC 260 JEDEC and below nm tech JEDEC mm low-k 30 mm low-k 30 mm low-k 30 mm low-k CSP Reworkable Reworkable Reworkable Reworkable Reworkable >> 25% 7

9 Press-Fit (Chair: Dennis Willie) Press-fit for electrical and mechanical interconnection Board connector to press-fit interface then to other board Backplanes, Mid-planes and Daughter Card Connectors to avoid challenges associated with soldering, rework, thermal cycles, installation and repair. EON (Eye of the Needle) Style Compliant Pin and Cross Sectional View within PCB. Press Fit Connectors Installed on PCB 8

10 Press-Fit (Chair: Dennis Willie) Press Fit Connector Key Attribute Roadmap 9

11 Press-Fit (Chair: Dennis Willie) Press Fit quality and inspection Bent under Pin Broken off pin Crushed pin Deflected/deformed pin Typical Press-fit Compliant Pin Faults X-ray of bent-under and crushed EON pins on a backplane 10

12 Press-Fit (Chair: Dennis Willie) Press Fit quality and inspection GBX press-fit bent pin with TDR data 11

13 Press-Fit (Chair: Dennis Willie) Press Fit quality and inspection 3D automated press-fit profiling inspection (metrology) 12

14 Repair and Rework (Chair: Jasbir Beth) Hand soldering technology trend Soldering Process Pb-free Parameter Units Soldering iron peak temperature used Total contact time Smallest pitch to be reworked by hand Smallest type of discretes being reworked (Imperial) Type of wire alloy used C sec mm SAC305/ SnCuNi (low tip dissolution alloys) SAC305/ SnCuNi (low tip dissolution alloys) SAC305/ SnCuNi (low tip dissolution alloys) SAC305/ SnCuNi (low tip dissolution alloys) (0201 metric) SAC305/ SnCuNi (low tip dissolution alloys) 13

15 Repair and Rework (Chair: Jasbir Beth) Hand soldering technique Hand Solder Rework Pitch and Components Hand Solder Rework Soldering Parameter Units Process SnPb Pb-free Smallest pitch to be reworked by hand Smallest type of discretes being reworked Smallest pitch to be reworked by hand Smallest type of discretes being reworked Mm (Imperial) 0201 (Imperial) (Imperial) (Imperial) (Imperial) Mm (Imperial) 0201 (Imperial) (Imperial) (Imperial) (Imperial) 14

16 Repair and Rework (Chair: Jasbir Beth) Cu-dissolution and rework defect Convection Connector Rework Temperatures (Ref: VJ Electronix) Overall Board Bottomside Preheat Temperature Localized Bottomside PCB Temperature Localized Topside PCB Temperature Single Point Rework C C C Connector Removal C C C Barrel Scavenge C C C Connector Replace C C C Copper Dissolution and Insufficient Hole fill (Ref: Celestica 2007) 15

17 New ESD challenging From the failure analysis data collected in the past several years, it can be observed that ESD failure has been increasing. About half of failure were induced by ESD(Electro-Static discharge) or EOS(Electronic Over Stress). It is difficult to distinguish ESD or EOS because EOS always is the final failure symptom but it could be hurt by ESD firstly. 16

18 What has Changed From device ESD threshold roadmap (ESD Association it can be seen that ESDs become more sensitive. Some devices will start seeing 100 V to 200 V HBM and 125V to 250 V CDM for the target level within the next few years. 17

19 What has Changed From device ESD threshold roadmap (ESD Association it can be seen that ESDs become more sensitive. Some devices will start seeing 100 V to 200 V HBM and 125V to 250 V CDM for the target level within the next few years. 18

20 Case -1 High failure return rate(1~12%) was found at a switch MOSFET. After failure analysis, it was disclosed all of them were damaged by ESD

21 Case -1 After check with the suppliers, this switch 2N7002 N channel MOSFET that is being used has very low ESD rating with 25V~100V HBM. And CDM threshold is not provided in data sheet since very few MOSFET manufacturer have equipments to make CDM validation. Page 20 20

22 Case -2 Another case below is a BGA. It was damaged by CDM ESD Event. More and more CDM ESD events appeared in recently years which much different from before. Page 21 21

23 Case -3 Case of ESD damaged power controller chip: The true Failure mode is Diode problem from Silicon process Page 22 22

24 ESD Challenging Resolution Quantitative ESD assessment, mitigation, process/technology change Extended ESD capability measurement needs to be understood and implemented to face the challenging The capability involves dynamic charge voltage and dynamic ground resistance measurement, charging control of insulator and boards When there is risk identified, mitigation plan can be -- Avoid hard discharge -- Use ionizer to discharge the charging of insulator -- Replace the sensitive part by higher ESD rating --OCP overstress current protection circuit Page 23 23

25 NPI Executive Summary evolve to use use DRfR and CLE2E for robust product Life Cycle management 3D printing to Rationalization from the concept to Rapid Prototyping Assembly material Continuous Lead-Free solder and low silver SAC Halogen free prevail overtime for flux Press-Fit Technology evolution for higher data rate and smaller dimension Repair and Rework Technique to accommodate miniaturization in pitch and smaller component ESD capability evolution to match HBM and CDM of component challenging Quantitative process capability ESD protection Design 24