RISC-V SoC Hierarchical Verification Block to Top Level. Jeremy Ralph - Verification Consultant November 13, 2018

Transcription

1 RISC-V SoC Hierarchical Verification Block to Top Level Jeremy Ralph - Verification Consultant November 13, 2018

2 Imagine: This SoC Needs Verification CPU Subsystem Subsystem A Subsystem B Trade-offs Quality Schedule Product scope Costs (engineers, tools, compute, IP) Assume Quality + Schedule CPUSS is pre-verified Page 2

3 Start with a Documented Methodology Ground rules Share best practices Design and Architecture for Verification Decoupled small blocks with a spec No logic outside of block Scheduling, reporting, indicators Virtual platform Imperas UVM, FPV, low power UPF Page 3

4 SoC Project Verification Planning Environment partitioning VIP sourcing Reuse strategy Assignments Page 4

5 Block Level Verification CPU Subsystem Subsystem A Subsystem B Verify each block s features as specified Constrained-random Functional coverage plan Review, revise, prioritize Hit 100% goal(s) Focus on coverage, not tests Page 5

6 Subsystem Verification CPU Subsystem Subsystem A Subsystem B Subsystem A and B Verify interactivity, connectivity, performance Less random HUGE alignment challenge Vertical Reuse Organizational debug Page 6

7 Full SoC-Level Verification CPU Subsystem Subsystem A Subsystem B Verify interactivity, connectivity, performance, programmers view Directed C/C++ on CPU Simulation / Emulation SystemVerilog BFM sequencing, checking Vertical reuse is debatable Page 7

8 RISC-V Verification and [ riscv-vip ] CPU Subsystem RISC-V Core Subsystem A Subsystem B [ riscv-vip ] Open-source SystemVerilog with UVM Functional coverage Runtime trace Check it out at github.com/jerralph/riscv-vip

9 Summary Methodology Tactical SoC Verification Plan Block Level Subsystem Level Full SoC Level RISC-V configurations, customizations = Verification challenges, functional coverage can help Page 9

10 Thank You Please visit our booth and website XtremeEDA Engineering Jeremy Ralph, Principal DV Eng XtremeEDA Sales Jim Nash, VP Sales Mobile: (508)

11 Long History of Trust with Clients Page 11

12 Client Testimonials XtremeEDA has been a pleasure to work with. We can count on XtremeEDA to provide the senior talent required to attack our most challenging Verification IP development projects. We treat our XtremeEDA team members as if they are our direct employees, and they work seamlessly with our team members. We primarily use remote team members, and this has been refreshingly successful. Engineering Director "I've been incredibly impressed with the quality and dedication of the XtremeEDA consultants that we've had working for us. When we need verification consultants again in the future, they will be the first person I call. ASIC Engineering Manager I have been very impressed with the professionalism and technical competence of the Engineers and the Management at XtremeEDA. When we look for ASIC Verification help we always start with XtremeEDA as they have a strong history of success with our team and they continue to provide flexible access to very experienced talent. ASIC Development Manager "XtremeEDA stands out among the crowd of outsourced resources I've worked with over the years. They do so not only with the quality of their engineering team but also with a uniquely strong focus on the customer relationship, showing tremendous flexibility with engagement models (i.e. selection, timing, scope) and creative pricing models. ASIC Verification Program Manager Page 12

13 XtremeEDA: Corporate Overview Company Profile Founded in 2002, HQ in Ottawa, US HQ in Austin, TX All engineers are full-time employees with >22 years average experience Reputation for Fairness, Honesty, Trustworthiness, Reliability and Top Quality Performance Strategic partnerships with Andes Technology (RISC-V) and Sondrel (Physical Design) Design and Verification Experts Focused on SoC, ASIC, IP and FPGA ARM and RISC-V Processor experience Architecture, Design and Implementation (RTL) Digital Design Verification in UVM (DV) Analog Modeling and Mixed-Signal Verification (AMS) Program & Project Management (PM) Project Based Engagement Model Full ASIC Development (from Specification to GDSII) IP and Subsystem Development VIP Development RTL and DV Team Augmentation for large SoC designs Page 13