JS-002 Module and Product CDM Result Comparison to JEDEC and ESDA CDM Methods

Transcription

1 JS-002 Module and Product CDM Result Comparison to JEDEC and ESDA CDM Methods A. Righter (Analog Devices Inc.) [1], R. Ashton (ON Semiconductor), B. Carn (Intel), M. Johnson (Texas Instruments), B. Reynolds (Global Foundries), T. Smedes (NXP Semiconductors), S. Ward (Texas Instruments), H. Wolf (Fraunhofer EMFT) (1) Analog Devices, 804 Woburn St, M/S 613, Wilmington, MA USA tel.: , fax: , Abstract - CDM standard JS-002 is introduced, including the reasons for its development and the technical issues the new standard addresses. JS-002 is compared to the JEDEC JESD22-C101, ESDA and AEC Q100 CDM standards in terms of waveforms and integrated circuit pass/fail levels. JS-002 robustness levels are similar to JEDEC CDM levels. I. Introduction This paper introduces the new joint JEDEC/ESDA charged device model (CDM) test standard JS-002 [1] and presents data comparing it with the legacy JEDEC (JESD22-C101) [2], ESDA S5.3.1 [3] and AEC Q [4] CDM test methods. It is well known that the largest cause of ESD damage to integrated circuits (IC) during device handling in a manufacturing environment is from charged device events [5]. It is therefore vitally important that the level of charged device immunity ICs have is well known to ensure the CDM ESD design strategy has been implemented correctly and that the IC s charged device immunity is matched to the level of ESD control in the manufacturing environment to which it will be exposed. It is for this reason that CDM test methods were developed; providing a metric for IC charged device immunity robustness. A challenge to the industry has been that there have been four CDM test standards, the JEDEC, ESDA, and AEC standards which use field induced charging and the JEITA [6] standard which uses direct charging. While all of these methods produce valuable information, the presence of several standards is not a benefit to the industry. The different methods often produce different passing levels, and the presence of several standards requires manufacturers to support multiple test methods with no increase in meaningful information. II. Goals and Basics of JS-002 A. Goals of JS-002 JS-002 has been developed to replace the separate JEDEC and ESDA standards. Additionally, the joint working group (JWG) wanted to make technical improvements to the field induced CDM (FICDM) method based on lessons learned since FICDM was introduced [7]. Finally the JWG wanted to minimize disruption in the electronics industry. To reduce industry disruption the working group decided that the joint standard should not require purchasing of totally new field induced CDM testers and pass/fail levels should be matched as close as possible to the JEDEC CDM standard, the most widely used CDM standard. While the JEDEC and ESDA test methods are very similar there are a number of differences between the standards which needed to be resolved. There are also technical issues which JS-002 seeks to address. Some of the most important issues are listed below. Differences between the standards o Field plate dielectric thickness o Calibration modules used to calibrate systems o Oscilloscope bandwidth requirements o Calibration waveform parameters Technical issues with standards o Measurement bandwidth requirements too slow for CDM o Pulse width in JEDEC s standard is artificially wide

2 o Waveform and equipment geometry requirements forced hidden voltage adjustments. B. Basics of JS-002 To address the objectives and harmonize, the following choices were made. Note that extensive measurements were made in arriving at these decisions. Hardware Choices o Use the JEDEC dielectric thickness o Use the JEDEC coins for system calibration and verification o Forbid use of ferrites in the measurement chain Measurement Bandwidth o Require a 6 GHz minimum bandwidth oscilloscope for system calibration/acceptance o Allow the use of 1 GHz oscilloscope for routine system verification Minimization of data disruption and hidden voltage adjustments o Match real peak currents with JEDEC standard o Specify Test Conditions matching JEDEC stress levels. For JS-002 test results, we refer to Test Conditions (TCs) and for JEDEC and AEC we refer to Volts. o Field plate voltage adjusted for JS-002 to provide correct peak current corresponding to JEDEC peak current requirements. III. JS-002 High Bandwidth Multisite Module Data Figure 1 presents composite (over one dozen test platforms) large JEDEC verification module average Ipeak data taken with high bandwidth oscilloscopes (>= 6 GHz). This data formed the basis for the large module Ipeak high bandwidth waveform parameters published in Section 6.7 of JS-002. The calibration procedure calls out the 500V test condition voltage as the starting calibration voltage and this is reflected in the narrower variance in the TC500 values compared to other TC voltages in Figure 1. Figure 2 shows similar composite average Ipeak data for the small JEDEC verification module taken with the same oscilloscopes at each site, forming the basis for the small module high bandwidth Ipeak waveform parameters in JS-002 Section 6.7. Figure 1: Average Ipeak data for the large JEDEC verification module across over a dozen JS-002 test platforms taken with high bandwidth (>= 6 GHz) oscilloscopes. Figure 2: Average Ipeak data for the small JEDEC verification module across over a dozen JS-002 test platforms taken with same high bandwidth oscilloscopes. IV. Product JS-002 Case Studies A. Parts Tested In Studies Table 1 presents products tested for pass / fail comparison (A, B and C) and peak current comparison (D) between JS-002, JEDEC and ESDA test methods. Product Table 1: Products in Test Comparison Technology Package A 40nm CMOS LQFP64 B 40nm CMOS LQFP64 C 65nm CMOS 184BGA D 0.35um CMOS 20 QFN B. 40nm Products A and B Two different IO libraries in the same technology node have been evaluated for CDM robustness with JS-002 and ESDA. In all cases, a plastic LQFP64 package was used. Three samples were used per level;

3 each sample was stressed on all pins with three positive and three negative discharges. For each run, samples were stressed at 200 V, 500 V, 750 V, 800 V, 900 V, 1000 V, 1500 V and 2000 V. The pass/fail levels are given in Table 10. The electrical failure signature was identical in all cases, Iddq increase in a thin gate oxide domain. All discharges were recorded in order to be able to analyze the results and compare between standards. Figure 3 shows the distribution of peak current divided by the stress level as a function of the stress level for 2 methods, both for an individual pin and for the full set of discharges. It illustrates that the peak current in the JS-002 method has slightly less spread and is more constant as a function of stress level. Current/Stress Level (A/kV) Current/Stress Level (A/kV) Jedec JS Stress Level (V) Jedec JS Stress Level (V) Current (A) A/JS002 A/ESDA A/Jedec B/JS002 B/ESDA B/Jedec Product/Method Figure 4: Comparison of failure peak currents and the +/- 3 sigma limits for 2 products and 3 CDM methods for Products A and B. To establish an equivalence, it is important that the stress methods result in the same failure mode. The electrical failure signature was identical in all cases, both for product A and product B: increased Iddq in a domain controlling the state of another part of the product. Thus it is likely that the physical damage is also equivalent. Failure analysis was performed on product B to verify this. Figures 5 and 6 show the results of OBIRCH failure localization and SEM physical inspection respectively for a sample that failed after ESDA The transistor identified by OBIRCH has clear gate oxide damage. This transistor receives its gate signal from the domain with the increased Iddq. Thus the physical damage explains the electrical failure signature. Figure 3: Distribution of peak current vs. stress level for product B. Top: a random pin; Bottom: all pins combined Figure 4 shows the average peak current and the +/- 3 sigma limits of its distribution at the failure levels of product A for two methods and for product B for three methods. It is clear that the failure regions overlap significantly, indicating that JS-002 addresses the same weakness as the other methods and actually produces the damage at the same amount of This data also illustrates that JS-002 produces a better pulse-to-pulse repeatability. Figure 5: OBIRCH signal of damage on Product B after ESDA

4 Figure 6: SEM photograph of damage on Product B after ESDA A similar analysis was conducted on a sample stressed with the JS-002 method. The OBIRCH and SEM results are shown in Figures 7 and 8 respectively. The OBIRCH and SEM are very similar to those found for the ESDA stressed sample. The damaged transistors in the SEM photos of Figure 6 for JEDEC and Figure 8 for JS-002 are not the same transistor in the physical circuit, but are equivalent transistors in similar control gates. The product contains dozens of such control gates. Figure 8: SEM photograph of damage on Product B after JS-002 C. Product C The 65nm product C in this study had a number of high frequency low capacitance pins having known pass/fail negative CDM levels of 125 V pass / between 150 V and 175 V fail according to JESD22C101. First calibration of an Orion2 CDM tester with an ESDA probe assembly (according to JS-002 waveform specifications, using a 6 GHz oscilloscope) resulted in the voltage setting correction factor for each JS-002 Test Condition being 10% less than JEDEC voltage levels to achieve the same peak current. (This is on the lower end of the range determined for JEDEC to JS-002 correction factors seen by the CDM Joint Working Group.) Comparison waveform data between the JEDEC and JS-002 measurements for the small (6.6 pf) JEDEC module are shown in Table 2. It is observed that the rise times and full widths at half maximum are noticeably faster for JS-002 than for JESD22-C101. Table 2: 6.6 pf module JESD22-C101 (500V) vs. JS-002 (450V) Tester Ipeak (A) Tr (ps) FWHH (ps) C JS Figure 7: OBIRCH signal of damage on Product B after JS-002 JS-002 testing from this calibration resulted in reduced pass/fail levels (TC-125, -113 V / TC-150, 135 V) compared to JESD22-C101 (-155 V, -150 V).

5 Electrical test results showed similar test failure signatures. Figure 9 shows example waveforms on a GND pin for both methods. Comparison waveform data of a ground pin for both JS-002 and JESD22- C101 is shown in Table 3. Comparison waveform data of a high frequency pin for both JS-002 and JESD22- C101 is shown in Table 4. was found that the tester ESDA probe assembly contained a ferrite which could not be removed due to its being soldered into the test head cavity. It is instructive to note that many ESDA probe assemblies in use today do not contain a ferrite and can be suitable for use. A second calibration of this same CDM tester was done, using an 8 GHz oscilloscope, with the tester having a new manufacturer probe assembly verified to have no ferrite. The lack of a ferrite resulted in an increase of the peak current (at a given test condition voltage) compared to the first results. Thus further reduction of the plate voltage was necessary to approximate the same peak currents between JS-002 and JEDEC. Comparison waveform data between the JEDEC and JS-002 measurements for the large (55 pf) JEDEC module (start point of the calibration) are shown in Table 5. It is observed that the rise times and full widths at half maximum are noticeably faster for JS-002 than for JESD22-C101. Table 5: 55 pf module JESD22-C101 (500V) vs. JS-002 (TC500, 325V) C Figure 9: JEDEC -125V (30 mv/div, 2 ns/div) and JS-002 TC-125 (40 mv/div, 1 ns/div) AGND waveforms. 10X probe used. Table 3: Product C GND pin C JS JS Table 6: 6.6 pf module JS-002 (TC500, 325V) JS Table 4: Product C HF pin C JS After this first product C measurement, a review of the data showed the JS-002 rise time in Table 2, although faster than for JESD22-C101, was too high and outside the JS-002 specification of <250 ps. It JS-002 testing for Product C from the second calibration (new probe assembly) resulted in a comparable distribution of pass/fail tests by level compared to JESD22-C101. Electrical test results showed similar test failure modes between the two methods. A breakdown of the test results by voltage is given in Table 7. It is noted that there is some local difference in the tests that failed at a particular voltage between the two methods, but within the range overall, there is some correlation. It is to be expected that for low test voltages in the 125V and below range, the field-induced method will have variations in the spark resistance which can produce local variations in test results.

6 Table 7: Product C Test Results JS-002 vs. JESD22-C101 Figure 10 shows example waveforms on an AGND pin for both methods. Tabular results of the AGND pin for both JS-002 and JESD22-C101 are shown in Table 8. Tabular data of a high frequency pin for both JS-002 and JESD22-C101 is shown in Table 9. Table 9: Product C HF pin C JS D. Pass/Fail results comparison Table 10 shows the test method comparison results for the three products with pass/fail data. The pass/fail results obtained with the JS-002 are comparable to those obtained with legacy methods. Product Table 10: Product CDM Test Comparison JS-002 P/F (Test Cond) JEDEC P/F (V) AEC P/F (V) A 800/ /900 B 750/ / /750 C Figure 10: JEDEC -125V (30 mv/div, 2 ns/div) and JS-002 TC Amp/div, 4 ns/div) AGND waveforms. 10X probe used. Table 8: Product C GND pin C JS E. Product D Peak Current Comparison Figure 11 shows the comparison of discharge peak currents for JEDEC (750 V) and the JS-002 (TC 750) testing of a CMOS ASIC in a 20 pin QFN package. The data were obtained during the product qualification on a CDM tester in combination with

7 Figure 11: Comparison of the peak discharge currents of a CMOS ASIC in a QFN20 package for JEDEC and JS-002. a 4 GHz bandwidth oscilloscope (Tektronix TDS7404). The characterization waveforms of the discharge heads for the JEDEC standard and JS-002 complied well with the waveform characteristics published in each standard. The tested devices (3 pulses per pin and polarity) have passed both stress levels for both standards. The data set (with limited statistics and significant variation due to air discharge) shows a tendency with few outliers that the JS-002 stress currents slightly exceed the JEDEC stress in terms of peak current, however the JS-002 data points tend to have a tighter distribution. V. Conclusion For the first time practical results obtained with the new CDM standard, JS-002, are presented. The paper collects results for verification modules and products obtained with different CDM testers in different labs. Both calibration and qualification results are shown. Results were compared with those obtained with testers meeting the legacy CDM standards. The pass/fail results obtained with the JS- 002 were comparable with those obtained with legacy methods. More importantly, the failure level in terms of peak current and the obtained failure signatures showed good correlation. From waveform evaluations, it is observed that the JS-002 demonstrates somewhat lower variation than the legacy methods. Acknowledgements The authors gratefully acknowledge the work of the ESDA/JEDEC Charged Device Model Joint Working Group for their extensive data gathering and work to harmonize the platform and test methodology into a common standard and document. References [1] ANSI/ESDA/JEDEC JS , Charged Device Model (CDM) Device Level, EOS/ESD Association, April [2] JESD22-C101F, Field-Induced Charged-Device Model Test Method For Electrostatic Discharge Withstand Thresholds Of Microelectronic Components, JEDEC, October [3] ANSI/ESD S5.3.1, Charged Device Model (CDM) Component Level, EOS/ESD Association, December 2009, obsoleted by [1] in April [4] AEC-Q , Charged Device Model (CDM) Electrostatic Discharge Test, Automotive Electronics Council, July [5] R. J. Peirce, The Most Common Causes of ESD Damage, Evaluation Engineering, November [6] EIAJ ED-4701/300-2, Test Method 305, Charged device model electrostatic discharge (CDM-ESD), Japan Electronics and Information Technology Industries Association, June [7] A. W. Righter et al, Progress Towards a Joint ESDA/JEDEC CDM Standard: Methods, Experiments and Results, Proc EOS/ESD Symposium, paper 1B.1.