Expanding the Reach of Formal. Oz Levia November 19, 2013

Transcription

1 Expanding the Reach of Formal Oz Levia November 19, 2013

2 Agenda Jasper Our Product Strategy and Apps Design Coverage App What will it mean to you? Page , Jasper Design Automation All Rights Reserved.

3 Jasper s Business Predictable: Ratable subscription software 90%+ annual renewal rate Fast-growing: 35% CAGR since 2007 Growing 6 times faster than the EDA industry Profitable: 14 consecutive quarters 15-20% EBITDA Bookings Revenue Target Page , Jasper Design Automation All Rights Reserved.

4 A Closer Look at Jasper Growth Metrics Compound Annual Growth Rates (CAGR) since 2010: Metric CAGR Jasper Revenue 37% Number of Customer Logos 11% Number of Users 79% Number of Licenses 129% Page , Jasper Design Automation All Rights Reserved.

5 Jasper: Growth Strategy Create solutions to specific customer problems We don t provide a single TOOL We provide Application Specific Solutions (Apps) We don t accept limitations of size, capacity and speed Extend the solution to fit the problem(s) Divide & conquer verification into sub-tasks addressed by numerous optimized micro-solutions (vs. one-size-fits-all) Page , Jasper Design Automation All Rights Reserved.

6 Upgrade your Verification with Jasper JasperGold Apps Common Database Common Interface Simplified Interaction Between Apps Flexible Deployment Intelligent Proof Kits and Verification IPs Certification of AMBA 4/ACE checkers Popular standard protocols Configurable, illustrative, optimized for formal Formal Property Verification App Protocol certification End-to-end packet integrity Asynchronous clocking effects Assertion-based verification Proofs for critical functionalities Debug isolation and fix validation Architectural Modeling App Pre-RTL modeling Capture executable spec Absence of deadlock Cache coherency verification Liveness and latency Low Power Verification Connectivity Verification App Properties automatically extracted from table input Sub-system and Chiplevel connectivity Conditional connection with latency Creating power-aware formal model Automatic extraction of power-related functionality and sequencing properties Formal verification of power optimized SoCs X-Propagation Verification App Automatic property generation Unexpected X detection and debugging Design Coverage Verification Coverage metrics generation from formal verification Coverage metrics to establish quality of formal testbench and for bounded/full proof result Interacting with coverage metrics from simulation via an external DB (e.g. UCDB) Control/Status Register Verification App Comprehensive Standard and proprietary protocols Sequential Equivalency Checking Sequential, temporal and functional equivalence verification Multi-value logic Full chip capacity Security Path Verification Behavioral Property Synthesis Synthesis of multi-cycle, handshake, implication, black-box, and white-box properties from simulation Automated and manual property ranking and classification Feedback properties into formal or simulation environments VCD, FSDB and PLI support Identify unintentional/ illegal read access to secure data (leakage) Verify absence of illegal secure data overwrite (sanctity) Fault-tolerant security verification Post-Silicon Debugging Failure signature matching Root cause isolation Candidate cause elimination Validation of fixes before re-spin Structural Property Synthesis Automatic checks from RTL such as arithmetic overflow, dead code, FSM Livelock/Deadlock states Automated and manual property ranking and classification Feedback properties into formal or simulation environments Other SoC-Related Applications IPXACT Designer-based verification w/o testbench Glitch detection System-level deadlock Higher Capacity Verify complex 100M+ gate designs Interactive Debug Modify/create properties on the fly to explore design behavior Increased Throughput Utilize multiple proof engines on parallel compute resources Wider Deployment Proliferate across engineering teams with unique adoption model Page , Jasper Design Automation All Rights Reserved.

7 Jasper s Coverage-Driven Verification Strategy Provide solutions to accelerate the overall verification coverage closure process. 1. Use formal to help identify holes and unreachables in your simulation (via UCIS/UCDB) 2. Provide coverage metrics for formal verification to establish confidence in formal results, and eliminate redundant simulation tasks Page , Jasper Design Automation All Rights Reserved.

8 Formal-Specific Coverage Metrics Measuring completeness of a formal testbench Stimuli coverage: completeness of stimuli applied to the design under the given set of constraints Property completeness: Completeness of property set applied to the DUT Measuring verification coverage after formal analysis Proof coverage: coverage for properties fully proven Bounded proof coverage: coverage for properties with bounded proofs Benefits Protect against the potential over-constraint problem to eliminate false confidence in design correctness Provides an empirical measurement of the ROI of your formal verification Page , Jasper Design Automation All Rights Reserved.

9 Measuring Property Completeness RTL Property Coverage Reporting Design Coverage Verification Branch coverage Statement coverage Fault coverage* Assertions JasperGold w/visualize Textual Report GUI-based Report Jasper DB Constraints Bottom-line Users can empirically determine the sufficiency of their formal testbench * Coming in future release Page , Jasper Design Automation All Rights Reserved.

10 Property Completeness Coverage Illustrated Determine the cover items in the COI of each assertion Find the union of the assertion COIs The remaining out-of-coi cover items indicate holes in the property set at this hierarchical level Design P0 COI P1 COI Out of COI cover items P2 COI P3 COI P4 COI Page , Jasper Design Automation All Rights Reserved.

11 Example Property Completeness Report: Sample Outside COI Out-of-COI report widget Hierarchical Report Results GUI highlighting out-of-coi code Page , Jasper Design Automation All Rights Reserved.

12 Example: Coverage Measurement from Bounded Proofs RTL Design Coverage Verification Bounded Proof Coverage Reporting Branch coverage Statement coverage Expression coverage* Functional coverage Assertions JasperGold w/visualize Textual Report GUI-based Report Jasper DB Constraints Bottom-line Valuable verification progress info is available even if a property is not yet proven. * Coming in future release Page , Jasper Design Automation All Rights Reserved.

13 Sample Bounded Coverage Report Hierarchical Report Results GUI highlighting of unverified code First cycle where code becomes reachable Assertion bound Page , Jasper Design Automation All Rights Reserved.

14 Case Study: D&V Group In UK Background Customer D&V engineering group focused on ARM-based CPU peripherals IPs include sensor controllers, clock & reset management blocks Engineers were moderately familiar with ABV / formal Process Used Coverage App to eliminate all dead code / work toward 100% code coverage goal Used App to confirm there was no over-constraining Leverage data from bounded proofs to increase coverage Benefits Were able to quickly meet the project s for coverage closure specification Very high satisfaction with the results given the Coverage app / underlying formal analysis exhaustively exercised all functionality Page , Jasper Design Automation All Rights Reserved.

15 In the Future Jasper's formal technology will continue to expand to support larger designs, larger problems, and more types of problems Jasper will continue to push formal into spaces that were previously not conceived as applicable for formal Users will continue to see more and more ROI from Jasper's formal solutions, creating a positive feedback loop of more usage, more users, and even higher ROI Page , Jasper Design Automation All Rights Reserved.

16 Scaling Much Faster Than Moore s Law Moore s Law states that the number of transistors on an IC doubles every two years That equates to a CAGR of 42% Compare to Jasper Formal Analysis: Max Design Size CAGR Number of gates 86,000 >100,000,000 >104% Page , Jasper Design Automation All Rights Reserved.

17 What This Will Mean to You Someday Formal will be your default choice for virtually every verification task The tools will have the capability to selectively apply the right heuristics for each situation, under-the-hood The tools will guide the user s learning process, and will produce the needed metrics for management Engineering productivity will sky-rocket Page , Jasper Design Automation All Rights Reserved.

18 FORMAL WILL DOMINATE VERIFICATION Kathryn Kranen October 22, 2013