Testbench Automation. Adam Rose Product Market Manager Questa Verification IP

Transcription

1 Testbench Automation Adam Rose Product Market Manager Questa Verification IP

2 Advanced Verification The promise 15 years ago Reuse From Project to Project From block level to system level Coverage and Verification Management How do we know we re done? Project Management, Metrics Constrained Random Directed testing finds the known unknowns Constrained Random finds the unknown unknowns 2

3 ASIC/IC Mean Peak Number of Engineers Number of Peak Engineers Increasing 25 CAGR Designers 3.6% CAGR Verifiers 10.4% Verification Engineers Design Engineers Source: Wilson Research Group and Mentor Graphics, 2016 Functional Verification Study 3 H Foster, WRG Functional Verification Study, July 2016

4 ASIC/IC Mean Peak Number of Engineers More Verification Engineers vs Design Engineers CAGR Designers 3.6% CAGR Verifiers 10.4% Design Engineers Verification Engineers Source: Wilson Research Group and Mentor Graphics, 2016 Functional Verification Study 4 H Foster, WRG Functional Verification Study, July 2016

5 FPGA Mean Peak Number of Engineers More Verification Engineers vs Design Engineers Verification Engineers Design Engineers Source: Wilson Research Group and Mentor Graphics, 2016 Functional Verification Study 5 H Foster, WRG Functional Verification Study, July 2016

6 Why so much Time and Money on Verification? Complexity of Methodology AVM in 2006 : 6,000 lines of code UVM in 2016 : 75,000 lines of code Delivers re-use but hard to get up and running Complexity of VIP Protocols themselves are complex and therefore highly configurable Can be hard to instantiate, configure and bring up Constrained Random is dumb Many useless repeated tests, consuming compute resource but not improving coverage Directed vs Constrained Random trade-off 6

7 Verification Academy : UVM Cookbook De Facto Industry Standard UVM User Guide Verification Cookbooks UVM Coverage 27 Online Courses CDC & Formal SystemVerilog TB Automation Planning and Metrics Many more.. Discussion Forums More than 40,000 Members Patterns Library 7

8 ASIC/IC Mean Peak Number of Engineers But We Need to do More CAGR Designers 3.6% CAGR Verifiers 10.4% Design Engineers Verification Engineers Source: Wilson Research Group and Mentor Graphics, 2016 Functional Verification Study 8 H Foster, WRG Functional Verification Study, July 2016

9 Testbench Automation Start earlier, work smarter, finish earlier UVM Complexity VIP Complexity Inefficient Stimulus Testbench Automation Testbench Infrastructure Automation Interface VIP Automation Intelligent Stimulus UVM Framework QVIP Configurator Infact Portable Stimulus Enterprise Verification Platform 9

10 Testbench Generation : UVM-F and Configurator Become Productive in Hours Rather than Weeks UVM Framework Generates Testbench for SoC and Proprietary Interfaces QVIP Configurator Generates Testbench for Standard Interfaces Creating Infrastructure Get Up and Running Productive Verification Productive Verification 10

11 Intelligent Stimulus with InFact Portable Stimulus Earlier Tapeout and/or Higher Quality Graph based stimulus combines strengths of directed and constrained random Supports Portable Stimulus Standard Graph Kits available for QVIPs Directed + Constrained Random Testing Earliest Tapeout Date Intelligent Stimulus Testing More Tests 11

12 Testbench Automation Benefits For New UVM Users Testbench Automation Reduces Ramp-Up Time Testbench Infrastructure Automation Interface VIP Automation Intelligent Stimulus Reduces Project Risk UVM Framework QVIP Configurator Infact Portable Stimulus Enterprise Verification Faster Payback on Investment Platform 12

13 Testbench Automation Benefits For Experienced UVM Users Testbench Automation Reduces Ramp-Up Time Testbench Infrastructure Automation Interface VIP Automation Intelligent Stimulus Maximizes Productivity UVM Framework QVIP Configurator Infact Portable Stimulus Enterprise Verification Best Use of Compute Resource Platform 13

14 Testbench Automation Integrated UVM, VIP and Portable Stimulus Flow Maximum Productivity Best Use of Compute Resources Experienced UVM Customers Faster Ramp- Up New UVM Customers Reduce Project Risk Faster Payback on Investment 14

15 ADR, 15 VF17

16 Questa Verification IP A Complete Library for ASIC and FPGA Designs Questa VIP Library Questa Memory Library AMBA PCIe Ethernet USB MIPI Serial Display Automotive DRAM Flash Mil-Aero ACE AXI4 AXI3 NVMe AHCI RMMI 400G 25/50G 100G 3.1 Pipe 3.1 Serial USB PD I3C UFS Unipro JTAG SmartCard I2C CEC HCDP HDMI 2.1 CAN 5G LPDDR4 LPDDR3 LPDDR2 SDCard 4.2 SDIO 4.1 emmc 5.1 Spacewire 1553b AHB5 AHB APB3 PIE8 MRIOV MPHY 40G 10G 1G SSIC ohci xhci LLI CSI-2 / CSI-3 DSI I3C I2S SPI DisplayPort edp V-by-One JESD204B DDR4 DDR3 DDR2 ONFI 4.0 Toggle UFS PCI AMBA 5 CHI PCIe M MPHY DigRF SPI 4.2 WIDEIO ParallelNOR CHI PCIe 3.0 PCIe M Automotive ehci USB 3.0 MPHY HSI UART DFI HMC Serial NOR Hyperbus PCIe 1.0 Interlaken USB 2.0 CPHY HBM2 Hyperram USB 1.1 DPHY DIMM Hyperflash 16