Mentor Graphics Higher Education Program

Transcription

1 Mentor Graphics Higher Education Program Infrastructures for Education EWME Panel Session 5/30/08 Ian Burgess

2 Design for Globalization 2

3 A Simplified View of the EDA Market Concept to Verified RTL Functional Verification Electronic System Level Design Platform-based Design Digital Mixed Signal Analog Mentor MCMM Place & Route Mixed-Signal Environment Analog In EDA Physical Verification to Component Test Today Design-to-Silicon Platform Comprehensive DFM Solutions Yield Improvement Component to PCB System Printed Circuit Board Design High-Speed Design and Analysis Integrated PCB/FPGA Design 3

4 Potential IP Repository Deliverables Written Specifications Executable Models UML, C(++), TLM RTL Code VHDL, Verilog Testbenches System Verilog, System C, PSL Abstraction & Modeling What How Many Concept Architecture Exploration Micro- Architecture development ESL Design Implementation Constraints Test structures and patterns How RTL Implementation Many of these have different standards, different levels of completeness, depending on the target use Hardware 4

5 Educational Use/Benefit Advanced design projects require challenging, industrial strength examples But industry unwilling to compromise its IP Some exceptions eg. OpenSPARC Public domain examples (Eg. OpenCores) are of varying degrees of quality A central repository from a reputable source would be valuable here For universities it would probably need to be free 5

6 Questions/Issues??? Standards & metrics Which would be applied? Which would be applied first? How would the peer review be conducted? Financing of this initiative? Who would pay, how much, and for what? Would commercial companies risk exposing their flaws? Is there a compelling event to drive IP vendors? 6

7 Open Verification Methodology The first truly open, interoperable, and proven verification methodology based on the SystemVerilog IEEE 1800 language Delivers simulator, VIP, and high level language interoperability across companies and across the ecosystem Open, unified class library and methodology for interoperable VIP Environment configuration Sequential stimulus Built-in automation TLM communication Common messaging 7

8 DO-254 In 2005, the FAA* began enforcing a new standard for HW (FPGA/ASIC)** design This standard is known as DO-254, Design Assurance of Airborne Electronic Hardware DO-254 is based on a similar SW standard (DO-178B) DO-254 today applies to civil aviation but is spreading to military and other segments DO-254 is a concern because it adds significant time, risk and cost to design projects * Also EASA and other worldwide aviation safety agencies 8 Mentor Graphics Higher Education Program, NGS, **Airbus 4/16/07 projects require DO-254 compliance at the PCB level as well

9 DO-254 Business Concerns COST! % increase RISK! Certifiable, quality EFFICIENCY! Profitable, reusable flows Factors affecting DO-254 success (or failure) Understanding of and experience with DO-254 High quality, efficient design methodology Partnering with companies/organizations that can help 9

10 DO-254 Project Concerns Knowing that end product is customer safe Tracking that requirements are implemented & verified Design & verification processes meet compliance objectives Documenting project and process artifacts Keeping project on schedule and within cost XML ASCII RTL 10

11 Standards & metrics? Summary There are standards and open methodologies that can be applied. OVM, ex-vsia How would the peer review be conducted? Financing of this initiative? Would commercial companies risk exposing their flaws? Is there a compelling event to drive IP vendors? There are some compelling initiatives in mission critical markets that could drive this. 11

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