Schematic Integrity Analysis

Transcription

1 Schematic Integrity Analysis D A T A S H E E T Overview Xpedition schematic integrity analysis enables full inspection of all nets on a schematic using pre-defined checks and an extensive intelligent model component library. Schematic analysis saves design teams hundreds of hours of visual inspection and lab debug time by automating checks for each net within a schematic. These checks execute rapidly prior to your schematic freeze milestone, such that layout may commence with highest confidence of first-pass success. Schematic integrity analysis is performed in parallel with schematic capture. It can also be performed on electronic designs after they have been released into the market to improve the quality of the design, to increase yield and to decrease product returns. MAJOR COMPONENT SELECTION Initial BOM SCHEMATIC Final BOM Design PEER REVIEW LAYOUT Caption: Integrate schematic verification seamlessly into your existing design process. Applications Xpedition s schematic analysis technology is applicable to multiple needs within an engineering team s design operations. While primarily created to tackle emerging product developments, this rules-based and CADagnostic technology applies directly to other areas, providing enhanced business value to any client s product development requirements. KEY FEATURES 100+ built-in checks Multi-board interconnect analysis Full inspection of 100% of nets in a schematic Intelligent results postprocessing Extensive intelligent model library included Easy setup and intuitive operation Ability to create custom device models Automated custom FPGA model importation Interoperability with all major schematic capture tools KEY BENEFITS Schematic analysis systematically improves the business performance of electronic design teams, focusing on the earliest possible optimization of design quality, which leads to: Reduced hardware spins for faster time-to-market Reduction in development, testing and warranty costs Faster integration to high yield manufacturing Improved yield and decreased field returns Superior product quality

2 New Product Design Avoid downstream delay and quality problems Schematic designs are far too complex to thoroughly inspect using human-peer-review techniques. The implications of defect escapes at this stage of design are profound, and include excessive consumption of scarce engineering talent to debug problems, lengthy NPI delays, poor production yields, growing boneyards of irreparable products, high in-warranty costs and degradation of customer satisfaction. Schematic integrity analysis is performed in parallel with your design and does not affect the schedule of hardware development. NEW CLEAN EXISTING 3 RD PARTY Schematic analysis saves design teams hundreds of hours of visual inspection and lab debug time by automating > 100+ proprietary checks for each net within the emerging design. These checks execute rapidly and immediately prior to your schematic freeze milestone, such that artwork design may commence with highest confidence of success. Emerging new designs can be modeled and continually analyzed to assure last-minute design changes are fully assessed. Data from multiple board designs can also be integrated to perform system-level validation.

3 Existing Product Design Thoroughly diagnose problematic products Sustaining existing electronic designs can produce a significant burden upon product design teams, particularly when field performance does not match expectations and business intent. PRODUCTION RAMPUP FIELD ERRORS MARGINALITIES DETECTED UPDATE ERROR-FREE FULL PRODUCTION BOM NETLIST Schematic integrity analysis can be performed on electronic designs after they have been released into the market to improve the quality of the electronic design, increase yield, and decrease product returns. Schematic analysis can rapidly assess problematic released products, which are exhibiting less than ideal behavior resulting in impacts that negatively affect: High production yield Low in-warranty failure rate (MTBF) Low no-fault-found rate High install/commissioning success rate The prsence of latent design defects and marginalities in field-released products can produce degradation of operating performance, causing the design team to be distracted to isolate the hidden root cause of problems. It is common for such diagnoses to consume multiple weeks of investigation, much of which is avoidable via screening of the design s integrity. By modeling problematic products, schematic analysis can systemically identify latent defects and marginalities providing design teams with a comprehensive overview of where to look to diagnose any performance-limiting problems, in a fraction of the time and effort normally required.

4 Third-Party Design Screen new designs to meet quality expectations OEMs are increasingly taking advantage of the Original Design & Manufacturing (ODM) model, to accelerate time-tomarket and take advantage of low cost capabilities that ODM providers supply. But how do they maintain their quality reputation when dealing with ODM providers having differing quality systems, design approaches and verification methodologies? MAJOR COMPONENT SELECTION SCHEMATIC PEER REVIEW RELEASE OEM ACCEPT ODM Design The application of schematic integrity modeling as a screen for a new designs acceptance can provide time-to-market sensitive OEMs with a rapid and cost-effective means to assure consistent, reliable design from their ODM and Design Services partners. The systemic reveal of defects and marginalities presents an objective, thorough and measured indicator of the new design s ability to meet performance targets such as: High production yield Low in-warranty failure rate (MTBF) Low no-fault-found rate High install/commissioning success rate The CAD-agnostic capability can work directly with clients ODM partners to establish in-process analysis support, fully compatible with their unique design processes, which ensures optimized first pass design success.

5 Select examples of schematic checks performed by Xpedition schematic integrity analysis Pin voltage parametric verification for maximum, minimum and logic thresholds Bus flip errors (MSB to LSB, TX and RX errors) Full multi-board and backplane interface verification Pin function compatibility tests Symbol mismatch (to datasheet) Driver/receiver technology matching Diode orientation verification Driver/receiver function matching Power/ground/open collector/drain shorts Capacitor decoupling sufficiency checks Capacitor voltage derating (to user derating rules) Redundant resistors (on a net detection) Open collector/drain verification Poor design practice checks (ie: using pull-ups, pull downs when needed...) Power/ground plane connection verification Component power checks Multiple or missing power supplies (on a net) Differential pin verification Unconnected nets or bus detection Off-board nets detection Overloaded pins identification Unconnected mandatory pins identification Nets missing driver Nets missing receiver

6 The complete solution The following services are available to accelerate your time to productivity with Xpedition schematic integrity analysis: Model creation Models for new designs can be created on-demand, ensuring modeling quality, minimizing delay and enabling you to focus on the analysis. Modeling services are also available to create your most commonly used components for your central library. On-demand schematic integrity review Let our experts review your critical-path designs and provide reports and analysis to improve your design. Model library The analysis software comes with access to a multi-million part library that is cloud-based, enabling you to constantly have access to the latest models added. Jump start and product training Programs that quickly accelerate adoption of the technology by creating your most commonly used component models, and custom online/onsite product and process training gets your team set up and running within your own environment, ensuring immediate payback on investment. Support Delivered by a global team of dedicated experts that customers know and trust. Receive access to product releases and technical notes, an online support center and user forums, and expert support from Mentor support engineers. For the latest product information, call us or visit: 2017 Mentor Graphics Corporation, all rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent unauthorized use of this information. All trademarks mentioned in this document are the trademarks of their respective owners. TD w