ID 021C: Virtual Microcontroller & System Modeling A platform for all seasons

Transcription

1 ID 021C: Virtual Microcontroller & System Modeling A platform for all seasons Everett Lumpkin Independent Consultant 13 October 2010 Version: 1.2

2 Everett Lumpkin Experience 20 years tier 1 Automotive Many virtual prototypes for Body, Powertrain, Safety and Power Electronics Passion Microcontroller development and simulation SW tools focus to bake in quality Neutral No product to sell 2

3 Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * ASIC, ASSP & Memory Advanced and proven technologies Solutions for Innovation Analog and Power Devices #1 Market share in low-voltage MOSFET** * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). 3 (Optional)

4 Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * ASIC, ASSP & Memory Advanced and proven technologies Solutions for Innovation Analog and Power Devices #1 Market share in low-voltage MOSFET** * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). 4 (Optional)

5 Embedded SW; Do We Plan to Fail? 24% of projects are canceled due to schedule slip 54% of SW designs are completed behind schedule 33% of devices miss functionality/performance 80% of our effort is to correct errors that are discovered late Source: 5

6 Innovation The Virtual Prototype (VP) What if we could... Develop software without hardware? Support parallel simulation of legacy 'C' code and (UML/Matlab) models? Gain test capability? (Automated test) Gain quality? (Monitor firmware execution) 6

7 Agenda What is a virtual prototype? Characteristics and examples The compelling benefit... and some new ones How do we build it? Not your father's instruction set simulator Is the virtual prototype better than the bench? AND can we afford it? AND who will create it? 7

8 Automotive Body Controller Source: Delphi Power Body Controllers, 8

9 Body Controller Virtual Prototype Source: How to make virtual prototyping better than designing with hardware, 22-Jun-2010, E. Lumpkin and C. Alford, 9

10 Virtual Prototype Key Characteristics Simultaneous verification of HW and SW (co-verification) Loads and Executes same executable image as the physical ECU (no re-compile) Behavior models of CPU, peripherals and ASICs have bench "look and feel" to software programmer Within 1 order of magnitude of speed of the physical ECU May be aggregated with other ECU's sensor and actuator plant models 10

11 Automotive Rollover System 1. Computer-Operating- Properly watchdog reset processor erroneously 2. Accelerometer devicedriver read wrong register 3. Software segment not being initialized to zero caused an OS halt 4. Memory-fail register was not being reset following memory error 5. Math overflow problem caused late deployment of airbag by one second 6. Math overflow problem in timer code 7. Stack overrun 8. Bootstrap switched to PLL clock before PLL was running 9. Programmable timer initialized incorrectly 10.Asymmetrical rounding errors Source: VaST/Synopsys White Paper: "Virtual prototyping benefits in safety-critical automotive systems" C. Alford, October 21,

12 Prototyping Options Source: EDA, ESL, and more ideas from DAC 14-Oct-2009, Synopsys- F. Schirrmeister 12

13 The Compelling Use Case Source: EDA, ESL, and more ideas from DAC 14-Oct-2009, Mentor Graphics S. Matalon 13

14 VP Use Cases Early SW development For SW developers, most compelling use case Co-Verification of Register-Transfer-Level (RTL) models For Verification Engineers, requires both an initial virtual prototype and initial software Architecture Exploration For Architects, feedback architecture changes into current or derivative projects Source: TLM+ Modeling of Embedded HW/SW Systems, Ecker, Esen, Velton, DATE Feb 2010, 14

15 Common Misconception Once physical hardware is available, ALL software development should switch to bench development 15

16 Virtual Prototype Conceptual Puzzle Legacy Embedded Code Test Automation Hardware Drivers GUIs HW Models Plant Models Simulink, UML, Labview Models 16

17 Build on Host No need for these models in target code Test Automation HW Models Plant Models 17

18 Build on Host or Target Simulink, UML, Labview Natively are host compile Can usually be "autocoded" to target Product GUIs can usually be built on either host or target GUIs Simulink, UML, Labview Models 18

19 Build on Target Legacy Embedded Code Hardware Drivers Host compile possible but difficult Target compiler extensions Drivers may have to be bypassed/stubbed Host compile may mask... Data size differences Fixed point math Thread concurrency issues Target compiler issues Hardware requirements (timing, bit order) 19

20 VP Design Tools (Example) Source: "Using the new TLM-2.0 Standard for the Creation of Virtual Platforms for ESL Design" 20-May-2008 CoWare (Dr. Tim Kogel) 20

21 systemc (IEEE Std ) Extends C++ with class libraries for system design and verification Spans Hardware AND Software Used for Architectural exploration, IP hardware blocks, Virtual Platforms ESL: Electronic System Level 21

22 Transaction Level Modeling (TLM) 101 RTL Functional Model Pin accurate, cycle accurate Transaction level - function call write(address,data) RTL Functional Model Simulate every event ,000 X faster simulation 22

23 Use Cases and Simulation Speed Use cases Software Software development development Software Software performance performance Architectural Architectural analysis analysis Hardware Hardware verification verification TLM-2 7 Coding styles Loosely-timed 4 Loosely-timed Approximately-timed Approximately-timed Mechanisms Blocking Blocking interface interface DMI DMI Quantum Quantum Sockets Sockets Generic Generic payload payload `` Detail Non-blocking Timing Accuracy interface Phases Phases Speed Non-blocking interface Wireless SW "Sweet Spot" ASIC/SOC development Automotive SW "Sweet Spot" 23

24 Abstracting the details How to pass SPI/CAN transactions? How to represent A/D voltages? Model VDD/VCC? Pullup/Pulldowns? Data Flash programming? Code Flash reprogramming? What are the essential things to model in a FET driver? Does EVERY memory map register need to be modeled? Source: SAE Design Process Changes Enabling Rapid Development, Winters et al. 24

25 In Addition to Early SW Development Visibility Controllability Availability Repeatability Testability Acceptability Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 25

26 Visibility - Debugging Bench Limited breakpoints Trace buffer size limitations Lengthy bench re-flash Virtual Prototype Unlimited breakpoints Trace buffer only limited by disk space and simulation time Instant program load 26

27 Visibility Internal MCU state Interrupt Lock Duration Monitor the "I" bit in the MCU Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 27

28 Visibility Example: RF Receiver to MCU Signal changes Value Change Dump Internal MCU states (interrupts!) VCD Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 28

29 Visibility Pause/Resume Consider an internal combustion engine rotating 6000 RPM User typically gets one meaningful opportunity to view data structures in an interrupt routine Upon resume: Bench: Several pending interrupts then execute in priority order, but not real-time sequence VP: Synchronous pause and resume of engine controller model Multi-core further accentuates need! Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 29 (Optional)

30 Controllability De-bounce switch after 78us "on" Perl script used to precisely control stimuli Discovered firmware race conditions! Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 30 (Optional)

31 Controllability Fault Injection Induce conditions that normally require custom hardware variants. For a FET driver ASIC: Short to ground Open output Thermal overload "Checkbox" on GUI to induce fault MCU read of ASIC (via SPI) acts as if fault has occurred 31

32 Virtual Bench data/scripts Physical Bench Source: SAE "Adaptation of a Virtual Prototype for Systems and Verification Engineering Development, Chandrashekar et al. 32

33 Repeatability Physical Bench Asynchronous behavior due to lack of equipment coordination Labview, real-time cards, multiple computers, software debuggers, scopes and logic analyzers. Closed loop control may add Matlab tied to realtime driver and capture cards. Virtual Prototype Deterministic behavior Each run can be repeated Labview, Matlab directly connected as software models to virtual prototype. Elaborate tool interconnections: Cables, networks, test panels Leads to bench possessive-ness Each product may require a unique harness Configuration files and APIs Time-shareable licenses Configuration files run all products nightly Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 33 (Optional)

34 Trends Multi-core systems will REQUIRE virtual prototyping Synchronization solution for complex debugging issues Some domains (automotive) will demand VPs to address multi-core Multi-core workstations enable the simulation of BIG systems Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 34

35 Testability Allow testing where physical prototypes may be unsafe or inaccessible Entire system may be large Save money and increase safety via experiments Validate design with multiple grid simulation of virtual prototypes 35 Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford,

36 Testability Extensive Model Warnings Alert user of specification violations Omnipotent FAE watching the Software Development Typically 2-20 warning messages per ASIC/peripheral VP is good complement to existing verification techniques Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 36

37 Example: Internal MCU Warnings WARNING: EEPROM1 data read from address 0xXXXX while in the write state Other real examples: Illegal Memory Access Turn on timer prior to proper initialization Power off UART or SPI while still receiving data Alert to a user manual caution: Switch of timer from interval count to capture mode Must disable timer first to avoid a meta-stability issue. Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 37

38 Availability Which bench do you want to ship to Mexico or India? Which bench is easier to modify? Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 38

39 Time Check 25 minutes or less? Take two questions Our Agenda... What is a virtual prototype? Characteristics and examples The compelling benefit... and some new ones How do we build it? Not your father's instruction set simulator Is the virtual prototype better than the bench? AND can we afford it? AND who will create it? 39 (Optional)

40 Use Case for Post-Silicon Visibility Deep investigations Internal signal and state visibility Unlimited breakpoints and trace history Debugging easier Bypass lengthy bench re-flash Faster edit-test cycle Better SW analysis results in fewer defects Once physical hardware is available, ALL software development should switch to bench development Controllability and Repeatability Deterministic Precise applied stimuli allows study/control of race conditions Hardware variants Config files Induce faults easily and repeatedly Better SW control results in fewer defects 40 (Optional)

41 Use case for post-silicon Availability Embedded development simply requires more setup and care than server/desktop software Power supplies, oscilloscopes, voltage and current meters, debuggers, static and dynamic test panels $$$ Changes to embedded system are easier to deploy in virtual prototype 41 (Optional)

42 Acceptability Non-Technical "It's different Answer: Mimic debuggers, scripting and GUI of real bench "Not as accurate as hardware Accuracy or Ambiguity? Modeling helps clarify the HW specifications "It's not real hardware Pilot test Develop w/o HW Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 42

43 Acceptability Non-Technical Virtual Prototype not tangible Hidden on Developer desktops Until budget (hunting) season... "Models not available" Tough issue Source: How to make virtual prototyping better than designing with hardware 22-Jun-2010, E. Lumpkin and C. Alford, 43

44 Where do I get the Models? Model availability is a Roadblock! 44

45 Renesas MCU models Most popular EDA vendors have, or are willing to develop, the necessary CPU models Renesas has the most extensive library of high speed peripheral models (V850, R32C, SH2A, SH4A families) Unfortunately many of these have customer specific abstractions and business arrangements 45

46 Who will create the Virtual Prototype? Semiconductor Provider Has domain expertise for MCU peripherals Can leverage systemc / ESL methodologies ESL tool provider Typically offers the CPU/ISS portion of the simulation Contract services for a specific design Offers value for infrastructure technology (ESL, tools) Self grown modeling team Integrate the MCU and component models Close coordination with software team and milestones Access to hardware (schematic) Domain knowledge End User Graphical environment, watch for point solutions Difficult to optimize the ROI 46

47 Model Availability The Hard Truth The models you really need are not available! MCU libraries are customer not supplier driven Your plant models must be custom developed Potential Solutions Amortize cost of model development (share!) systemc and TLM 2.0 Automotive: Why do Toyota, Bosch and Delphi all independently develop model libraries? Raise the level of abstraction Hint: TLM+ Modeling of Embedded HW/SW Systems, Ecker, Esen, Velton, DATE Feb

48 Summary VPs have big (SW) value before HW avail. systemc/tlm is aiding the silicon design process Value even when HW is available Visibility, Controllability, Repeatability, Availability, Testability Multi-core will both drive and enable VPs But VPs remain expensive to develop As demand increases there will be more cost sharing 48

49 49 Questions?

50 Innovation The Virtual Prototype (VP) What if we could... Develop software without hardware? Support parallel simulation of legacy 'C' code and (UML/Matlab) models? Gain test capability? (Automated test) Gain quality? (Monitor firmware execution) 50

51 51 Thank You!

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