High Level Synthesis with Catapult 8.0. Richard Langridge European AE Manager 21 st January 2015

Transcription

1 High Level Synthesis with Catapult 8.0 Richard Langridge European AE Manager 21 st January 2015

2 Calypto Overview Background Founded in 2002 SLEC released 2005 & PowerPro 2006 Acquired Mentor s Catapult HLS technology and team in 2011 Operations Headquarters in San Jose with R&D in California, Oregon, NOIDA India Sales and support worldwide, with new support office opened in Korea Technology Patented Deep Sequential Analysis Technology for verification and power optimization Industry leading High-Level Synthesis technology 30 patents granted; 17 pending Customers Over 130 customers worldwide FY14 Results - Record revenue 2

3 Platforms Catapult HL Design & Verification Platform PowerPro RTL Low Power Platform 3

4 Why Teams Want to Adopt HLS Accelerate design time by working at higher level of abstraction New features added in days not weeks Address complexity through abstraction void func (short a[n], for (int i=0; i<n; i++) +) { if (cond) z+=a[i]*b[i]; else Cut verification costs with 1000x speedup vs RTL Faster design simulation in higher level languages Easier functional verification and debug Determine optimal microarchitecture Rapidly explore multiple options for optimal Power Performance Area (PPA) Facilitate collaboration, reuse and creation of derivatives Technology and architectural neutral design descriptions are easily shared, modified and retargeted HLS becoming an IP enabler RTL 4

5 Catapult Delivers QoR and Crushes RTL Design Time Catapult results on customer designs 5

6 High-Level Synthesis : Evolution 6

7 Early Generations of HLS 1 2 Circa 1997 Synopsys Behavioral Complier Monet Circa 2004 Mentor Catapult C Forte Circa 2009 Calypto Catapult Cadence C2S Forte Generation 1 (1997) Incremental raising of abstraction Limited value Generation 2 (2004) Move to standardized high level languages Raised abstraction level Big gain in top down optimization algorithms Circa 2009: Control logic improvements 7

8 3 rd Generation HLS Introducing Catapult 8 1 Circa 1997 Synopsys Behavioral Complier Monet Control and predictability required to achieve design closure Configurable design hierarchy with 10x capacity 2 Circa 2004 Mentor Catapult C Forte Circa 2009 Calypto Catapult Cadence C2S Forte Integration with corporate and standard RTL methodologies Creates verification-optimized RTL Native unified SystemC and C++ support Teams can choose, companies use both 3 Calypto 2014 Catapult 8 New Catware IP design libraries 8

9 Catapult 8 Customer Reception The Third Generation High-Level Synthesis and Verification Platform Enabling Widespread Adoption of HLS Catapult 8 allows rapidly evolving C++ algorithms to be explored and optimized to meet our area, power and performance goals. Michael Giovannini, Hardware project leader in Front-End team of Unified Platform Division for STMicroelectronics We write either C++ or SystemC, depending on the design and verification needs of each project, and then use Catapult s configurable hierarchy technology, which makes it possible to synthesize much bigger designs. Emmanuel Liégeon, Head of ASIC/FPGA Design Group at Thales Alenia Space France 9

10 High-level Synthesis : Catapult 8 10

11 What is High-level Synthesis? Two core capabilities define HLS 1. Mapping from abstract transactions to pin-accurate protocols A X I Control i/f A X I 2. Optimizing C/SystemC for performance/area/power in target technology TP = 1 LT < MHz Control i/f i o = f(i,s) o 11

12 Catapult HLS Design at a Higher Level Introduced in s of tape outs Automatic generation of high quality RTL from high level descriptions ANSI C/C++ and SystemC support Designs are correct-by-construction Manual errors are avoided Time-consuming iterations are eliminated Focus on function, not implementation Fewer lines of code Easier to understand Easier to modify Easier to maintain Easy migration to new technology Bridges the gap between specification & design void func (short a[n], for (int i=0; i<n; i++) { if (cond) z+=a[i]*b[i]; else RTL 12

13 Catapult 8.0 : Native Dual-language Support User choice of C++ or SystemC Catapult has dual-language architecture Projects may use either based on requirements C/C++ provides intuitive algorithm implementation flow Fewer lines of code Untimed description Streamlined flow Robust SystemC support Support OSCI synthesis subset Calypto leads Accelera working group Used for designs with complex timing dependent control and interface protocols 13

14 Synthesizing to Hardware Flow is the same for FPGA & ASIC technologies Same C++/SystemC source code for synthesis irrespective of target technology Technology libraries for FPGA base operators are provided in the Catapult installation Additional libraries for hard macros/dsps & memories Catapult Library Builder provided to characterize ASIC libraries 14

15 Supported FPGA Families (Catapult 8.0) Altera Arria GX, II GX, V Cyclone, II, III, III LS, IV E, IV GX, V Stratix, GX, II, II GX, III, IV, V Excalibur ARM Apex 20K, 20KC, 20KE, II Xilinx Artix-7 Kintex-7 Spartan 2, 2E, 3, 3A, 3ADSP, 3E, 6 Virtex, -E, -II, -II Pro, 4, 5, 6, 7 New libraries added to meet Customer requests 15

16 User Constrained Technology Based Scheduling User provides constraints to scheduler in GUI or as TCL script Scheduler uses technology information to allocate operations to clock cycles Source is independent of target technology timing characteristics Same source code gives different schedule based on constraints / technology Scheduler facilitates technology migration by re-scheduling to different target library Migrate FPGA fabric or family Migration to SOC ASIC: Sample 200MHz FPGA: Xilinx 200MHz 16

17 RTL Extraction/Generation RTL Generation creates : Data & control path/state machine RTL Bill of materials reports Estimation of area & timing critical paths Scripts for running backend synthesis/p&r SCVerify testbench & execution scripts ,

18 Catapult 8 : Verification 18

19 Catapult 8 Speeds Verification Closure Catapult 8 re-architected for Verification Closure Developed in partnership with leading Catapult customers Engineered for a drop-in fit into existing verification flows Considers verification coverage during synthesis Extracts and passes design knowledge to verification tools and users New capabilities to assist in closing verification Synthesizes assertions and cover points Identifies and guarantees key equivalent points Easily cross-probe between RTL and C++/SystemC Integration with formal tools to identify unreachable states 19

20 RTL Block Level Testing with SCVerify Catapult provides SCVerify, automated C-RTL co-simulation Generated RTL Optimized for verification Embedded Assertions Preserved probe points Generated Test Infrastructure Leverages original C++/SystemC testbench Verification of generated RTL vs original source Checks assertions, probes and IO Push-button Co-Simulation Supports VCS, Incisive, Questa Original C++/SystemC Golden results Original Testbench Comparator Driver Generated RTL Monitor DUT results 20 Easy testing of RTL before handoff

21 SLEC-HLS High Level Formal Verification C-to-RTL formal verification Sequential Logic Equivalence Checker Handles timing differences in internal computation and at interfaces Total verification confidence Identifies design inconsistencies No need for lengthy simulation runs Unlocks the full potential of HLS void func (short a[n], for (int i=0; i<n; i++) { if (cond) z+=a[i]*b[i]; else SLEC equivalence proof or counter example RTL 21

22 Catapult 8 : Implementation 22

23 Output Generated by FPGA Flow HDL outputs VHDL and/or Verilog Synthesizable RTL concat RTL containing whole design in a single file Synthesis scripts for backend RTL synthesis Precision, SynplifyPro, Xilinx XST Easy synthesis of generated RTL Customer free to integrate RTL into upper levels of system as needed Manual integration 23

24 Migration Catapult allows source code to be re-targeted to alternative technology Scheduler is aware of target technology characteristics Many design teams using : FPGA targets for prototyping, then ASIC for production FPGA for early access to algorithms in hardware, ASIC implementation lags due to lead time IP blocks are independent of implementation target Production quantities may necessitate migration from FPGA to ASIC How to reduce power once in ASIC? 24

25 Catapult LP Synthesizes Power Optimized RTL Available to support ASIC/SOC migration PowerPro technology under the hood Leading RTL Power Optimization Technology Built-in power analysis/measurement Closed loop PPA exploration PPA: Power, performance, area Frequency exploration Clock-gating Memory access minimization Automatic clock gating Deep sequential optimizations Maximizes gating efficiency Use Mode Active LowP InActive High-Level Synthesis Power Optimization Simulation Power Analysis Power Use Mode 1.0 mw Active 0.5 mw LowP 0.03 mw InActive Power 0.2 mw 0.1 mw 0.05 mw 25

26 Customer Success : HEVC Decoder Design 26

27 Google Designs VP9 in Half the Time Selected Catapult because Uses C++ gcc test flow Best versioning and merging tools Familiar language Constantly evolving algorithms & specification 50% faster design and verification cycle WebM - VP9 Video decoder Built in under 6 months vs. 1 year for RTL 69k lines of C++/ 14 blocks vs. ~300k lines RTL 0.9mm2 at 28nm, 243MHz G2 (VP9 + HEVC) video decoder Modifications in under 3 months 27

28 WebM : VP9 G2 The G2 VP9 decoder uses a completely new hardware architecture. A majority of its hardware modules are designed in C++ and converted to RTL using Calypto's Catapult C high-level synthesis tool. This higher abstraction level makes design implementation and verification much faster and cleaner than in a traditional RTL design flow. 28

29 Catapult 8 : Summary 29

30 Catapult 8 : Summary Catapult supports creation and implementation of production quality RTL Superior QOR through easy architectural exploration HLS methodology provides abstraction of implementation details and complexity, leading to : Rapid specification Easy technology migration Easier/faster verification Easier maintenance Efficient IP re-use Catapult HLS used today in production FPGA/ASIC projects Usage growing 30

31