Pre- and Post-Si Validation Challenges Intel Annual Symposium VLSI CAD and Validation

Transcription

1 Pre- and Post-Si Validation Challenges Intel Annual Symposium VLSI CAD and Validation Yossi Schenkler IDC GM and Director of Microprocessor Product Dev. June 2008 Page 1

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3 Intel Israel on the map Intel Haifa Intel Israel s main development center: MMG, LAD, MWG, DTS, SSG Intel Yakum Hardware component development center Intel Petach Tikva MWG: Wi-Fi WiMax development center Intel Jerusalem IDPj International Die Preparation - Jerusalem Intel Kiryat Gat Fab28 - Production plant for 45 nanometer technology components, 300 mm 3

4 Key Messages The Validation gap is growing! help! Validation was a Critical Path (CP) in every CPU we designed in the last 15 years and is a CP today Functional Complexity is doubling every 2 years Validation dictates the project scope and TT$ Physical Complexity is becoming a night mare Cost of an escape might be huge The Validation gap is growing We need breakthrough solutions to make better advancement for the benefit of all! Page 4 4

5 Microprocessor Design Scope Typical lead CPU design requires: 500+ person design team: logic and circuit design physical design validation and verification design automation 2-2½ years from start of RTL development to A0 tapeout months from A0 tapeout to production quality (may take longer for workstation/server products) One design cycle = 2 process generations Page 5 5

6 Functional Complexity: 2x/2years As Each new process generation doubles the number of transistors and Current verification methods do not scale effort more than doubles E.g. RTL FC Simulation speed on current lead CPU 0.5 Hz CPU becomes multi core/mt SOC with more integration of platform components and tech s E.g. More complicated FC protocols, deadlocks scenarios, complicated power management scheme, deeper pipelines, virtualization; Large teams, huge computing farms Validation dictates the project scope and TT$ Page 6 6

7 Electrical Validation Challenges Production Test Coverage Focus Traditional Focus Test 1 DPM Random Defects 1k-999K DPM Circuit and Process marginalities 1M DPM Logic Simulation does not cut it Si continues to miscorrelate to models A circuit marginality is the same as a logic bug Circuit Quality Validation adds another dimension to the infinite space of validation Page 7 7

8 Some Directions for Breakthroughs We need dramatic improvement in validation efficiency (it takes too many people, $$ and time): Coverage Validation is done in an open loop (Post Si more behind) No good metrics to know what s not covered and when we are done holes and waste Scalability Find effective ways of raising the abstraction level Can we make emulation effective? Modular, Reuse and higher quality Designs Effective methods for change verification Automation: Test generation, debug aids Electrical Similar (but not the same) coverage challenges Need Statistical methods to reduce waste Page 8 8

9 Summary The Validation gap is growing! Validation inhibits faster technological advancement Cost of an escape might be huge We need breakthrough solutions to make better advancement for the benefit of all! Page 9 9

10 Q&A Page 10

11 Back Up Page 11 11

12 Observations Overall Validation is sufficiently effective (we get the job done) Validation is not efficient enough (takes too many people too long) Must find a way to reduce effort while maintaining effectiveness Two components of validation effort Base validation Number of bugs Validation collateral is complex Significant percentage of bugs In recent projects, 40% are in the collateral Collateral readiness/maturity dominates efficiency Page 12 12

13 Major Validation Gaps Late specification convergence Validation and architecture/design are disconnected Validation is almost completely dependent on RTL and Si Little/no synergy between pre-si and post-si validation Poor controllability/observability in post-si No effective methods for change verification (both for pre and for post silicon) Page 13 13

14 Larrabee Architecture for Visual Computing example of design complexity Many IA cores Scalable to TeraFLOPS New cache architecture Throughput architecture New vector instruction set Vector memory operations Conditionals Integer and FP arithmetic New vector processing unit / wide SIMD Page 14 14

15 The Validation Challenge Microprocessor validation continues to be driven by the economics of Moore s Law Each new process generation doubles the number of transistors available to microprocessor architects and designers Some of this increase is consumed by larger structures (caches, TLB, etc.), which have no significant impact to validation The rest goes to increased complexity: Out-of-order, speculative execution machines Deeper pipelines New technologies (Hyper-Threading, 64-bit extensions, virtualization, security, Multi-core designs Power Management Protocols (Core Hopping, Throttling, Increased complexity => increased validation effort and risk High volumes magnify the cost of a validation escape Page 15 15

16 Digital Growth Worldwide 2,000 1,500 Digital Information Created, Captured, Replicated 500 Exabytes TENFOLD GROWTH IN 5 YEARS Personal Computer Sales Units (Millions) Mobile Phone Subscribers (Billions) Forecast Forecast Forecast 200 Global VoIP Subscribers Millions 2 Internet Users Billions Forecast Forecast Page 16 Source: IDC, The Digital Economy Fact Book 16

17 Analog effects modeling System level simulations Electrical validation /Analog inspection (EV/AI) Compatibility validation (CV) Power and thermal validation Stages in the validation process Software: Bios/Driver Emulation Debug Software Validation CPU: Architecture validation (AV) System Validation (SV) Circuit Marginality Validation (CMV) Chipset: Mother board Pre-silicon simulation/ Emulation Platform Design Chipset and graphics System validation (SV) Hardware debug & Platform Qualification Pre-silicon A0 silicon/alpha SW Post-silicon Source: Chip magicians at work Page 17 17

18 Major Validation Differences CYCLE COUNTS PRE-SILICON Slow & expensive POST-SILICON About a billion times faster & cheaper CONTROLLABILITY Much Little HW/SW PLATFORM INTEGRATION An interesting discussion A pre-requisite FORMAL VERIFICATION Promising Not applicable ELECTRICAL VERIFICATION ESCAPE TOLERANCE Difficult simulations Don t like them Major source of bugs Expected to find, The last stop! Page 18 18

19 Post-silicon validation spending is growing Page 19 19

20 The Coverage Problem Non-linear validation space IA32 has > arch. states 2.5 yrs of P4P ran 1011 cycles 8K 3GHz machine-wks = 1019 cycles 1B machines can only check FDIV in 1024 years Then you add Electrical Issues Quantitative Sampling Approaches Pure and Directed Random Functionality proof points Algorithmic stress Analytical Approaches Formal Verification Deep algorithmic analysis No known probably correct methodology especially post silicon No definitive measure to know when your done No definitive measure to guide investment We don t prove correctness We judge risk & viability from the preponderance of evidence Page 20 20

21 Security Security is both an opportunity and a challenge Validating security mechanisms requires a different way of thinking Security needs to be addressed at multiple levels Page 21 21

22 Evolution of Intel s Micro- Architecture Delivering Consistent Leaps Ahead Intel Smart Cache Dynamic Power Coordination Advanced Thermal Manager Merom Enhanced SpeedStep Technology 400 MHz Power Optimized System Bus Banias 2MB Power Efficient L2 Cache Dothan Yonah Integer Performance/Watt* Merom 2004 Banias Dothan Yonah >2X & >3X Pure Performance >3x 2003 Page Q1 06 *SpecIntRate. Source Intel 2H 06 22

23 Miki s foils Page 23

24 Pre-silicon Validation crisis era Functional complexity of each generation doubles every 2-3 years. Validation has been in the critical path for the last 2-3 generations Current verification methods do not scale Do not match growth in complexity of designs Validation consumes significant portion of the project resources Large teams, huge computing farms As Validation productivity doesn t scale, Validation effort more than double which each generation Validation dictates the project scope and tape-out Validation is the major bottleneck for completion of designs Validation today is a limiting factor in introduction of new Architecture and UArchitecture features Our Challenge: Dramatic improvement in productivity Maintain level of quality with smaller teams and shorter schedule Page 24 24

25 Fundamental parameters of verification Tighter time-to-market requirements Larger designs, shorter schedule, lower costs Infinite testing space Simulation covers only a negligible fraction No precise quality and completion metrics Subjective interpretations and heuristics Huge cost for mistakes Page 25 25

26 Non fundamental parameters Validation consists of low level manual work Interpretation of informal (English) specs Development of low level modules Testbenches with accurate modeling Checkers that verify all behaviors Stimuli capabilities the trigger all functions Development of coverage monitors Debug of failures Design is very low level too many details to deal with Page 26 26

27 Key directions Improve validation productivity Perform similar activities faster Earlier bugs finding Early verification, assertions, Spec FV Introduce new technologies to improve quality Emulation, Assertion FV, Mixed analog/digital Effectively cope with configurations and integrations Number of cores, memory controller Page 27 27

28 Key directions Reduce scope of problem Raise level of abstraction Less details, less bugs, less work Spec level validation Bridge the validation gap between the abstraction levels Raise effectiveness of existing methods Significantly increase automation - Test generation, Debug, Coverage Improve utilization of Formal Verification techniques Better use of emulation Usability of coverage for quality measurement Modularity and reuse Project are moving to System/Platform level integration. Methodology and technology for validation IP collaterals reuse Page 28 28