DISCOVER: Design and Simulation of Complex Low Volume Electronics Production

Transcription

1 DISCOVER: Design and Simulation of Complex Low Volume Electronics Production by Dr Andrew A. West DISCOVER GROUP Paul Conway Chris Hinde Diana Segura David Whalley Tony Wilson Loughborough University Loughborough University - Wednesday 21 September 2006

2 DISCOVER Industrial Context The Challenge Aims and Objectives Methodology Deliverables Current Status Questions? 2

3 3 Industrial Context

4 The Challenge What are the reasons for poor first time yield and long term reliability in complex products? Defects generated during the manufacturing flow, Lack of formalised process knowledge, Lack of knowledge concerning the implications of design features on manufacturing performance, Lack of in process performance monitoring and analysis, The impact of new materials and components e.g. (lead free legislation) Lack of knowledge of the impact of the adoption of new technology (e.g. novel agile approaches to reflow oven technology). 4

5 Aims and Objectives Understand the causes of poor manufacturing performance within the low volume electronics manufacturing domain Develop a suite of software tools that can enable models of complete design, manufacturing and business processes (throughout the entire product lifecycle) in terms of their propensity to create defects that could cause product failure, Reduce a products manufactured cost and time to market and enhance its quality, Enable simulation of new designs and the impact of design, manufacturing and business strategies, Enable the optimisation of designs and manufacturing processes for yield, quality and reliability. 5

6 Methodology Activities Analysis of the causes of poor yield and service failure - design and / or manufacturing processes, Mapping generic electronics design procedures into welldefined process steps, Modelling the defect causing propensity of each process, Developing knowledge-based software tools that capture both the design and manufacturing processes and defect causing propensity, Determining new product and new technology introduction scenarios to enable the software tools to be evaluated, Evaluation of the software tools from functional, human factors and business perspectives. 6

7 Methodology: Work Packages WP1: Analysis of cause of poor yield and service performance WP2: Generic Design and Manufacturing Process Steps WP3: Design and Manufacturing Defect Process Mapping WP4: Development of Component-Based (CB) simulation tool WP5: Evaluation of CB simulation tool for design and process optimisation WP6: Dissemination and Exploitation 7

8 Deliverables A methodology for capturing and describing the linkages between design and manufacturing process variables and yield, product reliability, cost and quality A component based framework for constructing static (i.e. visual) and dynamic (i.e. enactable via computer-based simulation) process representations A lifecycle model of a design and production facility capable of simulating process yield and guiding product or process design 8

9 Current Status ID Task Name Duration Start 1 WP1 Test and service Data Capture 326 days? Mon 16/01/06 10 WP2 Assembly Process Flow Map 194 days? Mon 16/01/06 11 Milestone2 - Initial Processes Mapped 0 days Fri 02/06/06 12 Milestone3 - Completion of process mapping 0 days Fri 13/10/06 13 Scope detail level required 164 days? Mon 16/01/06 14 Iniital process maps for all partners 83 days Wed 08/02/0 15 Capture partner process flows and process variations 160 days Mon 06/02/06 16 Capture partner design rules 33 days Mon 15/05/06 17 Encoding of DFM rules - Goodrich 18 days Mon 15/05/06 18 Encoding of DFM rules - Smiths 18 days Mon 15/05/06 19 Encoding of DFM rules - STI 11 days Mon 15/05/06 20 Iterative cycle of refining rules with expert support 12 days Tue 30/05/06 21 Creation of Rule-Based System 10 days Thu 15/06/06 22 Develop generic process flow with options (including rework) 140 days Sat 01/04/0 23 WP3 Individual Process step defect modelling 291 days Mon 21/08/06 24 Milestone5 - Define all processes 50% modelled 0 days Fri 02/03/07 9

10 Assembly Process Flow - Vision End-User Requirements Model validation check based on feedback EM : refers to Enterprise Modelling Approaches such as GERAM, PERA, GRAI, CIMOSA (adopted in this project) BPM : refers to Business Process Modelling Tools such as ProcessWise, SysytemArchite cture, IThink (adopted in this project) Processes (Current Practice) TO-BE Processes (After Implementing CBT) 10 Circuit Designers Manufacturing Engineers Methods: Study of available documentation, visits, questionnaire, structured interview (based on adopted EM approach) Knowledge Elicitation Phase Knowledge of Manufacturing Electronics Visualising Processes using BPM Tools Formalising Business Processes using EM approaches Information Time Cost End-User Circuit Designers Manufacturing engineers BP Models Modelling & Visualisation Phase Maintenance Testing & Installation Building Simulation and Demonstration of Current Practice Comparison Simulation and Demonstration of Systems after Analysis What If Analyses & Assessment Phase

11 Assembly Process Flow Constructs CIMOSA Domain Real World Processes Context Diagram Interaction Diagram Structure Diagram Activity Diagram Domain Processes Business Processes Abstraction Mechanisms Enterprise Activities Non-CIMOSA Domain Activity Events Information Human Resource Physical Resource Finance External Links Flow of Res./Mat. Flow of Process Alternative Flow 11

12 Assembly Process Flow Context Diagram Context Diagram Generic Level View DISCOVER Product Development Production Product Realization DP1: Product Design DP2: Process Development DP3: Product Qualification DP4: Vertically Integrated Design to Manf DP6: Commercialised Design to Manf DP7: Manufacturing Set-up DP8: Manufacturing Operations DP9: Test DP5: Parallel Design to Manufacture CIMOSA Domain Non-CIMOSA Domain Activity Event(s) Information Human Resource Physical Resource Finance External Links Flow of Res./Mat. Flow of Process Alternative Flow Complex LOw Volume Electronic Systems Process Modelling Title: Number: Overall Context Diagram XXXX Diag Design by: Diana Segura & Tony Wilson Checked by: Last update: 19/09/2006 Wolfson School of Mechanical & Manufacturing Engineering 2 12

13 Assembly Process Flow Activity Diagram BPx.x.x Sub-process - Generic Process Set-up BPx.x.x - Pxxx Process Set Up Required Build Schedule EAX.X.X BPx.x.x Product Set-Up Data i.e. EA Assembly Drawings EA ECNs EA Build Standard EA SMT Kiting List EA SMT Layout Drawings EA SMT Process Chemistry List EA SMT Process Chemistry List EA PTH Kiting List EA PTH Layout Drawings EA PTH Process Tooling List EA Mechanical Components Kiting List EA Mechanical Component Layout Draw's EA Mechanical Assembly Tooling List EA Wave Solder Process Chemistry List EA Wave Solder Process Tooling List EA NSP instructions & Drawings EA NSP Chemistry List EA NSP Tooling List EA Test Specs. EA Bom Verify Process Parameter Input Data File Correlates With Prod ID Product Set-Up Data Input Process Set-up Parameters * Validation Vehicle e.g. Set-up Board, Sticky Board, Profile Board etc * Production Released Product Tooling * Process Chemicals * SMT, PHT, Mech Comp Kits etc. EAX.X.X * Verification Equipment e.g. Paste Height/ Volume Measuring Kit, Magnifiers, SMT Overlays, Comp locator Software, API, AOI, AXI, FPT, ICT, FCT, etc Produce First-off EAX.X.X EAX.X.X Verify (Inspect or Test) First-off Define Set-up Parameter Adjustments Fail Validated First-Off (Pass Inspection or Test Stage) Pass EAX.X.X EAX.X.X Define Defect Opportunity Cause EAX.X.X Validate Process Set-up As Production Ready Yes Can Defect Opportunity Be Negated During Set-up No BPx.x.x - Pxxx Process Set Up With Defect Opportunity Concessions Generic Manufacturing Set up BPx.x.x - Pxxx Process Set Up Validated 13

14 Assembly Process Flow Activity Diagram DP7 (Manf Set-up) / BP (Subprocess - PTH Kitting Setup) Process Set-up Completed No Do Component Leads Require Tinning DP8 (Manf Ops) / K300 (PTH & Mech Comp Kitting) Manf Op Completed Yes Company Standard Requirements For Soft Soldered Electrical Connections Liquid Flux & Dip Tank Dip Flux Component Leads EAX.X.X EAX.X.X.X Tin/Lead & Solder Bath Liquid Flux & Dip Tank EAX.X.X.X Dissolve Gold Plating in Sacrificial Tin/Lead Bath EAX.X.X.X Dip Flux Component Leads PTH Operator Lead Tinning Tin/Lead & Solder Bath EAX.X.X.X Dip Coat Leads in Uncontaminated Tin/Lead Bath 14

15 Assembly Process Flow - Cause-Effect Diagram 15 BP1.2 Product Architecture DP1: Product Design BP1.1 DFx Rules BP3.2 Process Tooling Pre-qualification DP2: Process Dedvelopment BP2.2 Reliability Pre-qualification Product Development BP3.1 Process Chemistry Pre-qualification DP3: Product Qualification BP2.1 Functionality Pre-qualification BP7.1 Documentation DP7: Manufacturing Set-up BP7.2 PCB Prep BP7.3 Component Loading BP7.4 SMT Processes BP7.5 PTH & Pre-wave BP7.6 Wave & Post Wave BP7.7 PCA Test & Rework BP7.8 PCA Completion BP7.9 Module Assy & Test BP7.10 Unit Assy & Test Generic Ishikawa.igx BP4.1 Internal NPI (New Product Introduction) DP4: Vertically Integrated (i.e. Internal Production Model) BP5.1 Internal NPI With External Sub-assembly Product Realisation DP5: Parallel (i.e. Production Model Includes Internal & Outsourcing) BP6.2 BP6.1 New Contract Eternal NPI Introduction DP6: Comercialised (i.e. Part Of Or All Of The DTM Sequence Outsourced) BP8.1 Comp & PCB Prep BP8.2 Side 1 SMT BP8.3 Side 2 SMT BP8.4 PTH & Pre-wave Mech Comps BP8.5 Wave Soldering & Post-wave Mech Component Hand Soldering BP8.6 PCA Test BP8.7 PCA Completion BP8.9 Unit Assembly & Test DP8: Manufacturing Operations BP9.1 INTERNAL FAILURES: Inherent Defects In A Product's Mechanical Integrity That Are Detected During Printed Circuit Assembly & itest (i.e.yield) Inherent Defects In A Product's Mechanical Integrity That Are Detected During Environmental Stress Screening (i.e. Captured Infant Mortalities) Effects: BP9.1 Internal Failures BP9.2 External Failures BP9.2 EXTERNAL FAILURES: Inherent Defects In A Product's Mechanical Integrity That Cause Sporadic Early Life Field Failures (i.e Escaping Infant Mortalitiity Failures) Inherent Deficiencies In A Product's Mechanical Integrity That Cause Systematic Premature Inservice Stress Related Wear-out (i.e. Fatigue Resistance Failures

16 16 Partners Design Rules Vision

17 Partners Design Rules - Knowledge Elicitation Encoding DFM rules into IF THEN rules (e.g. IF Thinner circuits are required THEN Use dedicated fixtures AND Vacuum clamping) Validation of the rules with experts Link rules to defect opportunity i.e. effect on reliability Inclusion of defect costs Inclusion of rule metrics Generation of common rules clustering Unification of Vocabulary across industrial partners Comparison with high volume electronics Comparison with International Standards Trial of commercial rule-based software 17

18 Partners Design Rules - Example ATTRIBUTES / CHECKS RULES AND BEST PRACTICE >> Solder? Finish >> Solder? Finish The outer layers should have a FINISH NOTE, as determined by the Process Department. IF THE MINIMUM THICKNESS OF TIN-LEAD BEFORE REFUSING/REFLOWING IS BE 0,15um. THEN THE BOARD IS TO HAVE A 60/40 REFUSED/REFLOWED TIN- LEAD SOLDER FINISH IF OVER 0,06um TO 0,12um THICK IMMERSION GOLD OR OVER 3um TO 9um THICK ELECTROLESS NICKEL. THEN THE BOARD TO BE HOT AIR SOLDER LEVELLED USING 60/40 TIN-LEAD FINISH IF OVER ELECTROLESS NICKEL 3um TO 9um THICK. THEN GOLD IMMERSION PLATE 0,06 TO 0,12um THICK, FINISH IF THEN THE BOARD TO BE HOT AIR SOLDER LEVELLED USING 60/40 TIN-LEAD FINISH 18

19 Partners Design Rules Metrics and Defects METRICS DEFECTS AND REQUIREMENTS visual inspection THIS THICKNESS IS CRITICAL TO FACILITATE SUBSEQUENT REFLOW TECHNIQUES ON ASSEMBLY. NOT preferred for future designs (WHY?) visual inspection this was introduced to overcome soldering issues with Circast gold on Trent 500. NOT preferred for future designs (WHY?) visual inspection this is the preferred method for PCB s with vias that may not solder fill and for reflow soldered Surface Mount Cards visual inspection this is the current standard solder finish for discrete plated through hole PCB 19

20 DISCOVER Industrial Context The Challenge Aims and Objectives Methodology Deliverables Current Status Questions? 20