Application of Spacer Filled Silicone Die Adhesive in Stacked Chip Technology

Transcription

1 Application of Spacer Filled Silicone Die Adhesive in Stacked Chip Technology Xuan Li, R. Wayne Johnson 200 Broun Hall, Auburn University, Auburn, Alabama Thomas E. Noll, Michael J. Watson Dow Corning Corporation, P.O. Box 994, Midland, Michigan Abstract The increasing demand for feature content of portable electronic products drives requirements for smaller volume and lower cost device packaging. This has, in turn, led to the packaging industry s interest in stacked chip technology, especially for memory applications. The growth of stacked chip package technology drove development of specific die adhesives that combine low cost with controlled thickness, critical for wirebonding multiple layers. Silicone, as a die adhesive material, shows many beneficial properties such as low moisture absorption and thermal stability especially for lead free needs. In stacked chip packages with conventional wire bonding, a spacer is needed to provide controlled bond line thickness, to meet wire bonding and molding tolerances for thin packages. While preform sheets can be used to maintain bond line uniformity, they are not always as easy to use in high volume manufacturing as liquid adhesives. This paper discusses testing of a two chip simulated memory stack package using a liquid die adhesive material based on a flexible silicone filled with spacer beads. Attributes of the spacer filled silicone adhesive are discussed, effects of process parameters on bond line thickness are demonstrated, and resistance to humidity and thermal reliability are evaluated. Wire bonding results show this low modulus material can be reliably assembled in stack applications. Key words: 3D stacked packaging, adhesive, die attach, reliability, silicone, spacer Background The ubiquitous trend for ever smaller portable electronic devices (PDA s, MP3 players, Cell phones, etc.) and the needs for higher functionality, best exemplified by video transmissions using cell phones, has driven the need for increased memory density within a smaller area [1][2]. Portable devices are getting smaller in area while at the same time need to maintain convenient thin profiles. The best method for obtaining increased density in the same size footprint is to stack chip devices especially memory or memory and logic. With the advent of 3D die stacking, there is also a need to moderate the height of devices using three, four or more die. Thinning the die is one way to reduce the overall height of the package; however doing so introduces new requirements of die attach adhesives. In stacking technology, two major interconnect methods are used, flip chip and wire bonding [1]. Compared to flip chip, wire bonding is a mature technology with low cost and high flexibility. But difference in die size limits wire bonding application in stacked die packaging [6]. Difference of size and standoff between neighbor die must be large enough for wire bonding on top of the bottom die. One solution is using silicon die as spacer [5], but disadvantages are high cost, complexity in assembly and strict height limitation on die and die attach bondline. Another solution is using adhesive film as a spacer [5], but some manufactures are not equipped with additional equipment for high temperature die bonding. This paper discusses the development of new liquid die attach adhesives that allowed for control bondline thickness in thin die multi chip stacked packages. Test Vehicle We chose a two chip stack design with different size die to evaluate the performance of these new silicone die attach materials, and named it the

2 Auburn University Reliability Test Vehicle (AURTV, Figure 3). The substrate is a four layer PCB made with BT material, a common approach to meet low cost requirements without sacrificing reliability [2][6]. It was designed to simulate a typical 3D multi-chip package (see Figure 1), but internal ground layers are non-functional (checkerboard metal) and are included to simulate an actual product. We used an industry standard photo solder resist (TAIYO America, Inc. PSR-4000GG) to cover gold circuitry in the die area and also on the reverse BGA side. The two die are daisy chained (as shown in Figure 2) for electrical continuity during humidity and thermal cycling testing and bonded with a new spacer filled silicone die attach adhesive. The die are Delphi model PB400 and PB250 daisy chained test chips, thinned to 300 microns and wirebonded with 25 micron gold wire; the package is overmolded with a commonly used Cookson Plaskon SMT-B-1LV Epoxy Molding Compound. Solder balls are mounted for external terminals to the motherboard. Figure 1: Typical 3D Multi-Chip Package using two different size die stacked on a BT substrate with flat wirebond loops. Figure 2: An example of daisy chain patterns are shown above for die and BT substrate Figure 3: Dimension for the AURTV (in mm). Table 1: Test vehicle information (in mm) Package size 23 by 23 by 1.55 (Z-dimension excluding solder ball) Die size Bottom: by by 0.3 Top: 6.35 by 6.35 by 0.3 Substrate 0.43 thickness, BT 4 layer Gold Wire diameter The use of some type of a low modulus adhesive can be paramount to the reliability of the package [8]. Spacer filled silicone die attach adhesives are low in modulus which allows for stress relief caused by different coefficient of thermal expansion of materials used in our test vehicle. The spacers within this product control the bondline thickness of die attach adhesive during die placement, eliminating the need for a spacer die and additional equipment used for die attach with film adhesives. Liquid Silicone die attach adhesive Dow Corning has developed new die attach adhesives available with spacers to control the adhesive thickness and improved technology to control unwanted deposition of silicone on bond pads and other areas of the package. This material maintains the many inherent advantages of silicon based packaging materials [7][11]: 1) Microelectronics grade no outgassing or contamination, low ionics content and low alpha emitter content. 2) Good adhesion to passivated die and interposers: TAB tape, BT laminate, ceramics etc. 3) Low moisture absorption and high diffusion rate of moisture to prevent popcorning. 4) Stable electrical performance over a broad range of temperatures and frequencies critical as portable devices move into higher frequencies (>3GHz). 5) Thermal stability- performs well especially as no lead strategies lead to higher assembly temperatures. 6) Green materials silicones are inherently environmentally friendly as well as lead free enabling because of their tolerance for higher solder reflow temperature. Thermal stability of these materials is such that degradation in air does not begin until temperatures in excess of 300 C (Figure 4). This enables silicones to be used for die attach for short duration temperature excursions to lead free solder reflow temperatures of 260 C to 280 C. This is not

3 always true of organic based adhesives. It has similarly been demonstrated that silicones are superior in their moisture permeability properties and that silicones do not contribute to popcorning of die as can be true of epoxy materials [9]. While the continuing need is stressed for lower Coefficient of Thermal Expansion (CTE) materials, the lower modulus and greater elasticity of silicone materials results in a lower transfer of stress between device components due to the mismatch in CTE. It is true that standard liquid silicones can cause some problems with silicone contamination through volatilization followed by condensation. However, microelectronic grade liquid silicones are specially formulated to have dramatically reduced levels of low molecular weight silicone species that can deposit in unwanted areas. In addition to controlling the deposition of silicone by volatilization, it is also important to control the migration of silicone along surfaces into unwanted areas. Recent advances in polymer additive technology can be used to control the migration of silicone species along surfaces upon which it is applied. The inclusion of spacers into a liquid die attach adhesive is a key strategy in the control of the adhesive thickness during die attach. After the application of the die attach adhesive to the desired surface (we have used dispensing but printing is also and option), an appropriate amount of pressure is applied to the die to be attached. The adhesive then flows under the die. The spacers limit the distance that the die can be compressed and provide good control of adhesive thickness and die tilt. Table 2 summarizes some of the critical data for the family of die attach adhesives we are testing. The adhesive then flows out from under the die. The spacers limit the distance that the die can be compressed and provide good control of adhesive thickness and die tilt. Table 2 Typical properties of one spacer-filled die attach adhesive Figure 4 shows weight loss versus temperature in air of silicone die attach heated at 10 C/minute. Weight Retention, wt% Ramp Rate : 10 deg C/min. Gas : Air, 50ml/min Temperature, deg C Figure 4 TGA thermal characteristics of silicone die attach adhesive. Process Development A combination of high volume equipment available at Auburn University s CAVE Lab and a contract assembler (for wirebonding and all fabrication steps after wirebonding) were used to fabricate parts, which were then tested at Auburn University (see Figure 5). Wafer Grinding Plasma Clean Wire Bonding Testing Substrate Prebaking Wafer Sawing Step Cure Plasma Clean Singulation Bottom Die Attach Top Die Attach Molding and Curing Solder Ball Attach Figure 5: AURTV Assembly Flowchart Specifically, die attach was done by dispensing patterns on the substrate, then attaching the die with appropriate pressure and hold time. Parameters for dispensing and placement are showed in Table 3, and dispensing pattern shapes are shown in Figure 6. While determining appropriate process parameters for die attach for our test vehicle, it was found that die placement pressure is a key factor controlling the adhesive bondline thickness. Also, filler and viscosity adjustments can be made for specific applications using a variety of equipment to

4 Figure 6 Asterisk and cross line dispensing patterns obtain desired bondline thickness. Figures 7 and 8 show the effect of formulation and various process parameters on the adhesive bondline thickness. Spacer loading levels reported in Figure 7 vary from low (A) to high (D). Table 3 Dispensing and Placement Parameters Die Gauge size Dispensing pattern Placement pressure Placement hold time Top 18 Cross line 2 Newton 2 sec Bottom 18 Asterisk 8 Newton 2 sec Variations in ultimate bondline thickness occur in Figure 7 because of viscosity effects related to the loading level of the spacer particles. Figure 8 shows that placement holding time is not significant, this is fortuitous because of the push for faster automated die attach processes. The results, for level A bead loading, show that once critical level of pressure is reached holding time has no significant effect. For the die attach chosen for the reliability test vehicle, the fairly low viscosity allows die attach pressures of 3 N (~300 gmf) to be used for consistent results. The silicone is loaded with spherical spacer particles and other fillers to meet targets for cost, viscosity, and processibility. Figure 9 shows the spacer particles and Figure 10 shows two large spacers in a typical cross-section of cured silicone die attach between two silicon die Bondline (micron) Placement Pressure (grams) Figure 9: Spacer particles A% loading B% loading C% loading D% loading Figure 7: Effect of placement pressure and spacer loading level on bondline thickness Figure 8: Effect of placement pressure and hold time on bondline thickness Figure 10: Spacers in silicone die attach adhesive matrix This spacer filled silicone die attach adhesive showed good adhesion to both silicon die and substrate. For eleven die with mm by 10.16mm by 0.3mm space dimension, the average shear strength was Kg with standard deviation of 2.59 Kg with thin film cohesive failure.

5 Because of concerns about voids in die attach materials we developed proprietary processes that significantly minimized or eliminated sources of moisture and air in the materials. Also, due to moisture pick up and volatiles from circuit board materials [10], voids can form in the die attach adhesive during cure. Therefore, a step cure at 75 C for thirty minutes followed by 150 C for another thirty minutes was used to help slowly drive off unwanted volatile components. After step cure, the parts were sent to our contract assembler (OSE-USA, formerly IPAC, in San Jose, CA.) for the remainder of the fabrication processes. Wire bonding provides interconnects from die to substrate. Deposition in unwanted areas through volatilization during cure or migration along surfaces used to be drawbacks of silicone material [7]. This spacer filled die adhesive has low outgassing and migration, so no related problems were seen during wire bonding. The wire pull data is shown in table 4, and a photo of a wire-bonded part is shown in figure 11. Table 4: Wire pull data Sample size: Top Die Bottom Die 12 parts per unit Unit 1 Unit 2 Unit 1 Unit 2 Min Max Avg Std Dev Provided by OSE USA Two plasma treatments were performed in the assembly process. The first treatment was done to ensure bondability for wire bonding, and the second was done to ensure good adhesion for molding compound. A W Ar plasma clean for 10 min. +/- 2 min was done for both steps. After the parts were molded, wire sweep measurements were performed. Figure 12 shows a typical X-ray micrograph (Phoenix Xray Machine) of one of the parts. Measurements indicated that all of the wires had less than 5% wire sweep. Figure 12: Wire Sweep Measurement Figure 13: AURTV Package Top View The finished packages (Figure 13) were checked for electrical continuity and cross-sectioned to ensure that we were testing sound parts. Figure 14 shows a micrograph of the edge of one of the parts. Tested parts had good encapsulation with minimal voids and proper fillets around the two die - considered necessary for long term reliability. Figure 11: Wire bonded stacked package before molding Figure 14: Cross section of AURTV Package (BT Substrate, 2 die bonded with bead filled adhesive, wirebonded and overmolded with EMC Finally the most critical phase of this project was reached. Parts were placed in a humidity

6 chamber for 29 days at 35 C/60%RH conditions (JEDEC Level 2a) and then subjected to three simulated solder reflow cycles. All of the parts passed (as measured by change in resistance through the daisy chain pattern less than 10%). A second set of parts fabricated using different filler loading with a significantly higher CTE was tested in parallel but nearly 25% of these parts failed the resistance test. This underscores the importance of optimized formulation in meeting reliability requirements. Parts are now being conditioned for thermal cycling and we also intend to test at JEDEC Level 1. Summary We have demonstrated a reliable stacked die package approach built with spacer filled silicone die attach adhesive to control bond line thickness. This work is part of a program to develop a family of materials that meet the emerging requirements for low cost, reliable portable electronic memory products. Work is continuing on all-silicone packages, and on combinations of different materials to provide effective solutions for the very wide range of new products being designed today in the electronics industry worldwide. Acknowledgements We would like to thank Tan Zhang (Graduate student at Auburn University) for her work on substrate and mother board design for the AURTV, Mike J. Palmer (CAVE lab manager at Auburn University) for his help on wire bonding, Carol Shea (Dow Corning) for her work on adhesive lab support, Stan Dent (Dow Corning) for his project resources support. [5] Larry Wu, Innovative Stack-Die Package- S2BGA, 2002 Electronic Components and technology conference [6] Larry Wu, Yu-Po Wang, The Advent of 3D package Age, S.C.Kee 2000 IEEE/CPMT Int l Electronics Manufacturing Technology Symposium [7] Stanton J. Dent, Katsutoshi Mine, Yoshito Ushio, Michael J. Watson, Technology Roadmap for Silicone Adhesives in Thin Multi-Chip Packages, Proc. Tech. Program - Pan Pac. Microelectronics Symp., 8 th 2003 pp63-67 [8] Gen Murakami, Noriaki Taketani, Hiroyuki Okabe, Semiconductor Packaging Road Map in Japan, Int l Pkg Symp., Semi, B1-B4, 1998 [9] Michael Watson, Printable silicone die attach adhesives and spacers, SEMICON West, San Jose, California, July 13-14,1999. [10] Gary M. Freedman, Evelyn Baldwin, Method and Material for Maintaining Cleanliness of High Density Circuits During Assembly, Proc. Tech. Program - Pan Pac. Microelectronics Symp., 8 th 2003 [11] An Overview of Polydimethylsiloxane (PDMS) Fluids in the Environment, Dow Corning Environmental Information Update Ref. No A-01 rev. 04/98 Available from Dow Corning upon request. Plaskon is a registered trademark of Cookson Electronics, Alpharetta, GA. References [1] Akito Yoshida, Amkor Technology, Presentation material in IMAPS Advanced 3D packaging conference, March 2003, Baltimore, Maryland. [2] Intel Presentation. Presentation material in IMAPS Advanced 3D packaging conference, March 2003, Baltimore, Maryland. [3] Jim Walker, Market Outlook: 3D and SIP package, Presentation material in IMAPS Advanced 3D packaging conference, March 2003, Baltimore, Maryland [4] Marcos Karnezos, Package Level System Integration Enabling Solutions. Presentation material in IMAPS Advanced 3D packaging conference, March 2003, Baltimore, Maryland