Panel Discussion: Advanced Packaging

Transcription

1 Dr. Steve Bezuk Senior Director IC Packaging Engineering Qualcomm Technologies, Inc. Panel Discussion: Advanced Packaging PAGE 1

2 Technical Challenges of Packaging (Mobile Focus) Materials Die materials PAGE 2 Low K and Extreme Low K Dielectrics Fine Pitch Interconnects (<100mm) Substrate materials engineered for: Modulus, fracture toughness, CTE, Tg, shrinkage, cure temperature and kinetics, adhesion to multiple materials, dielectric properties (frequency dependence),.. Mechanical Ultra thin die ( 100mm) CTE Mismatch Warpage Control Preserving Si Strain Engineering 28nm Thermal Poor Thermal Paths No Air Flow, Closed System Electrical Signal Integrity Power DistribuLon FuncLonal ParLLoning Evolution of Si nodes in last 5 yrs 20nm 14/16 nm 1 st gen FINFET 10 nm 2 nd gen FINFET 7 nm 3 rd gen FINFET

3 Interconnect Trends for Packages FC Interconnect using SOP Fine Pitch FC used in mobile devices Die SOP Transition for CuBOL ETS Finer Pitches FC ( 130 um) CuBOL/ETS (>100 um) ETS(>60-80 um) TCFC ( 80 um) PAGE 3 - Fine pitch Cu pillar interconnect - Mass reflow most common and cheapest joining process - Capillary and molded underfills are used - TCFC and Laser Assisted - Lower stress attach - Ability to handle warped substrates

4 Current Mobile Packaging for Apps Processors High End Processors Mid End Processors Low End Processors Pseudo-Embedded POP packages MCeP (Shinko/ Amkor) + + FO Structure InFO (TSMC) Memory Memory Molded Laser PoP (MLP) with or w/o die exposed PAGE 4

5 The Quest for smaller form factor and higher FO-WLP Eliminates die interconnect (bump and wirebonds) and substrate Finer pitches than substrate based technology Substrate technology 10/10um L/S with 7/7um L/S in development FO technology 10-15um L/S common, 2/2um L/S in LVM Shorter interconnects = Lower parasitics Eliminate interconnect stress and ELK crack delamination issues Batch packaging process like WLP, but can be with KGD Potential SiP, Multi-die, 3D Solution Can improve thermal characteristics Larger panel batch processing in development to lower cost Challenges in patterning, sputtering, plating, and metrology over large format Modules Higher component density saves PWB area Finer component pitches than standard SMT line Embedded devices enables 3D 2.1 and higher D s Shorter interconnects = Lower parasitics Interconnect pitches approaching wafer BEOL 2/2um L/S in LVM, 1/1um L/S in development Multiple die or Split die architectures Can require in 2/2um L/S or better Improved power dissipation PAGE 5

6 Wafer Batch Processed Package Evolution WLP Face Down FOWLP WLP with Sidewall Prot. Face Up WLP/ FOWLP Face Down FOWLP POP Face Up FOWLP (InFO) Time Features and Benefits - Lowest cost solu2on if applicable - Finer pitch rou2ng than substrates - Cost effec2ve for die requiring some fan out - Lower parasi2cs - Finer pitch rou2ng than substrates - More robust handling, Not prone to edge cracking - Flat surface to pabern RDL. Finer pitch possible - Mold protec2on over die surface - Thinner POP possible compared to substrate based - Flat surface for paberning RDL. Finer pitch Pillars for POP connec2on than solder balls Challenges - Rel limits die size - Handling issues for EMS - Low K makes worse - Yield challenges because die first - 2+ layers of RDL more expensive than substrate pkg. - Increases cost over WLP - Requires growth of Cu pillar on die increasing cost over face down FOWLP - Cost For 2+ RDL - Cost for 2+ RDL - Cost to grow Cu pillars for POP Applica2ons - Devices that I/O boundary - Many FC applica2ons can port - Mul2 chip modules - Same as WLP - Same as FOWLP, WLP, sidewall protected WLP - Apps processor for high end phones - Apps processor for high end phones PAGE 6

7 2.1/2.5D Advanced Packages for Multichip, Processors, GPUs and FPGA TSI CoWoS, CoW, CoS 2.5D 2.1D FOCoS Fan Out Chip on Substrate SWIFT 2.1D Photo-Defined Organic Interposer (POI) EMIB Suppliers Features Assembly Complexity Multi-die Integration TSMC, Multiple OSATS Si Interposer Glass Interposers in development for improve electrical performance by GaTech Die first or last assembly depending on process flow In LVM Si Interposer +Substrate Assembly ASE Amkor Shinko Intel Die first face down FO construction Leverages HVM processes of standard FOWLP but fine pitch RDL In Dev. FO processes+ PKG to Substrate Assenly Conventional RDL Die last assembly AOI inspected RDL In Dev. RDL+ Chip Joining + PKG to Substrate Assembly Advanced PID Substrate Die last assembly AOI Inspected RDL In Dev. Conventional Chip Joining only Si Bridge Embedding Laser SRO/ Mixed Bump Known Good Si Bridge In LVM Conventional Chip Joining only PAGE 7