ELEC 6740 Electronics Manufacturing Chapter 5: Surface Mount Design Considerations

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1 ELEC 6740 Electronics Manufacturing Chapter 5: Surface Mount Design Considerations R. Wayne Johnson Alumni Professor

2 Outline System Design Issues Package Drivers Real Estate Considerations Manufacturing Considerations Cost Considerations Thermal Considerations Package Reliability Considerations Solder Joint Reliability Considerations Interconnect Considerations CAD Layout Considerations

3 System Design Form, fit and function Form Fit Relates to the physical size, shape, and weight of the product Factor constraints: MULTIBUS I, MULTIBUS II, PC BUS Slot spacings,, connectors, etc. Relationship with other functions or products within the system Function Products basic mission in life

4 System Design Application environment Cost constraints

5 Package Drivers High End Performance Driven Mid-Range Cost/Performance Driven High Electrical & Thermal Performance High performance & Lower cost packages SMT Technology, Cheaper Assembly cost to OEM Package Requirements Narrow pad pitches Decoupling capacitors PGA, BGA, Flip Chip, MCM Thermally enhanced Plastic packages SMT, CPGA, PQFP, PPGA, BGA Entry Level Cost Driven Cheap! Packages Thin and small outline packages For notebooks & chipset applications Low cost plastic QFPs, TSOP, BGA

6 Microprocessor I/O

7 Cost Package Drivers Cost per I/O Thermal Plastic vs. Ceramic Heat sinks, slugs Electrical Parasitics Propagation delay Signal distortion Electrical noise Real Estate Perimeter vs. area array

8 PGA Area array Through hole Robust leads Sockets Known reliability

9 Fine Pitch Packages QFP Real estate Lower cost vs PGA 2-44 watts with heat slug

10 BGA Area array real estate Robust manufacturing process No repair, only rework Inspection, X-ray X only

11 Real Estate Type of SMT Assembly Type III SMT Functional Density Increase 1.05x 1.10x Type II SMT 1.20x 1.40x Type I SMT 2.00x 4.6x

12 Real Estate A = {(a 1 + I 1 )n 1 +(a 2 + I 2 )n 2 +(a 3 + I 3 )n 3 + } K+M A = real estate area requirement a 1, a 2, = land pattern areas of different components I 1, I 2, = interpackage spacing requirements n 1, n 2, = total number of each component K = packing efficiency constant 1.10 for memory board 1.30 for logic board M = reserved area required for miscellaneous purposes such as clearance for edge card guide, automated test assess, etc.

13 Land pattern/package and interpackage spacing

14 Land pattern/package and interpackage spacing

15 Manufacturing Ease of manufacturing Inspection, test, repair Manufacturing capability Component compatibility with assembly process

16 PWB Cost

17 PWB Cost Pitch Ball Dia. Pad Dia. 6/6 5/5 (mil)

18 Blind & Buried Vias

19 PWB Cost

20 Board Area & Layer Count

21 PWB Hole Costs

22 Component Cost CSP more expensive PGAs more expensive Ceramic more expensive

23 Assembly Cost Type of Assembly Through Hole Type III SMT Type II SMT Type I SMT Savings in Placement Cost % 30%

24 Thermal Design T j = (Θ( ja x P d ) +T a T j = junction temperature ( o C) Θ ja ja = thermal resistance, junction to ambient ( o C/W) P d = power dissipation at T j (W) T a = ambient temperature

25 Thermal Design

26 Ceramic Packages

27 Thermal Performance

28 Air Flow

29 Thermal Resistance (Θ ( ja ja) Type of Package DIP 20 pin Lead Frame Material Kovar Thermal Resistance ( o C/W) 68 SOIC 20 pin Copper 97 PLCC 20 pin Copper 72

30 Max Power Rating

31 Package Reliability IPC Electronics trade association EIA Electronic Industries Association JEDEC Joint Electron Device Engineering Council jedec.org

32 Package Cracking During Reflow Assembly Ratio of paddle size to minimum plastic thickness Quantity and distribution of moisture absorbed by the package prior to surface mounting Maximum package temperature during solder reflow/rework Adhesion of molding compound to die, lead frame, and other internal elements Mold or potting compound material properties CTE mismatch between different materials used in the package Component assembly mold process Die Fabrication and wire bonding process (cratering only)

33 Pop Corning

34 During Reflow

35 Moisture Absorption

36 Moisture Absorption & Desorption

37 JEDEC Classification

38 JEDEC Moisture Sensitivity Level Floor Life Soak Conditions Time Time (hrs) Conditions 1 <30 o C 85%RH 2 <30 o C 60%RH 2a <30 o C 60%RH Unlimited o C 85%RH 1 year o C 60%RH 4 weeks o C 60%RH 3 <30 o C 60%RH 168hrs o C 60%RH Joint IPC/JEDEC Standard J-STD-020A

39 JEDEC Moisture Sensitivity Following soak, parts are subjected to 3 reflow cycles Issue Eutectic Sn/Pb or Lead Free Inspected: Electrical Visual for cracks Acoustic microscopy for delamination

40 Inspection Cracks are not allowed to intersect the wire bond, ball bond, or wedge bond. Cracks are not allowed to extend from any lead finger to any other internal feature (lead finger, chip, die attach paddle). Cracks are not allowed to extend more than 2/3 the distance from any internal feature to the outside package

41 Packages & Humidity & Temperature

42 Packages & Humidity & Temperature

43 Plastic Thickness & Die Attach Pad Area

44 Handling Shipped in Dry Bags Desiccant materials Humidity indicator card 6 month shelf-life life if unopened

45 Packaging

46 Bake Out

47 Bake Out Temperature 125 (+5)( o C Duration hours Chamber RH <50% Limited re-bake µin Cu-Sn intermetallic Temperature 40 (+5, -0) o C Duration 192 hours (min.) Chamber RH <5% Unlimited re-bake

48 Solder Joint Reliability Solder Joint Failure CTE mismatch between PWB and component Compliance of lead Corrosion

49 Solder Joint Reliability Type III Type I Type II Random Vibration Pass Pass Pass Mechanical Shock N/A Pass Pass Humiodity Storage Pass Pass Pass Temperature Cycling (operating) N/a Pass Pass Temperature Cycling (non-operating) operating) Pass Pass Pass Life Test Pass Pass Pass Total Solder Joint Cycles 210, , million

50 Environmental Test Conditions Random Vibration 0.01g 2 /Hz sloping to 0.01g 2 /Hz from 20Hz to 1kHz Mechanical Shock 50g sine for 11ms Humidity Storage 5 days at 55 o C, 95%RH Temperature Cycling (operational) -15 to 70 o C for 5 days Temperature Cycling (non-operational) operational) -40 to 125 o C; 2500 cycles Life Test 3000 hours at 60 o C

51 Environmental Test Conditions jedec.org

52 Thermal Cycling & Thermal Shock Dwell times and ramp rates are important Fatigue: cycling strain loading Creep: constant stress loading Solder joint failure includes both fatigue and creep The degree of each is a function of the cycle conditions Cycles to failure in the field are always less than in laboratory tests Less hold time at hign temperature Less stress relaxation

53 Stress Strain No Dwell Time

54 Stress Strain Complete Stress Relaxation

55 Number of Cycles to Failure The area of the hysteresis loop is a measure of the fatigue damage per cycle Cyclic fatigue damage is cumulative The larger the hysteresis loop, the fewer cycles to failure

56 Thermal Cycle Profile

57 Interconnect Connection to Power and Ground Planes Propagation Delay Cross-talk Line width and spacing Line length Dielectric constant Distance from ground plane

58 Cross Talk

59 CAD Parts library Automated layout Design rule checking