Texas Instruments LMG V GaN Power Stage

Transcription

1 Texas Instruments LMG V GaN Power Stage Power Semiconductor report by Elena Barbarini July 2017 version 1 21 rue la Noue Bras de Fer NANTES - FRANCE info@systemplus.fr by System Plus Consulting TI LMG3410 1

2 SUMMARY 3 o Executive Summary o Reverse Costing Methodology Company Profile 8 o Texas Instruments 12 of the o Package analysis Package opening Package Cross-Section o FET Die FET Die View & Dimensions FET Die Process FET Die Cross-Section FET Die Process Characteristic o ASIC Die ASIC Die View & Dimensions ASIC Die Process ASIC Die Cross-Section ASIC Die Process Characteristic Power Stage Manufacturing Process 37 o FET Die Front-End Process o FET Die Fabrication Unit o ASIC Die Front-End Process o ASIC Die Fabrication Unit o Final Test & Packaging Fabrication unit 45 of the cost analysis o Yields Explanation & Hypotheses o FET die FET Front-End Cost FET Die Probe Test, Thinning & Dicing FET Wafer Cost FET Die Cost o ASIC die ASIC Front-End Cost ASIC Die Probe Test, Thinning & Dicing ASIC Wafer Cost ASIC Die Cost o Complete Power Stage Packaging Cost Final Test Cost Component Cost Price Analysis 58 o Estimation of selling price 61 o between Panasonic, Transphorm and GaN Systems HEMT Company services by System Plus Consulting TI LMG3410 2

3 Executive Summary o Executive Summary o Market o Reverse Costing Methodology GaN power device technology is evolving quickly. Due to fast switching and drive complexity, players are providing more userfriendly solutions to accelerate the adoption of power IC technology in power stages. In this context, more solutions with integrated driver or other functions are appearing on the market. Among them we see two approaches: monolithic integration, or a system-in-package solution. Texas Instruments (TI) is the pioneer in the latter. In this report, System Plus Consulting unveils the LMG3410: the first GaN FET Power Stage from Texas Instruments. The device contains a 600V GaN power transistor and a specialized driver in an 8mm x 8mm VQFN package. Texas Instruments introduces to the market a completely new design for GaN FET. The design s optimization allows for integration of a silicon driver and a GaN FET in a compact, standard package. The specific architecture allows for a normally-off device thanks to the integrated silicon MOSFET, which turns the FET off via its source. The new LMG3410 from TI features a medium-voltage breakdown voltage of 600V for a current of 12A (25 C), with very low RdsOn compared to its competitors. The transistor is driven by a specially-designed silicon PMIC with a 0.18 µm technology node. The GaN and AlGaN layers are deposited by epitaxy on a silicon substrate. A complex buffer and template layers structure is used to reduce stress and dislocation. Based on a complete teardown analysis, this report also provides estimated production costs for the PMIC, FET, and package. This report also proposes a comparison with GaN Systems, Transphorm, and Panasonic GaN HEMTs and epitaxy. This comparison highlights the differences in design and manufacturing process and their impact on device size and production cost by System Plus Consulting TI LMG3410 3

4 Texas Instruments GaN products o Texas Instriments Profile o TI GaN Products Texas instruments proposes different integrated solutions with GaN: Part Number VDSS Drain Current (A) Package RdsON (ohm) LMG V 12 VQFN 70 LMG V 10 QFM 15 Analized device 2017 by System Plus Consulting TI LMG3410 4

5 Texas Instruments LMG3410 Datasheet o Texas Instriments Profile o TI GaN Products 2017 by System Plus Consulting TI LMG3410 5

6 Synthesis of the o Package o GaN FET o ASIC Package VQFN 8x8: o Dimensions: 8mm x 8mm x0.9mm o Number of Pins: 32-pin ASIC Package GaN FET FET: o o o Dimension: xxxmm x xxxmm = xx mm² Electrical Connection: xxxx wire bonding Placement in the package: xxxxxx lead frame. Package opening Optical View ASIC: o Dimension: xxxmm x xxxxmm = xxxxmm² o Electrical Connection: xxxx wire bonding o Placement in the package: xxxxxxx by System Plus Consulting TI LMG3410 6

7 Package characteristics o Package o GaN FET o ASIC o o o The package type is a VQFN 8x8 Package size : 8mm x 8mm x 0.9mm Pin pitch : xxxxx mm o The package markings include the following markings : Reference of component Year Month: xxxxxx Assembly lot code XLMG3410 TI 66I AQ86 E4 Assembly site code: xxxxxxx Package Front view Package Side view Package Back view 2017 by System Plus Consulting TI LMG3410 7

8 Package opening o Package o GaN FET o ASIC Wire Bonding: o xxx Gold wire. o Diameter: xxxxµm. o Medium length: xxxxmm Package Source Gate Source GaN FET Drain Package Opening Wire bonding 2017 by System Plus Consulting TI LMG3410 8

9 Package Cross-Section o Package o GaN FET o ASIC Package cross section FET SEM View 2017 by System Plus Consulting TI LMG3410 9

10 FET die Dimensions o Package o GaN FET o ASIC 2017 by System Plus Consulting TI LMG

11 Die Process o Package o GaN FET o ASIC 2017 by System Plus Consulting TI LMG

12 Die cross section o Package o GaN FET o ASIC Die cross section SEM View 2017 by System Plus Consulting TI LMG

13 Die cross section o Package o GaN FET o ASIC 2017 by System Plus Consulting TI LMG

14 Die cross section -Source o Package o GaN FET o ASIC Die cross section SEM View 2017 by System Plus Consulting TI LMG

15 Die cross section -Source o Package o GaN FET o ASIC 2017 by System Plus Consulting TI LMG

16 Die cross section - Epitaxy o Package o GaN FET o ASIC Die cross section TEM View 2017 by System Plus Consulting TI LMG

17 Die cross section TEM Epitaxy o Package o GaN FET o ASIC EDX Spectrum 2017 by System Plus Consulting TI LMG

18 ASIC die Dimensions o Package o GaN FET o ASIC 2017 by System Plus Consulting TI LMG

19 Die marking o Package o GaN FET o ASIC ASIC process Marking This marking give information about the mask set origin in In our economic calculation we have considered a introduction date for production at the middle of µm 2017 by System Plus Consulting TI LMG

20 Die Process o Package o GaN FET o ASIC 2017 by System Plus Consulting TI LMG

21 Die cross section o Package o GaN FET o ASIC Die cross section SEM View 2017 by System Plus Consulting TI LMG

22 Die cross section o Package o GaN FET o ASIC Die cross section SEM View 2017 by System Plus Consulting TI LMG

23 Epitaxy Structure Process Flow (1/2) o FET Fab Unit o FET Process Flow o ASIC Fab Unit o Packaging Fab Unit AlGaN GaN Superlattice Template AlN Superlattice Template AlGaN AlN A thin layer of AlN is deposited on the silicon substrate. The silicon substrate is a carrier substrate and has no function in the transistor. The AlN insulates the GaN layers from the silicon substrate and is the nucleation layer for the next layer. A template layer in AlGaN is deposited. Superlattice structure (AlN/GaN) Epitaxy of the thick GaN layer. Another thick GaN layer is deposited A thin layer of AlGaN is deposited. The top layer of oxide is deposited The MESA is patterned AlGaN GaN Superlattice 2017 by System Plus Consulting TI LMG

24 Structure Process Flow (3/4) o FET Fab Unit o FET Process Flow o ASIC Fab Unit o Packaging Fab Unit S/D Oxyde Metal contact deposition and pattern Oxyde deposition Contact Upper metal deposition and pattern Drawing not to Scale 2017 by System Plus Consulting TI LMG

25 ASIC Front-End Summary o FET Fab Unit o FET Process Flow o ASIC Fab Unit o Packaging Fab Unit 2017 by System Plus Consulting TI LMG

26 Main steps of economic analysis xxx FET Front-End Cost ASIC Front-End Cost xxx o Die Cost o Packaging Cost o Component Cost xxx Probe Test Cost Probe Test Cost xxx Assembly Cost xxx Final Test Cost xxx We perform the economic analysis of the component with the Power CoSim+ and ICPrice+ tools 2017 by System Plus Consulting TI LMG

27 FET Front-End Cost o Die Cost o Packaging Cost o Component Cost 2017 by System Plus Consulting TI LMG

28 FET Die Cost o Die Cost o Packaging Cost o Component Cost 2017 by System Plus Consulting TI LMG

29 Packaging Cost o Die Cost o Packaging Cost o Component Cost 2017 by System Plus Consulting TI LMG

30 Component Cost o Die Cost o Packaging Cost o Component Cost 2017 by System Plus Consulting TI LMG

31 Estimated Manufacturer Price 2017 by System Plus Consulting TI LMG

32 between Transphorm, GaN Systems,Panasonic and TI GaN FET FET Manufacturer Voltage Current at 25 C Current density Epitaxy Wafer thickness PGA26E19BA Panasonic 600V 10A xx xx µm xx µm GS66504B GaN Systems 650V 15A xx xx µm xx µm TPH3206PS Transphorm 600V 17A xx xx µm xx µm LMG3410 Texas Instruments 600V 12A xx xx µm xx µm o Panasonic 600V GaN FET o Transphorm, GaN System and Panasonic 600V GaN FET 2017 by System Plus Consulting TI LMG

33 Related Reports o Company services o Related reports o Feedbacks o Contact o Legal REVERSE COSTING ANALYSES - SYSTEM PLUS CONSULTING Power Semiconductors & Compound Transphorm GaN-on-Silicon HEMT TPH3206PS Efficient Power Conversion EPC V egan FET for LiDAR Systems GaN Systems GaNpx Top Cooled AT&S ECP Embedded Power Die Package Transphorm TPH3002PS 600V GaN on Silicon HEMT GaN Systems GS66508P 650V HEMT EPC2010 GaN 200V power transistor Infineon IPB60R280C6 600V CoolMOS C6 MOSFET Toshiba TK31E60W 4thgen DTMOS 600V Super- Junction MOSFET MARKET AND TECHNOLOGY REPORTS - YOLE DÉVELOPPEMENT Power Electronics & Compound Power GaN 2016: Epitaxy and Devices, Applications, and Technology Trends 2017 by System Plus Consulting TI LMG

34 COMPANY SERVICES 2017 by System Plus Consulting TI LMG

35 Business Models Fields of Expertise o Company services o Related reports o Feedbacks o Contact o Legal Custom Analyses (>130 analyses per year) Reports (>40 reports per year) Costing Tools Trainings 2017 by System Plus Consulting TI LMG

36 Contact PHOENIX YOLE Inc. FRANKFURT/MAIN Europa Sales Office NANTES Headquarter LYON YOLE HQ KOREA YOLE TOKYO YOLE KK GREATER CHINA YOLE o Company services o Related reports o Feedbacks o Contact o Legal Headquarters 21 rue La Noue Bras de Fer Nantes FRANCE sales@systemplus.fr Europe Sales Office Lizzie LEVENEZ Frankfurt am Main GERMANY llevenez@systemplus.fr America Sales Office Steve LAFERRIERE Phoenix USA laferriere@yole.fr Asia Sales Office Takashi ONOZAWA Tokyo JAPAN onozawa@yole.fr Mavis WANG GREATER CHINA wang@yole.fr 2017 by System Plus Consulting TI LMG