Application of the Latency Insertion Method (LIM) to the Modeling of CDM ESD Events

Transcription

1 Applcaton of the Latency Inserton Method (LIM) to the Modelng of CDM ESD Events Dmtr Klokotov, Vrashank Shukla, José Schutt-Ané and Elyse Rosenbaum Department of Electrcal and Computer Engneerng Unversty of Illnos at Urbana-Champagn, Urbana, IL, USA Abstract In ths paper, the applcaton of the latency nserton method (LIM) to the analyss of charged devce model (CDM) electrostatc dscharge (ESD) events n ntegrated crcuts (ICs) s dscussed. LIM s proposed as an alternatve to exstng technques commonly used for chp-level crcut smulaton of CDM ESD. Such smulators, based on the modfed nodal analyss (MNA) method, can underperform n cases that requre very large model szes. LIM was developed specfcally for the analyss of fast transent phenomena n very large networks and s more robust and less resourcehungry than conventonal methods. Introducton Electrostatc dscharge (ESD) has become a major consderaton n the desgn and manufacture of ntegrated crcuts (ICs). ESD mpacts producton yelds, manufacturng costs, qualty, and relablty of contemporary semconductor devces. Problems related to ESD events are ncreasng as the trends contnue toward hgher speed and smaller devce szes. As the nanoscale CMOS devces are fabrcated wth thnner gate oxde, ICs become more susceptble to oxde breakdowns. At the same tme, more functon blocks are beng ntegrated nto a sngle chp, whch ncreases a de sze and leads to larger amounts of statc charge stored n the body of the crcut, and consequently, hgher ESD current and voltage spkes. To avod devce falures due to ESD, preventve measures must be taken. Such measures nclude provdng safe paths for the dscharge current to flow off chp by equppng each IC wth ESD protecton crcutry. Desgn and placement of such crcutry requres dentfcaton of current and voltage dstrbuton durng ESD. Therefore, understandng mechansms of ESD, ablty to test, analyze and model ESD events are now crucal parts of the IC desgn process. A number of dfferent models have been developed to smulate dfferent ESD condtons that cause devce falures. These nclude the human body model (HBM), the machne model (MM), and the charged-devce model (CDM). In ths paper we focus on CDM, whch s currently the domnant ESD model as t s partcularly effectve at smulatng damage nduced by automated equpment, present n every modern manufacturng faclty. Also, as the delectrc falure has become more promnent wth scaled semconductor devces, the CDM accounts for the majorty of ESD falures durng chp manufacturng [1]. The CDM assumes that the IC package s charged ether drectly va trboelectrc effect (.e., va frctonal contact wth some materal), or due to nducton n the presence of an external electrc feld. One or more package pns (e.g., leads, solder balls) subsequently contact a conductve surface at or near ground potental. The charge stored on the metal parts of the devce flows through n a very fast spark dscharge and causes falures of junctons, delectrcs, and components along the dscharge path [2]. Varous hardware test setups have been developed and are used to physcally replcate real-world CDM falures. In these tests, the electrostatc charge s nduced on a devce, and then a dscharge path s created, emulatng the ESD event. Although successful at stress-testng producton devces, physcal tests often do not provde enough nformaton about the exact mechansms of ESD. In partcular, the effects of substrate resstvty, as well as the cases of falures occurrng at nternal nodes of a chp, are hard to nvestgate va test chp desgn and hardware testng. Crcut smulaton presents an attractve tme- and cost-effectve alternatve to physcal tests. Crcut smulatons are partcularly useful for modelng of the falures at nternal nodes of a chp, whch occur due to ESD currents flowng through the substrate of an IC. In order to capture the effects of substrate conductvty, a sutable model has to be used to represent the substrate materal n a smulaton. Snce on-chp devces are represented wth ther crcut models, t s desrable to use a crcut level model for a substrate. Dscrete dstrbuted resstve or resstve-capactve models can be employed to model a substrate materal wth fnte resstvty. However, such representaton may result n very large networks snce the number of substrate network nodes s related to the number of substrate taps (.e. Vss bus connectons to the substrate) and the number of substrate taps can be very bg. The sze of such model makes analyss of the crcut wth conventonal matrx-based methods neffcent or even prohbtve due to prolonged runtmes and excessve memory requrements. In ths paper we propose an alternatve smulaton technque based on the latency nserton method (LIM) [3]. The method s based on the fnte-dfference formulaton smlar to the one used by the well-known fntedfference tme-doman (FDTD) method [4]. LIM teratvely solves crcut equatons for voltages and currents usng a tme-steppng scheme; therefore, t elmnates the need for large matrx equatons employed n modfed nodal analyss. The method s partcularly effcent at modelng very fast transents, such as those occurrng durng CDM ESD events. The method enables the smulaton of substrate models wth very hgh levels of dscretzaton n a reasonable amount of tme; provdes access to voltage and current values at any pont of a crcut model; and allows mappng of the current dstrbuton n the crcut wth very hgh precson. The LIM smulaton of CDM ESD s based on the crcut representaton of the ndustry-standard feld nduced charged devce model (FICDM) ESD test setup [2]. Although the crcut model emulatng the CDM event s uncommon for a /10/$ IEEE Electronc Components and Technology Conference

2 LIM smulaton, the method was found capable of effcent and accurate modelng of ESD transents. Feld-Induced CDM ESD test setup and the equvalent crcut model There are several types of CDM test methods. The one on whch we based our smulatons s the feld-nduced method. In the actual test the chp s placed pns-up ( dead bug poston) on a thn delectrc layer on top of a feld-chargng electrode. The chp capactance s charged ndrectly to a desred stress voltage by a hgh voltage source. Next, one of the package pns s touched wth a pogo pn, whch creates a connecton to the top ground plane and trggers the dscharge event. The tester setup s shown n Fg.1. becomes very tme-consumng f the hgh-resoluton substrate model s used. Another lmtng factor s the sze of the onchp power dstrbuton network. Usng hgh-resoluton substrate model and large on-chp nterconnect network may result n a crcut netlst wth more than a mllon nodes. In such cases, conventonal crcut smulators are neffectve and the use of alternatve methods (such as LIM) s desrable. Basc LIM Formulaton Latency Inserton Method (LIM) treats a network as a grd composed of nodes nterconnected wth branches. Each branch s represented as a combnaton of a voltage source, an nductor, and a resstor n seres (as shown n Fgure 3). Fgure 3: LIM branch representaton Current I j s assumed to be drected from node at voltage V to node j at potentalv j. Each node s modeled as a combnaton of a current source, a conductance, and a capactor to the ground (as n Fg.4). Fgure 1: Feld-nduced CDM ESD test setup. Chp n the dead bug poston. The setup n Fg.1 can be represented wth the equvalent crcut model (Fg.2) [5], [6]. Fgure 4: LIM node representaton Fgure 2: Crcut model of CDM test setup. The model n Fg.2 represents an IC n a wrebonded, leaded package. The crcut model for on-chp devces ncludes power busses, ESD protecton crcutry, and decouplng capactors. The substrate can be modeled as three-dmensonal resstve grd. The package pns as well as the pogo-pn are represented by seres combnatons of resstance and nductance. The charge stored on the elements of the chp and the package s contaned n capactances formed between these elements and the two plates of the tester. Usng the model n Fg.2 the CDM ESD event can be successfully smulated usng SPICE-lke tools. The smulaton, however, Soluton of the dscrete tme equaton for the branch n Fg.3 yelds the followng expresson for branch currents: n 1 n t n 1/2 n 1/2 n n I 1/2 j Ij V Vj RjIj Ej (1) Lj The equaton for node voltages (Fg. 2) reads: n1/2 N CV b n n H Ik n1/2 t k1 V (2) C t In the above equaton, N b s the number of branches connected to the node (excludng connectons to the ground). Superscrpt n n (1) and (2) denotes dscrete tme. Currents are computed at whole tme ntervals, voltages at half ntervals. In ths way, computatons of voltages and currents are alternated n tme. Ths scheme s known as the leapfrog algorthm and s smlar to the Yee algorthm used n the fnte-dfference tme-doman method [7] Electronc Components and Technology Conference

3 As seen from (1) and (2), the presence of latency generated by reactve elements L j and C s requred for the algorthm to functon. If reactve elements are not present n the crcut, small fcttous nductors must be nserted n each branch, and capactors must be added at every node to enable LIM formulaton. It can be shown that f the values of those fcttous elements are small enough, the accuracy of the smulaton s not compromsed [3]. The LIM algorthm uses central dfference based fntedfference approxmaton, whch s condtonally stable. The condton for the numercal stablty of the method can be wrtten as [8] Nn N C b t 2mn mnlp, (3) 1 N p1 b where N n s the total number of nodes, Nb s the number of branches connected to node, C s capactance at the node, L p, s the value of pth nductor connected to node, Condton (3) s formulated for the sem-mplct update scheme, under the assumpton that G =0. A more conservatve (and more robust) upper bound for the tme step s Lp, C t mn (4) p, N b The condton for the tme step n (4) was observed to be workng when floatng capactors were present n the crcut. ESD event smulaton usng LIM To llustrate how LIM can be appled to the smulaton of ESD events, we consder a smple crcut example shown n Fg.5. The crcut n Fg.5 represents a lumped model of all the key elements of the CDM test model n Fg.2. The crcut essentally represents a sngle pn between the two plates of the tester, wth a sngle resstor R sub modelng the substrate, and a dode representng on-chp crcutry. All nodes of the crcut are precharged to the desred stress voltage, then the swtch s closed, the connecton to the ground plane s establshed, and the dscharge through the pogo-pn occurs. the crcut n Fg.5 must be augmented. The three nodes of the crcut have capactors connectng them to the ground plane. Snce n the LIM smulaton the ground plane s treated as the deal crcut ground wth constant zero voltage, these capactors can be treated as standard node capactors n the LIM scheme. However, capactors C 1 and C 2 are floatng, and thus do not ft nto the standard LIM format. Branch capactors requre specal treatment n the LIM and are processed usng the drect ntegraton method [8]. Some nodes of the crcut do not have capactance; small fcttous capactors to ground are added at such nodes to create latency. Small fcttous nductors must also be nserted nto some of the branches. The resultng augmented crcut s shown n Fg.6. Fgure 6: LIM-enabled smple crcut schematc Fgure 7: Small crcut ESD current waveform. Current s probed at the pogo-pn. Fgure 5: Smple crcut example As mentoned earler, the LIM algorthm requres that the crcut be represented as a network of nodes and branches contanng latency elements. To enable the LIM smulaton, Fnally, the test crcut contans a nonlnear element, a dode. Nonlnear devces can be ncorporated nto the LIM algorthm as shown n [3]. The nonlnear equaton for current flowng through the dode s solved teratvely at each step of the smulaton. Intally, voltage at all nodes of the crcut s set to the precharge value; then, voltage at the node representng the ground plane s forced to zero, and the smulaton begns. Results of the LIM smulaton are shown n Fg.7. The crcut was precharged to 300 V. Fg.7 shows a typcal ESD transent current waveform wth a very sharp spke occurrng wthn the frst 0.5 ns. The whole dscharge event takes less Electronc Components and Technology Conference

4 than 3 ns. To verfy the LIM results, the same smulaton was performed usng an MNA-based commercal crcut smulator (MNA-CS). As evdent from Fg.7, there s a good agreement wth the LIM results. Analyss of the full chp model usng LIM The full chp model used for the smulaton ncludes the dscrete dstrbuted resstve model for the substrate n the form of a three-dmensonal resstve grd [5], [6]. The grd s composed of cells; each cell contans 6 resstors (as shown n Fg. 8). The dscharge current waveform observed at the pogo-pn has the shape characterstc for the CDM ESD event. The frst current spke exceeds 6 A, wth a very fast rse tme of roughly 0.5 ns. In the LIM smulaton we can probe voltage at any node and current through any branch n the crcut. For example, we can observe transent voltage waveform at one of the nodes nsde the substrate (Fg.10). Fgure 8: Unt cell of a lumped resstve substrate model. The model for the on-chp crcutry ncludes power buses, modeled wth resstve chans. Dode-based ESD protecton crcutry s also ncluded as well as decouplng capactors. The resultng netlst contans over 82,000 nodes. The crcut s precharged to 300 V, the dscharge connecton s realzed va the low resstance (20 Ohms) pogo-pn. The resultng current transent current flowng through the pogo-pn s shown n Fg.9. MNA-CS s agan used to verfy the LIM results. Close agreement between LIM and MNA-CS results s observed. Fgure 9: CDM ESD current waveform. Fgure 10: Transent voltage at one of the nodes nsde the substrate. Agan, close agreement wth the results of the smulaton wth the commercal tool can be observed. Conclusons The latency nserton method was appled to the analyss of the CDM ESD event. It was demonstrated that the LIM can accurately smulate the fast transents emergng durng the dscharge event. The full chp model that accounted for substrate conductvty and stresses occurrng at the nternal nodes of the chp was used n the smulaton. Results of the LIM smulatons are n close agreement wth the ones obtaned usng a commercal MNA-based crcut smulator. Whle for small test cases conventonal tools were observed to be faster than the LIM, as the crcut sze ncreases the LIM becomes more effcent, and can sgnfcantly outperform other methods when the node count s n the mllons. References 1. Lee, J., K.-W. Km, Y. Huh, P. Bendx, S.-MKang, Chp- Level Charged-Devce Modelng and Smulaton n CMOS Integrated Crcuts, IEEE Transactons on Computer-Aded Desgn of Integrated Crcuts and Systems, Vol. 22, No. 1, 2003, pp ADI Relablty Handbook. Analog devces, Inc., Norwood, MA, Schutt-Ané, J. E., Latency nserton method (LIM) for the fast transent smulaton of large networks, IEEE Trans. Crcut Syst., vol. 48, Jan. 2001, pp A. Taflove, Computaton Electrodynamcs: The Fnte- Dfference Tme-Doman Method. Boston, MA: Artech House, Electronc Components and Technology Conference

5 5. M.S.B Sworarraj, Smedes T, Salm C., Mouthaan, A.J. and Kuper, F.G, Role of package parastcs and substrate resstance on the CDM falure levels, Mcroelectroncs Relablty, vol. 43, pp , Shukla, V. Jack, N and Rosenbaum, E., "Predctve Smulaton of CDM Events to Study Effects of Package, Substrate Resstvty and Placement of ESD Protecton Crcuts on Relablty of Integrated Crcuts", In press, IEEE Internatonal Relablty Physcs Symposum Yee, K. S., Numercal soluton of ntal boundary value problems nvolvng Maxwell s equaton n sotropc meda, IEEE Antennas Propagat., vol. AP-14, May 1996, pp Lalgud, S. L., Swamnathan, M., and Kretchmer, Y., On-chp power-grd smulaton usng latency nserton method, IEEE Trans. Crcut Syst., vol. 55, no. 3, Apr. 2008, pp Electronc Components and Technology Conference