INTERCONNECTION AND GATE DELAYS IN CMOS VLSI CIRCUITS

Transcription

1 INTERCONNECTION AND GATE DELAYS IN CMOS VLSI CIRCUITS El beta PIWOWARSKA Warsaw Unversty of Technology, Insttute of Mcroelectroncs & Optoelectroncs ul. Koszykowa 75, Warszawa, POLAND tel./fax: (48)-(22) , e-mal: Summary: The paper presents results of delay tme measurements for CMOS nverter and descrbes an expermental chp. The chp was desgned and fabrcated n ECPD12 technology (1.2 µm of channel length). Delay tmes were measured for mnmal sze nverter and for nverter loaded wth long nterconnecton. The comparson between expermental results and some models was made. The nfluence of partcular parastc parameters was defned for VLSI CMOS crcuts condtons. 1. INTRODUCTION Development of very hgh-speed ntegrated crcuts s of great nterest. The expermental S crcuts wth an average propagaton delay below 100 ps were realzed n small scale of ntegraton [6, 7]. However for VLSI crcuts some lmts exst. The most mportant s that the average nterconnecton length per gate ncreases wth the gate count and logc cell layout area. Speed becomes lmted not only by the devce speed tself, but also by the fact that each gate should drve nterconnectons [1, 7]. For long nterconnectons propagaton delay s lmted by the nterconnecton parameters. The second aspect s that the speed of devce does not grow suffcently wth the feature sze decreasng [3]. The scalng of dfferent areas does not proceed n the same manner. The channel area decreases faster than actve areas. For modern technologes the dopng of the actve area ncreases. Ths causes that for technologes wth small feature sze the juncton capactance becomes comparable wth the gate capactance. The devce delay s lmted not only by gate capactance but also by actve area juncton capactance. The delay ncreases and ts estmaton becomes more complcated. In specalzed desgn of VLSI crcuts the aspect of devce delays should be consdered carefully. Theoretcal models for devce propagaton delays and nterconnecton delays should be verfed. Models true for bgger feature sze technologes mght fal for small feature sze. RC model for nterconnectons mght become not vald f the crcut speed ncreases so that the nductance effects become sgnfcant. An experment was carred out to consder these problems.

2 2. EXPERIMENTAL CHIP An expermental chp for measurng nverter and nterconnecton delays was desgned and manufactured n CMOS ECPD12 (1.2 µm channel length) technology. Delays are calculated from measured rng oscllator perod. The perod T of rng oscllator s equal: n ( ) T = t LH + t HL = 2 t pd, (1) =1 where n s a number of nverters, t LH hgh to low respectvely, t pd and t HL 50% pont of the nput to the 50% pont of the output). n =1 are tmes of output transton from low to hgh and from average propagaton delay (each parameter s referred as tme perod from the The functonal scheme of expermental chp named DELAY s presented n fg. 1. R 4 R 3 R 2 multplexer to osclloscope dvder /1 /4 /16 /128 /256 R 1 multplexer Q Osc. counter control crcut COUNTER dvder /256 fg. 1 Scheme of chp DELAY. There are four rng oscllators. Each one conssts of 99 dentcal mnmum sze symmetrcal transton characterstc nverters. The bg number of nverters was chosen to obtan stable oscllatons n the range of frequency easy to measure. The frst oscllator s for measurng nverter delay. The other are for measurng delay of nverter loaded wth long nterconnecton. The nverters n a rng are connected between each other wth the long nterconnectons of 250 µm length and 3 µm wdth each. The nterconnectons were desgned n dfferent way: n metal1 over n-well for Rng 2, n poly over n-well (Rng 3) and n metal1 over substrate (Rng 4). The measurement of rng oscllator perods s realzed on chp. Pulses from the rng oscllator chosen by the multplexer are counted by 16-bt counter. The countng s made n the tme delmted by a standard quartz oscllator (marked Q Osc. n fg. 1) of frequency khz. The frequency of the oscllator s dvded to obtan long countng tme. The counter s controlled by logc crcut (counter control crcut),

3 whch allows to halt the counter state exactly after one pulse of the standard sgnal. The result s kept untl the counter s reseted wth external sgnal, whch smultaneously starts another countng. A checkng output of measured oscllator sgnal s also desgned. The rng oscllator sgnal after frequency dvson has the frequency whch can be easy observed by external osclloscope or measured by frequency meter. Ths soluton avods the error n the case of ncorrect on-chp measurng crcut workng. Results of on-chp measurements close to external measurement results confrm correctness of the on-chp measurement. 3. RESULTS OF THE MEASUREMENTS The expermental chp was measured usng LogcBox and DesgnWorks software from Caplano Computng System Ltd. The LogcBox allows to control and observe dgtal hardware usng computer. Real sgnals n a chp are converted to smulated sgnals n a LogcDesgn schematc and can act as nputs to smulated logc devces. The hexadecmal dsplays were used for output counter sgnals readng. The state of the on-chp counter was read drectly from computer n hexadecmal code. Usng that method many measurements could have been carred out n a short tme. Results of partcular measurements for one chp dd not dffer more than 1% from each other and were stable n tme. Results for dfferent chp dffered slghtly due to dsperson of technology parameters. The results of the onchp measurements are presented n table 1. The values n the table are average values of propagaton delay per one nverter obtaned from many measurements made n dfferent tme. t pd [ps] chp 1 chp 2 chp 3 chp 4 chp 5 average Rng Rng Rng Rng tab. 1 Measured average delay tme per one nverter. The propagaton delay of mnmum sze nverter loaded wth dentcal nverter s much more than 100 ps what s assumed to be a lmt for lumped element models. The bandwdth of CMOS crcuts n ths technology estmated as [8]: BW = 0.35 t r where t r 2.3t pd, (2) s below 0.4 GHz. The transmsson lne models for nterconnectons are not needed n the range of frequency. The propagaton delays for nverters loaded wth 250 µm long nterconnectons are more than twce bgger than for nverter loaded only by another mnmum sze nverter. It means that even for that length of nterconnecton the load mpedance s lmted by nterconnecton parameters not by drven gate parameters. In recent VLSI crcuts average length of per gate nterconnecton s n order of several mllmeters [7]. The measured delays for dfferent nterconnectons (the strps made from dfferent materal) dffer

4 between each other n accordance to theory owng to the dfferences of the lne capactances and resstances. 4. COMPARISON WITH THEORETICAL MODELS The smplfed model of nverter delay s presented n fg. 2 [1, 2, 3, 4, 5]. + + V n Vout Vn R tr Cnt V out Cgate t pd = R tr ( C gate + C nt ) Fg. 2. Model of gate delay. The gate delay s determned by the on-resstance of the drver R tr and capactances of the nterconnecton and the recevng gate C nt, C gate. To a frst order model parameters are gven [1]: R tr w L C gate = 1 C gox( V DD V T), ox w n L n + w p L p t gox, C nt = ox w nt l nt t fox. Usng (3) for catalog and taken from electrcal report parameters of ECPD12 technology one obtans: Rng 1 Rng 2 and Rng 4 Rng 3 t pd = 22 ps t pd = 76 ps t pd = 119 ps The dfference between calculated and measured values s of an order of magntude. Addng edge capactances to nterconnecton and overlap capactances to the gate capactance gves: Rng 1 Rng 2 and Rng 4 Rng 3 t pd = 26 ps t pd = 111 ps t pd = 163 ps The accuracy s stll unacceptable. Some more complcated formulas for gate delay calculatng were proposed n lterature [2, 3]. They are based on dren current ntegratng durng load capactance chargng. The load capactance s assumed to be constant and charged by one transstor. The current of the second transstor s neglected. The analtycal soluton can be obtan for ths case only. Fgure 3 presents model for transton from hgh to low calculaton. Usng ths formulas mproves the accuracy but as was checked for the example under consderaton errors are greater than 500%. The man source of errors n smplfed models s neglectng of actve areas juncton capactance. The mportance of juncton capactance grows wth the feature sze decreasng. There are two aspects of ths phenomenon. Frst the actve area lmted by contact sze does not decrease as quckly as gate area wth the (3)

5 scalng of technology. The second s ncreasng of actve area dopng for modern technologes. For measured nverters juncton capactance of the actve area was close to the gate capactance. Omttng juncton capactance durng electrcal smulatng of manufactured crcut caused errors of about 100%. HSPICE smulator was used. V DD V n IL ID IC C out V out I D = C out dv out dt + I L, I D >> I L, I D C out dv out dt. Fg. 3. Model for dschargng load capactance. The necessty of ncludng juncton capactance C j complcates the model of gate delay. In ths case none of the currents I L, I D (fg. 3) can be neglected. The load capactance s charged (dscharged) wth smaller current and the transton tme decreases. Fgure 4 presents the smulated currents durng nverter swtchng [2, 3]. HSPICE was used. The smulated nverter has the same parameters as rng oscllator nverters n expermental chp. When juncton capactance s neglected (fg. 4.b) the loadng current s very close to NMOS (dschargng) or PMOS (chargng) current. Addng juncton capactance C j n transstor model causes sgnfcant decreasng of loadng current. Assumpton ID = 0, or IL = 0 s not vald and analytcal solutons based on ths assumpton fal. Fg. 4 Voltage and currents durng nverter swtchng, a) output voltage, b) currents forcj 0, c) currents for Cj = 0. HSPICE models [8] predct gate delay wth good agreement wth expermental results f parameters of those models are precsely defned. All parastc parameters must be specfed. It was observed that for the wres wth neglgble losses model of fg. 3 can be qute good approxmaton f resstance of the drver R tr s corrected on the base of emprcal results or results of full electrcal smulaton. The measured or smulated values are backsubsttuted nto approprate delay equaton.

6 Inaccuracy of that approach (4) s estmated as no more than 50% - 60% n comparson to HSPICE smulaton whch proved to be n good agreement wth experment. The juncton capactance of dren C jd should be added to gate and nterconnecton capactance n that case. The accuracy of such an approach s better for bg values of load capactance. t pd = R tr ( C gate + C jd + C nt ), measured (smulated) value R tr =. C gate + C jd + C nt ( ) For long or lossy wres the resstance of nterconnecton R nt must be taken nto account [1, 2, 4, 5]. The proper model of the nterconnecton s RC dstrbuted lne model. The good analytcal soluton for RC dstrbuted lne drven by resstance exsts [4, 5]. However any analytcal model s applcable n general when C j and R nt are sgnfcant. For the measured chp omttng the resstance of metal wres does not change the results of delay calculatons. For poly lne RC wre model mplemented n HSPICE smulator [8] gves accurate results. The nductance L nt of nterconnectons s neglgble, because the bandwdth of crcuts under consderaton s low such that the resstance of drver s much greater than R nt + jωl nt. The dfference between delays calculated usng RC model and other models (RLC, transmsson lne model) are neglgble. (4) 5. CONCLUSIONS The expermental chp for delays measurng was desgned and manufactured n CMOS 1.2 µm channel length technology. Results of measurements show lmts n CMOS crcuts speed wth small feature sze. The theoretcal models were compared to results of measurement. The sgnfcance of actve area juncton capactance for crcuts contanng small sze transstor was shown. The mperfecton of analytcal delay calculaton models was revealed. The only way to correctly predct the delay n crcut contang small sze transstors s electrcal smulaton wth the use of full transstor equvalent crcut. All parastcs must be taken nto account. Due to small bandwdth and bg drver resstance of CMOS crcuts on-chp nterconnectons can be modeled as RC dstrbuted lnes. REFERENCES [1] H. B. Bakoglu, "Crcuts, Interconnectons, and Packagng for VLSI," Addson-Wesley Publshng Company, [2] N. H. E. Weste, K. Eshraghan, "Prncples of MOS VLSI Desgn," Addson-Wesley Publshng Company, Second Ed [3] J. P. Uyemura, "Fundamentals of MOS Dgtal Integrated Crcuts," Addson-Wesley Pub. Com., [4] T. Sakura, Approxmaton of Wrng Delay n MOSFET LSI's, vol. 18, No. 4, pp , Aug [5] T. Sakura, "Closed-Form Expressons for Interconnecton Delay, Couplng, and Crosstalk n VLSI's," IEEE Trans. on ED, vol. 40, No. 1, pp , Jan [6] L. W. Schaper, D. I. Amey, Improved Electrcal Performance Requred for Future MOS Packagng, IEEE Trans. on CHMT, vol. 6, No. 3, pp , Sep [7] H. Hasegawa, S. Sek, "Analyss of Interconnecton Delay on Very Hgh-Speed LSI/VLSI Chps Usng an MIS Mcrostrp Lne Model," IEEE Trans. on MTT, vol. 32, No. 12, pp , Dec [8] HSPICE Manual. Vol II, "Elements and Models,",Vol. III, "Analysys and Methods"