Floorplanning with IR-drop consideration

Transcription

1 Floorplannng wth IR-drop consderaton Jan Chen 1, Chonghong Zhao 1, Dan Zhou 2, Xaofang Zhou 1 1 ASIC & System State-key Lab 2 Department of Electrcal Engneerng Mcroelectroncs Department School of Engneerng and Computer Scences Fudan Unversty The Unversty of Texas at Dallas Shangha , P. R. Chna Rchardson, TX Abstract: As technology advances, wth supply voltage decrease and power densty ncrease modern chps suffer more serously IR-drop problem. In ths paper IR-drop constrant s consdered n floorplannng stage n order to solve problem n the early stages of physcal desgn and shorten tme to market. Frst a fast model wth some extend of accuracy s proposed to quantfy the IR-drop of a block. And then selecton strategy n smulatng annealng based on the model beng ntroduced. The experments show that the algorthm proposed n ths paper can reduce the chp average IR-drop and maxmum IR-drop effectvely and only brngs a lttle tradeoff n area. Key Words: VLSI IR-drop Floorplannng Smulatng Annealng Wre-bond 1. Introducton Wth the advance of VLSI manufacturng technology and market requrement, chps that ntegrate more functonalty are operatng at hgher frequency and requre hgher current and more power. The lower supply voltage, hgher power densty and longer wre length deterorate the IR-drop problem, whch s due to large current passng large power network resstance. So IR-drop wll be fast becomng one of domnant factors determnng the chp frequency. Due to on-chp IR-drop, the actual voltage supply of standard cells on chp s less than the power-supply voltage, whch results nsuffcent drvng strength and fnally lower chp frequency. Even the chp mght not work normally for setup tme or hold tme volaton, f care s not taken nto clock tree delays caused by on-chp IR-drop. So n today s new nterconnect-centrc paradgm [1], new terms such as IR-drop, power and sgnal relablty have become as mportant, or more mportant, as chp area, whch was a prme concern for prevous technologes. In ths paper we address IR-drop problem n floorplannng stage. Floorplannng s the frst stage n physcal desgn. And the areas and relatve postons of blocks are determned, and varous constrants are also concerned n ths stage. As a key stage floorplannng bulds the framework for a feasble layout and can be used to verfy the feasblty of a desgn. IR-drop problem has close connecton wth block postons and f the problem can be well solved n ths early stage, t wll reduce the desgn return tme and shorten tme to market. In tradtonal floorplannng stage [2] chp area and wre length s optmzed, but these factors are less crtcal n DSM era. We ntroduce IR-drop constrant n floorplannng to address to more and more serous tmng and sgnal ntegrty problem Ths research s supported by NSF grants CCR , and s also supported partly by NSFC research project , , partly by Cross-Century Outstandng Scholar s fund of Mnstry of Educaton of Chna, partly by Natonal 863 plan projects 2004AA1Z1050, 2003AA1Z1120, Shangha Scence and Technology commttee Key project 04JC14015 and Shangha AM R&D fund 0418.

2 caused by voltage drop. Because the exact analyss about on-chp IR-drop can only be performed after route power network. However t s unpleased to dscover IR-drop volaton n ths late stage. So a fast and accurate model to calculate the IR-drop n early physcal desgn stage s needed. In ths paper we propose a feasble model to estmate the IR-drop of blocks n foorplan stage. Wth ths model we propose our floorplannng appoarch based on smulatng annealng algorthm. Fnally the expermental results are encouragng. Through comparng wth tradtonal floorplanner wthout IR-drop consderaton, we obtan floorplans wth sgnfcantly less maxmum IR-drop and average IR-drop and wth only a lttle area ncrease. The rest of paper s organzed as follows. Secton 2 descrbes our fast IR-drop model and calculaton of a floorplan IR-drop cost. Smulatng annealng wth IR-Drop constrant s ntroduced n Secton 3 and the selecton strategy s also descrbed n ths secton. Secton 5 shows our approach for floorplannng wth IR-drop consderaton. Fnally expermental results and concluson are stated n Secton 5. through the resstance of the power dstrbuton network. Sharp IR-drop wll cause logc error because of nsuffcent supply of voltage. Snce IR-drop has close relatonshp wth blocks postons, we should consder the IR-drop constrant n floorplannng stage durng VLSI physcal desgn. In floorplannng stage the unt block can be a CPU core, DSP core, memory core and so on. After floorplannng the maxmum IR-drop value of every block should be wthn ts IR-drop margn by specfcaton. For sze of problem we need a fast and accurate model to quantfy the IR-drop values of blocks. For the chp wth wre-bond package, there s power/ground rng surroundng the chp (Fg. 1) [3]. Ths power/ground rng s connected to the on-chp power network, whch dstrbutes power across whole chp. The rng s made by wde transfer lne n order to reduce the voltage drop along t. Hence, IR-drop s neglgble wthn the power/ground rng, resultng n the constant voltage boundary condton [3]. And For smplfcaton we assume that IR-drop s only caused by resstance of nner power network s for wre-bond package. 2. IR-Drop Model IR-drop s the voltage drop due to current passng Prevously, several IR-drop models have been ntroduced [3-5]. In [3] a smple and accurate model s ntroduced for wre-bond package as follows. mπ nπ VIR ( x, y) = Emn sn( x)sn( y) Eq.1 a b n= 1 m= 1

3 Where V IR (x,y) s the IR-drop of a pont at (x,y) on the chp, a s the heght of the chp and b s the wdth, and E mn s a coeffcent whch depends on the current dstrbuton across the chp. For a unform current dstrbuton, the maxmum voltage drop s at the center of the chp [3]. (, ) ( a, b V ).2 IR max x y = VIR x= y = Eq 2 2 If the IR-drop s calculated by usng Eq.1 drectly, the spendng wll be too large to be accepted. It s the bottleneck of the algorthm. Ths paper extends the applcaton of Eq.1. The dstance between the observed pont (x,y) and the maxmum IR-drop pont s used to quantfy the IR-drop of pont (x,y). The expermental results n Fg.2 shows that the actual IR-drop of pont (x,y) s mostly lnear wth the dstance between the pont and the maxmum IR-drop pont on the chp. Hence, a possble IR-drop cost functon can be wrtten as follows. n CostIR = d where d = dmax d ' Eq.3 Where n s the number of block, d max s the maxmal dstance between a pont on the chp and maxmal IR-drop pont and d s the dstance between block s center pont and maxmal IR-drop pont. Such cost functon s smply, but the mpact of coeffcent of E mn s not consdered. Furthermore n practce margns for IR-drop of blocks are dfferent. Some blocks run at hgh frequency f, whch demand a strct tmng relaton. A lttle IR-drop for these blocks wll cause chp malfuncton. So a weght w varable s ntroduced n IR-drop cost functon n order to reduce the IR-drop for the needy block. w has drect proporton wth frequency f f w ). Now the cost functon s as follows. ( Cost = w d Eq.4 IR For block wth hgh frequency consumes hgh power p and has hgh power densty ρ, w can be calculated as follows. ρ p w =, ρ = Eq.5 ρ a Where the area. ρ s power densty, p s the power, a s 3. Smulatng Annealng Wth IR-drop Constrant Floorplannng wth IR-drop consderaton can be descrbed as follows: Gven N blocks b 1 b n, where a set b = { a, p},1 n, a s the block area, p s the block power, fnd a feasble soluton such that IR-drop and chp area s optmzed maxmally. Durng smulatng annealng process the move probablty s controlled when optmzng IR-drop. If the IR-drop of a block s large, the selecton probablty for t s large. And meanwhle the selecton probablty s also large for a block wth small IR-drop. Ths means blocks wth large IR-drop or small IR-drop are more probably selected for move durng smulatng annealng. Such selecton strategy wll produce more even IR-drop dstrbuton as shown n Fg.3. The contrbuton to IR-drop cost functon s same for both stuatons n Fg.3 (a) and Fg.3 (b). However stuaton n Fg.3 (b) s preferred, because more even IR-drop dstrbuton s produced than

4 stuaton n Fg.3 (a) and block e n Fg.3 (a) may suffer from logc error for large IR-drop. In practce the goal s to confrm every block of chp satsfes ts IR-drop constrant and the whole chp functons normally. Accordngly the selecton probablty dstrbuton as shown n Fg.4 s adopted, where X-coordnate denotes IR-drop and Y-coordnate denotes the probablty of certan IR-drop. The selecton process s as shown n Table 1: Table1. Selecton Strategy 1. Calculate every block s IR-drop (IR ); 2. Calculate the average IR-drop N 1 IR ( IR = = 0 ); avg N 3. Calculate the absolute dfference between IR avg and IR ( Abs = IR IR avg ); 4. Sort the Abs (0N-1) n set Ary by descendng order. 5. Generate a random number Rnd between [0, N-1] whch meets norm dstrbuton. 6. Select the block chosen by Ary[Rnd] for move. 4.Floorplannng Wth IR-drop Consderaton Our flooplannng algorthm wth IR-drop consderaton s based on the H. Murata, et al [7] floorplan representaton approach. Accordngly n our algorthm a legal floor plan s represented by a sequence par (SP). In ths paper nstead of optmzng chp area or chp area and wre length n tradtonal floorplannng algorthm, we propose to perform IR-drop plannng wth respect to current foorplan be consdered and n result to obtan a much better floorplan wth less IR-drop constrant volaton n followng physcal desgn stages. For the cost functon, we use the followng equaton. Cost = α Area + βwrelen + λcostir Eq.6 Where Area s the total chp area, WreLen s the total chp wre length and CostIR s the cost value of total chp IR-drop that can be calculated by before mentoned approach n secton 2. The coeffcents α, β and λ are weghtng parameters of chp area, chp wre length and IR-drop cost respectvely. Users due to the mportance of the optmzaton terms can change these coeffcents. 5. Experment We have tested our approach on some MCNC buldng blocks benchmarks. All experments were carred out on 2.8G-pentum-IV processor. For benchmarks wthout enough nformaton on current or voltage, we randomly generate t on the bass of benchmarks wth ths nformaton. In our all experments, we only optmze total chp area and IR-drop. So the wre length weghtng parameter s zero. And we set IR-drop and area weghtng parameters as 0.3 and 0.7 respectvely. Talbe2-4 show the comparson results between results obtaned by our approach and results obtaned

5 by a tradtonal floorplanner wthout IR-drop consderaton. In these tables, IR max row shows the maxmal IR-drop, IR ave row s the average IR-drop and Area row s the area. The row shows the mprovng degree that s our result subtracted from tradtonal floorplanner result then dvded by tradonal result. We can see that our approach effectvely reduces maxmal IR-drop and average IR-drop of a floorplan and brng a lttle area ncrease. For am33 benchmark that contans 33 blocks, we get 81.6% maxmal IR-drop decrease, 36.5% average IR-drop decrease and only 6.5% area ncrease. For am49 benchmark that contans 49 blocks, we get 93.1% maxmal IR-drop decrease, 56.6% average IR-drop decrease and only 5.7% area ncrease. For some benchmark Xerox than only contans 10 blocks, we also get some mprovement n maxmal IR-drop and average IR-drop wth a lttle area ncrease. In Fg. 5 shows IR-drop dstrbutons of floorplan obtaned by our approach and tradtonal approach wthout IR-drop consderaton. Where the darker blocks are suffered from more serous IR-drop than other blocks. We can see the floorplan by our floorplanner has more even IR-drop dstrbuton and less dark IR-drop blocks than floorplan obtaned by a tradtonal floorplanner. In concluson, we have proposed an approach to consder IR-drop constrant n floorplannng stage. Wth a fast and accurate IR-drop model and certan selecton strategy, our algorthm can get encouragng results quckly. Wth slght area ncrease, we obtan large reducton on maxmal and average IR-drop of a floorplan. Table 4. Xerox IR max % IR ave % Area % Ours Trad (a) Am33 result by tradtonal floorplanner Table 2. Am33 IR max % IR ave % Area % Ours Trad Table 3. Am49 IR max % IR ave % Area % Ours Trad (b) Am33 result by ours Fg. 5. Am33 floorplan obtaned by tradtonal floorplanner and ours. Dark color blocks sufferng from large IR-drop.

6 Referecnes [1] J. Cong. An Interconnect-Centrc Desgn Flow for Nanometer Technologes. Proceedngs of the IEEE, 89(4): , Aprl [2] D.F. Wong and C.L. Lu. A New Algorthm for Floorplan Desgn. In Proceedngs IEEWACM Desgn Automuton Conference, pages , [3] Kaveh Shaker, James D. Mendl. Compact physcal IR-drop models for chp/package co-desgn of ggascale ntegraton (GSI). IEEE Transactons on Electron Devces, 52(6) : , June [4] L. A. Arledge and W. T. Lynch. Scalng and performance mplcatons for power supply and other sgnal routng constrants mposed by I/O pad lmtatons. In Proc. IEEE Symp. IC/Package Desgn Integraton, Feb. 1998, pp [5] J. W. Joyner and J. D. Mendl. A compact model for projectons of future power supply dstrbuton network requrements. In Proc. ASIC/SOC Conf., Sep. 2002, pp [6] Hung-Mng Chen, L-Da Huang, I-Mn Lu, Mnghorng La and Wong, D.F. Floorplannng wth power supply nose avodance. In Proceedngs of the ASP-DAC. Page(s): , Jan [7] H. Murata, K. Fujyosh, S. Nakatake and Y. Kajtan. VLSI Module Placement Based on Rectangle-Packng by the Sequence Par, IEEE Trans. on CAD 15(12), pp , [8] S. N. Adya, I. L. Markov. Fxed-outlne Floorplannng Through Better Local Search, In Proceedngs of ICCD 2001, pp