Deep Healing: Ease the BTI and EM Wearout Crisis by Activating Recovery

Transcription

1 Deep Healing: Ease the BTI and Wearout Crisis by Activating Xinfei Guo and Mircea R. Stan Department of Electrical and Computer Engineering University of Virginia, Charlottesville, Virginia Abstract The down-scaling of CMOS technologies into the nano-regime and the advent of the IoT era jointly conspire to elevate wearout effects to the status of major reliability threats. Bias instability (BTI) and Electromigration () are two of the dominant wearout mechanisms which affect transistors and on-chip interconnect, respectively. Both phenomena have been shown to exhibit partial recovery, but this property has been treated only as a side effect until now since passive recovery is slow and ineffective due to the permanent portion of wearout. In this paper, we propose and demonstrate that recovery for both wearout mechanisms can be further activated and accelerated, such that the permanent portion of wearout can be fully eliminated by using in-time scheduled recovery. We show that the explored recovery properties can be utilized effectively for reducing the wearout-induced design margins, this approach introducing a new design dimension by reducing the effects of wearout in a fundamental way. A novel circuit scheme and potential implementations at the system level that can assist both BTI and recovery are also detailed in the paper. Index Terms Wearout, IoT,, BTI, Active I. WEAROUT CRISIS Wearout (aging) has become one of the dominant failure sources for VLSI systems as technology scaling is reaching the nanoscale regime [1], [2]. The transistors become more susceptible to voltage stress [3], [4], [2] due to the increased effective field due to the scaling of the thin oxide. Similarly, the shrinking geometries of metal layers render higher current densities, and the tremendous number of transistors within a compact area has resulted in higher power densities as well. Together, these lead to increased on-chip s which potentially accelerate the wearout effects [5]. Moreover, advanced technologies such as FinFET have given rise to several new wearout concerns due to new effects such as selfheating [6]. Besides the technology scaling factors, wearout issues also become more pronounced from an application perspective. In emerging applications like the Internet of Things (IoT) or wearables, where circuits usually work in near/sub-threshold for ultra low power (ULP) operation, the sensitivity of transistor current to threshold voltages is much higher than in super-threshold regimes. Also, demanded by marketing and applications, these devices usually have very strict resiliency requirements [1] and require long lifetimes. For example, some biomedical applications will require a lifetime of more than 50 years for medical implants [3]. Finally, many of these devices need to operate in extreme environmental conditions, such as high s, which, unfortunately, further accelerate wearout. Wearout phenomena affect all the parts of a system. In general, at the transistor level, Bias Temperature Instability (BTI) is one of the most prominent wearout mechanisms [2], [4]. It is characterized by the increase of the absolute value of threshold voltage V th and the reduction of the carrier mobility (µ). In the metal layers Electromigration () is the dominant reliability threat that increases the wire resistance over time (soft wearout), and ultimately can potentially break the wire (hard failure). is especially critical for power delivery networks (PDN) in modern ICs [5], [7]. These two wearout effects conspire to worsen the system metrics like performance, and can lead to timing errors at the circuit level and, ultimately, failures at the system level. The most common solution for wearout issues is adding margins at design time (pre-fabrication). Specifically, for BTI, upsizing the transistors or stretching the clock are widely used. effects are mainly addressed by design rules (e.g. metal width requirement) during the physical design phase. However, predicting the margin under dynamic workloads and changing operating conditions is very difficult and many times unfeasible, and therefore, worse-case estimation is commonly used; but this leads to conservative overdesigns, which can significantly sacrifice performance and increase area, power and cost. Adaptive postsilicon techniques appear to be more economic in terms of costs and margins by compensating for wearout during run-time. Previous work have proposed novel BTI and sensors to track and monitor wearout, and then several knobs can be adjusted correspondingly. Such knobs can be clock frequency, supply voltage or body bias [8], [9]. Although the dynamic margins enabled by these solutions can guarantee that the circuit is functioning in the presence of wearout, the wearout itself means that the power/performance metrics will be degraded and the system runs sluggish or burns more power gradually. Thus, a solution that can fundamentally fix wearout instead of compensating for its effects would be clearly preferable. It has been known that the effects of both BTI and wearout recover passively when the stress (voltage or current stress) are removed [2], [5]. Because passive recovery is very slow and unpredictable, and it can only relieve wearout, there is still a permanent portion of wearout that still keeps accumulating [10]. In this paper, we propose that recovery for both wearout mechanisms can be further activated by reversing the directions of the stress and, additionally, can also be accelerated (e.g. by increasing the ). Based on actual hardware measurement results, we demonstrate both significant improvements in the recovery rate as well as avoidance of the permanent portion of wearout. To enable the proposed recovery techniques, an on-chip implementation that is able to activate both BTI and recovery is presented. II. BACKGROUND AND PRIOR WORK A. BTI and Mechanisms Although a consensus has still not been reached regarding the exact physical mechanisms that cause wearout (especially

2 NBTI PBTI Gate Stress Traps De-Trapping Trapping Oxide (a) BTI Passive Charge Carriers Channel On-chip Power Rail Stress Current Flow Anode + e - e - e - Load Passive On-chip Power Rail No Current Cu + e - e - e - e - (b) Current Load Cathode - Fig. 1: BTI and Mechanisms: (a) BTI Stress and Passive ; (b) Stress and Passive. for BTI), it is now widely accepted that BTI is induced by traps at the Si SiO 2 interface and in the gate oxide [4], [2]. As shown in Fig. 1(a), when a transistor is under stress, traps are able to capture charge and cause a threshold voltage shift. If the transistor is in passive recovery phase (no stress), some of the interface traps can anneal slowly (known as detrapping process), and the number of occupied traps reaches a new equilibrium. Since the stress process exhibits a nonnegligible permanent component, this limits the attainable level of recovery [11]. A somewhat similar degradation also happens to the power rails as shown in Fig. 1(b); when a current flows through a metal wire the current conducting electrons produce an electron wind and lead to momentum exchange with the constituent metal atoms [12], [5]. This momentum exchange leads to a flux of the metal atoms that can create voids and cause uneven redistribution of resistance. If the voids grow gradually (known as void growth), this can cause an open circuit eventually. passive recovery happens when no current flows in the metal, the effect of the electron wind induced-stress can be relieved to a certain level, but can not be fully released [13]. B. Prior Work on BTI and Since both wearout effects are partially recoverable, the property has been previously utilized to improve the lifetime and other metrics (e.g. performance) of the system. For BTI recovery, several methods [14], [15] were proposed to rebalance the signal probabilities to maximize the passive recovery time. An alternative method was to adaptively tune the performance according to the degree of wearout so that certain blocks could start the recovery phase earlier [16]. Since passive recovery is much slower than the wearout process, recovery boost for SRAM array was introduced in [17]; the idea was to raise the gate voltages of a memory cell in order to put PMOS devices into the recovery enhancement mode. As these works focus on SRAM cell circuit and architectural level through modeling and simulation, it was still unclear how much benefit recovery boost could achieve due to lack of experimental data. Several recent works [18], [19] have studied the irreversible components of BTI at the device level. However, these works focused only on demonstrating and modeling the permanent component, thus a solution that could fundamentally repair the irreversible wearout is still missing in the field. Wafer level and transistor level experiments and theory [20] indicated that BTI recovery highly depends on ; thus these works provide physical evidence for our proposed active recovery solutions. The recovery effect of under AC stress was firstly studied in [21]; the experimental results show that the lifetime increases with the frequency. This effect was further analyzed in [22], which shows that the healing can increase the lifetime by several orders of magnitude depending on the metal used. While [13] indicates that is not fully recovered even during an opposite polarity pulse current, this means there is also an irreversible component for. [5], [12] suggest from a physics perspective that high can lead to faster and more complete recovery, but it is still simulation based, and no experimental results are presented. In this paper, we investigate how recovery can be accelerated by high and activated by reverse stress for both BTI and wearout based on actual measurements. Furthermore, we study the extent of the irreversible components and the frequency dependence of wearout and recovery. The goal is to fully alleviate or avoid both BTI and wearout through effective deep healing techniques. III. ACTIVATING RECOVERY BY REVERSING THE DIRECTIS OF BTI AND WEAROUT A. Activate the In this paper, we postulate that BTI and recovery can be further activated and accelerated beyond passive recovery, and that systems can effectively use their sleep time (e.g. intrinsic periods or scheduled time) as active healing periods essential for their overall performance, not unlike in the biological world. During sleep periods, several active recovery solutions can be applied, and they are shown in Fig. 2. In both BTI (a) and recovery cases (b), passive recovery (No. 1) is treated as the baseline case. Different from the passive recovery where only stress is removed, BTI recovery can be made active by turning off the transistor more via a negative voltage across the source and gate (No. 2). High can increase the kinetic energy for the charge carriers, thus leading to the accelerated recovery (No. 3). The joint efforts of both negative voltage and high are able to deeply rejuvenate the circuit. Similarly, for, the direction of current can be reversed to assist the electron back flow (active recovery), and high can accelerate the recovery. To validate these hypotheses, we conduct hardware testing and study the recovery behaviors for both wearout phenomena comprehensively; details are presented in the next sections. B. Experimental Setup The recovery behaviors for BTI are studied on 2-input Look Up Table (LUT)- based commercial FPGA chips fabricated in the 40nm node. The test structure is a 75-stage LUTmapped ring oscillator, the oscillation frequency change is captured during BTI wearout and recovery. For, we conduct experiments on a set of on-chip long and narrow

3 Passive 1 Active : 2 Activate the recovery Vsg = negative room Vsg = 0, room Accelerated 3 T Accelerated & Active 4 Accelerated Stress Vsg = negative high Vsg = 0, high T Active and Accelerated C1 C2 Cx: End of xth cycle (a) Activating BTI Passive I = 0, room 1 Active : 2 Activate the recovery I = negative room Accelerated 3 Accelerated & Active 4 I = negative high I = 0, high (b) Activating Fig. 2: Illustration of wearout reversing techniques for BTI and wearout: No.1 is the passive recovery case which is used as the baseline, and No. 2, 3, 4 are proposed active and accelerated recovery solutions. Probe Pads Metal Wire Technology 180nm Material Copper Thickness 0.8um Length 2.673mm Width 1.57um Resistance (@rt) Ω Fig. 4: Measurement results that show how BTI permanent components accumulate over time under different stress vs. recovery patterns (recovery condition is the same as in No. 4): Under 1 hour vs. 1 hour case, the permanent component is almost 0. Fig. 3: Die photo with the test structure for recovery: On-chip 74.8 long and narrow metal wires and their dimensions Stable even with extended recovery Void Growth 73.8 Void Nucleation Permanent Component Start Time (min) C. BTI Active and Accelerated Experimental Results The BTI experiment and measurement results presented in this part were previously published in [10], [11]. Shown in Table I is one group of measurements, where we demonstrate that 72.4% of the wearout is recovered within only 1/4 of the stress time through both high and negative voltage. The measurement results are also compared against the analytical model [10]. Our experiments further reveal that even under a high and negative voltage recovery condition (No. 4), there is still a permanent component (>27%) which cannot be recovered with the extended recovery period (much longer than 6 hours). To further fix this component, we proposed that periodic scheduled recovery (instead of one-time recovery) will be able to fully eliminate or avoid the permanent BTI wearout. This has been demonstrated successfully by our experiments, the results are shown in Fig. 4, where the same period of recovery (the same as the condition in test case No. 4) is scheduled after accelerated stress. It shows that the permanent BTI component under 1 hour stress vs. 1 hour active accelerated recovery schedule is practically 0, and this leads to full recovery. We conclude that BTI recovery can be activated and accelerated significantly, and there is a balance of stress and recovery (e.g. 1hr vs. 1hr in Fig. 4) which can bring Continuous stress after this point will potentially cause metal break 74.6 Resistance (ohm) metal wires (with probe pads) that are fabricated in 0.18µm technology. Fig. 3 shows the die photo and the dimension of the metal wire. The metal wire is fabricated with the highest metal layer (M6) of the technology in dual-damascene process. The resistance change is measured during stress and recovery phases. Temperature in both test cases is controlled by a thermal chamber which allows fluctuation of ±0.3 C. All tests are carried out on fresh devices that haven t been powered before. Accelerated Stress Accelerated and Active Passive Fig. 5: Measurement results for degradation and recovery under passive recovery (Fig.2b No. 1) and proposed recovery conditions (Fig.2b No. 4, at 230 C and ±7.96M A/cm2 ) during the void growth phase: there is still a permanent component even under accelerated and active recovery. the aged system back to almost fresh status. In Section IV, we discuss how to utilize these explored unique BTI recovery behaviors in detail. TABLE I: Summary of the BTI recovery test results for a 6-hour recovery following a 24-hour constant accelerated stress with high voltage and (%: recovery percentage; Test case number corresponds to Fig. 2a) Test Case No. 1 No. 2 No. 3 No. 4 Condition 20 Cand 0V 20 Cand -0.3V 110 Cand 0V 110 Cand -0.3V Measurement 0.66% 16.7% 28.7% 72.4% Model 1% 14.4% 29.2% 72.7% D. Active and Accelerated Experimental Results Shown in Fig. 5 is the measured -induced resistance change under accelerated stress and recovery with relatively high constant current density and elevated. During the stress phase, the results indicate that the evolution consists of two distinct phases the void nucleation phase and the void growth phase. During the nucleation phase, the -

4 Resistance (ohm) Accelerated Stress Accelerated and Active Reverse currentinduced 77.0 Full Start Time (min) Fig. 6: Measurement results for accelerated and active recovery during the early period of the void growth phase (at 230 C and ±7.96MA/cm 2 ): full recovery. Resistance (ohm) Accelerated Stress Accelerated and Active Apply recovery regularly, void nucleation slows down Metal broke Full 75.5 Overall time to failure (TTF) is extented Time (min) Fig. 7: Measurement results for scheduled periodic recovery intervals during void nucleation phase: It takes much longer for voids to nucleate, and the overall TTF is extended. induced stress increases until it hits a critical value, when voids are generated; before this point, the resistance has almost no change. Following the void nucleation phase, these generated voids start growing and lead to an increased resistance over time. Our experimental results agree with measured data in [23], [21], and are also consistent with what is predicted by recently proposed physics-based models [5], [12]. During the active recovery phase, a reverse current (with the same absolute value as in the stress phase) and elevated are applied; Fig. 5 shows that the activated recovery is much faster than that under passive recovery, and more than 75% of wearout can be recovered within 1/5 of the stress time. However there is still a lingering permanent component, which is similar behavior to what we saw for initial BTI wearout measurements. This suggests that a similar scheduling strategy as the one used in BTI recovery case can be applied to in the hope of reducing, or even eliminating the permanent component of ; Fig. 6 demonstrates exactly this. The results show that by scheduling the recovery phase in the early phase of void growth, can also be fully recovered. But the potential issue of scheduling recovery during void growth is that during recovery, there is still (reverse) current flowing through the metal, and this could lead to potential, but in the opposite direction (shown in the figure), and thus add uncertainties in terms of ultimate effects. A more economic way is to schedule the recovery periodically before voids nucleation happens; the results of this strategy are shown in Fig. 7, where multiple short recovery intervals are scheduled in the early phase of stress evolution, and this results in a delay of void nucleation for a significant amount of time (almost 3 slower compared to Fig. 5). In this way, the overall time-to-failure (TTF) can be also significantly extended. E. Summary on Experimental Results Based on extensive accelerated tests, we conclude that both BTI and recovery can be further activated and accelerated significantly, and both share common recovery behaviors the Push-Pull stress/active recovery compensation where intime scheduled periodic recovery intervals are able to fully eliminate the permanent wearout component. While BTI active recovery needs to be in an period, and active recovery happens during period when there is reverse current flowing; this opens new opportunities of scheduling both recovery over the whole lifetime span with the proper circuit solutions, which will be discussed in details in the following section. IV. IMPLENTATIS A. Assist Circuitry for Activating BTI and Since power rails suffer from single-direction DC current mostly [12], [5], we focus only on -induced effects in power delivery network in this paper. The circuit scheme presented in this section is inspired by the concept proposed in [7], [24], [25]; the difference between this work and previous solutions is that our scheme is able to support both and BTI active recovery modes, and we also discuss physical implementations and potential system level integration, which are missing in the literature. Shown in Fig. 8(a) is the schematic of the assist circuitry, which supports three modes (Normal, Active and BTI Active ). Under Normal operating mode, the load works similarly to a regular powergated system, and during Active, the current flowing through the VDD and VSS grid is reversed, and the current has the same absolute value that is guaranteed by the symmetry of the scheme, thus the load (target circuit) still functions as under Normal mode. BTI active recovery happens when the load is idle, during which VDD and VSS of the load are switched. Depending on the input values, NBTI or PBTI recovery can be activated; this is shown in Fig. 8(c). To validate the design, we implemented and simulated the assist circuitry in 28nm FD-SOI technology. A set of ring oscillators running in parallel was used as the load, the VDD/VSS grid was treated as a resistor for which we picked a reasonable value based on the published literature. Fig. 9 presents the functionality simulation under three different modes, under BTI Active mode, the VDD and VSS nodes of the load are switched as expected, and there is about 0.2V voltage droop/increase induced by the pass transistors, but the voltage is still large enough for activating BTI recovery (-0.816V is much higher than -0.3V used in our experiment in Section III-C). One of the biggest challenges of the assist circuitry is the voltage droop/increase

5 Normalized Delay VDD Grid Current (A) Voltage (V) V DD V SS (a) (b) Mode Device P1 P2 P3 P4 N1 N2 N3 N4 P1 N1 Normal P2 N2 Active VDD Grid VSS Grid BTIActive 1 N3 P3 P4 Load N4 CurrentDirection Normal Operation Active BTI Active Negative Voltage (c) V SS + V >V DD - >V DD - V th 2V th V DD - V Load VDD Load VSS Activate NBTI Fig. 8: Assist circuitry for activating BTI and recovery: (a) The main circuitry, arrows represent the current direction under different modes, V DD and V SS pins can be connected to the on-chip voltage regulator directly, or to the global power delivery network; (b) Truth table for three operating modes; (c) An example of activating NBTI recovery under BTI Active mode, for PBTI recovery, the input needs to be 0, V represents voltage droop/increase or noise. 6.00E E E E E E E E-04 Active Mode -4.00E E-04 (a) Normal Mode Time (s) 0.9 BTI Active Mode ~ 0.816V 0.6 Load VSS node Load VDD node 0.3 ~ 0.223V 0.2 V: 0.2 ~ 0.3V E E E-08 Time (s) Fig. 9: Functionality simulation in 28nm FDSOI: (a) The current direction is reversed under Active Mode, and the current value is still the same; (b) Under BTI Active Mode, load VDD and VSS values are switched Load Delay Switching Time (b) Load Size Fig. 10: Load Size vs. Performance and Switching time: Increasing the number of loads will reduce the performance as well as the switching time between modes, to compensate the degradation, header/footer transistors need to be upsized, which will further increase the area. at the load VDD/VSS nodes that are introduced by the header/footer transistors during Normal operation and active recovery mode, during which performance is critical. Another potential concern is the switching time (retention time) between modes. Since both metrics depend on the load, we explore how load size affects them. Fig. 10 shows that by increasing load size, the performance degrades linearly because of the voltage drop/increase across the footer/header transistors. Switching time also reduces with the increased load, but with a slower rate. To compensate this performance Global PDN VDD Via Tower Connect to VSS Grid M10 M9 M8 M7 M6 M5 M4 M3 M2 P2 V DD P1 C4 Bump VDD_PAD Connect to VSS Grid VDD Grid ( hazards) P4 P3 Load BTI Fig. 11: Vertical cross section of the physical implementation for the assist circuitry for VDD Grid (VSS Grid is similar): hazards happen at high current density regions, which could be caused by faster switching activities on the load logic; At the logic level, BTI hazards happen due to the continuous stress. degradation, the header/footer transistors need to be upsized, which will results in more area. This study indicates that each load will have its own optimal design point which give the optimal metrics in terms of area and other metrics. Fig. 11 gives an example of physical implementation of VDD Grid with the assist circuitry integrated (10 metal layers are assumed). It has a global PDN grid which is usually built with the top one or two metals that are wide and thick, thus being relatively robust against. Local VDD/GND grids that are close to logic and use the lower metal layers are more sensitive; this implementation will be able to protect the local grids and also enable the flexibility of designing localized assist circuitry for individual loads. The structure is very similar to a conventional power gated PDN, on top of which we add one more layer of header/footer. Since power gating techniques are widely used, this implementation makes it easy to integrate the assist circuitry into the existing design flow. B. Implications at the System Level The recent shift of architecture to heterogeneous and manycore systems significantly increases the number of integrated cores. Specialized computing resources serve for different load tasks, which also leads to different and BTI behaviors, thus requiring different recovery strategies. At the system level, localized active recovery at the core level or block level will be able to leverage the cost while rejuvenating the aged system. Fig. 12(a) illustrates a potential system with the localized active recovery techniques. Each square represents a core or logic block with local PDN and can have different recovery strategies. In the meanwhile, Dark Silicon still appears at a big challenge in these systems [26]. The dark parts of the chip usually lead to some redundant resources which have intrinsic periods, and these resources can be a single core or a subset of the cores. Since we have demonstrated that high is able to accelerated the recovery of both wearout mechanisms, and if these redundant resources (e.g. the core located in the center in the system shown in the figure) can be scheduled and allocated in such

6 (a) Logics and Local VDD/VSS Grids (Most Sensitive) (b) Time 0 Performance Global VDD Grid (Top Metal Layers) BTI Active Active BTI-induced BTI/ Sensing Wearout Short intervals C4 Bumps Global VSS Grid Assist Circuitry New Design Margin Original Lifetime Target Normal Operation Active BTI Active Heat Flow Fig. 12: System-level Implementation: (a) Illustration of On-chip PDN that supports both BTI and active recovery: Local VDD/VSS grids (Most -sensitive) are connected with global grids with the assisted circuitry; Depending on the applications, multiple recovery modes can be enabled, the generated heat from the neighboring logic can be utilized to accelerate the BTI recovery; (b) Illustration of periodic scheduled /BTI active recovery. a way that they can be healed by the generated heat from the neighboring active elements, the recovery can be further sped up. Fig. 12(b) presents an example of run-time scheduling for BTI and active recovery. In the early lifetime, since -induced stress hasn t reached the nucleation threshold, the main performance degradation will be caused mainly by BTI; novel BTI and sensors can be employed to track wearout and feed back the run-time degradation information. Short intervals of BTI active recovery periods can then be inserted to bring the chip back to the fresh status in time; during these intervals, certain states need to be in retention mode, alternatively, workload can be shifted to other redundant resources. Active period can be scheduled either from when the void nucleation happens or even earlier. Based on the measurement results presented in Section III-D, early recovery is more economic and efficient, and the system is still in operation during recovery interval, so active period can be scheduled alternately with normal operation with a small switching overhead. Overall, such a scheduling strategy can potentially fully recover both the BTI and wearout, such that the system always runs in a refreshing mode; the necessary wearout guardbands can then be significantly reduced as well. V. CCLUSIS AND FUTURE WORK As BTI and wearout effects become more critical, novel techniques that are able to mitigate them with lower overhead are highly desirable. In this paper, we propose one such candidate solution by fixing both wearout mechanisms in a fundamental way. Based on hardware measurements, we demonstrate that BTI and recovery can be activated and accelerated, and the permanent components can be effectively eliminated by optimal scheduling. To fully enable Worst-case Margin Time the utilization of the explored recovery behaviors, we present an assist circuitry scheme and discuss the implementation details at both circuit and system level. As future work, we will continue to develop the high-level compact models that capture the accurate device and circuit level BTI/ recovery information while being able to apply at the architectural and system level; this will enable an enhanced design methodology that integrates active recovery as an effective design knob for system-level design. ACKNOWLEDGMENT This work was supported in part by NSF CCF , SRC and C-FAR, one of six SRC STARnet Centers, sponsored by MARCO and DARPA. The authors would like to thank Mr. Linqiang Luo for helping with wire bonding. REFERENCES [1] R. Aitken et al., Resiliency challenges in sub-10nm technologies, in IEEE 33rd VTS. IEEE, 2015, pp [2] S. Mahapatra, Fundamentals of Bias Temperature Instability in MOS Transistors. Springer, [3] J. Franco et al., BTI reliability of ultra-thin EOT MOSFETs for subthreshold logic, Microelectronics Reliability, vol. 52, no. 9, pp , [4] Y. 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