3D-WLCSP Package Technology: Processing and Reliability Characterization

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1 3D-WLCSP Package Technology: Processing and Reliability Characterization, Paul N. Houston, Brian Lewis, Fei Xie, Ph.D., Zhaozhi Li, Ph.D.* ENGENT Inc. * Auburn University ENGENT, Inc Outline Packaging Technology Trends 3D Integration and Wafer Level Packaging Bridge 3D Wafer Level Chip Scale Packaging (3D-WLCSP) Yield and Reliability Study Test vehicles for the first and second level assembly First level assembly and reliability Second level assembly Second level reliability and failure analysis Summary and conclusions 2 ENGENT, Inc

2 Packaging Technology Trends WLP packages is the fastest growing market segment Source: Yole Development ENGENT, Inc Advanced Packaging Trends Source: Yole Development ENGENT, Inc

3 Bridging the 3D-IC Gap Wafer-level-packaging technologies are of multiple flavors and will bridge the gap between Front-end wafer and BE, assembly & test manufacturing environments Source: Yole Development ENGENT, Inc Overall Advanced Packaging Demand Wafer-level-packages have emerged as the fastest growing semiconductor packaging technology with more than 27% CAGR in units and 18% in wafers over the next 5 years to come Source: Yole Development ENGENT, Inc

4 3D-WLCSP: Die-to-Wafer Integration Three Dimensional Wafer Level Chip Scale Packaging (3D- WLCSP) technology leverages the existing infrastructures of high throughput wafer level packaging and low cost flip chip process Source: VTI Singulation ENGENT, Inc D-WLCSP: 3D Structure Two levels of interconnection 1st level interconnection: Flip chip on CSP attachment at the wafer level Silicon on silicon structure Face to face bonding through flip chip solder joint Pb free (Sn-96.5%, Ag-3%, Cu-0.5%) application Fine pitch (85 μm 200 μm), thin profile (100 μm FC thickness) 2nd level interconnection: mount of singulated 1 st level package to PCB Silicon on PCB (or other carrier) Standard CSP SMT assembly process Two levels of underfill application 1 st Level Silicon on Silicon 2 nd Level Silicon on Other Carrier ENGENT, Inc

5 Yield and Reliability Study Yield Improve first level (wafer assembly level) flip chip process yield Study second level CSP Surface Mount process yield Reliability Solder paste selection Reflow process study Underfill process evaluation for both first level and second level packages Flux/underfill compatibility study First level reliability & second level reliability qualification 9 ENGENT, Inc Test Vehicles 1 st and 2 nd Level WLCSP Assembly Quadrant 2 Quadrant 1 Flip Chip Die 2x2 WLCSP Tile Quadrant 3 Quadrant 4 WLCSP Substrate Wafer ENGENT, Inc

6 Test Vehicles 1 st and 2 nd Level WLCSP Assembly Quadrant 1 Quadrant 2 PA Flip Chip Site WLCSP Solder Balls Pitch 95um ACT Pitch 85um ENGENT, Inc Test Vehicles SEM Images Q1 Flip Chip Die Q1 Flip Chip Bumps and Pitch Q1 WLCSP Substrate WLCSP Solder Ball (Pb free, SAC 305) Flip Chip Solder Bumps (Pb free, SAC 305) Pure Copper Pad ENGENT, Inc

7 1 st and 2 nd Level Assembly Process Dip Flux First level assembly process Second level assembly process ENGENT, Inc st and 2 nd Level Assembly Process Dicing Assembly Wafer Waffle Pack Reflow Second level assembly and cross section ENGENT, Inc

8 First Level Package Qualification Testing Involved a underfill/flux compatibility study followed by a comprehensive reliability test on the best known underfill/flux combination Air to Air Thermal Cycling Testing 55 ºC to 125 ºC, 10 minutes dwell time, 10 minutes transition time 89 Q3 (5000 AATC cycles) and 28 Q2 (3000 AATC cycles) first level packages, using pump dispensed underfill 99 Q3 first level l packages, underfill jet dispensed d (4000 AATC cycles) ENGENT, Inc First Level Assembly Qual Reliability Data Cycles Quadrant Q2 0/28 1/28 7/28 12/28 15/28 21/28 Q3 0/89 0/89 0/89 0/89 0/89 0/89 0/89 1/89 1/89 1/89 Reliability Data-Underfill Pump Dispensed Cycles Quadrant Q3 0/99 0/99 0/99 0/99 0/99 0/99 0/99 0/99 Reliability Data-Underfill Jet Dispensed ENGENT, Inc

9 1 ST Level Assembly-WeibullAATC Q2 ReliaSoft's Weibull Probability - Weibull Weibull Q2 Qual Testing W2 RRX - RRM MED F=21 / S=7 β=3.5 wear-out failures Weibull life=2442 cycles Weibull model correlation coefficient = Unreliability, F(t) Time, (t) Engent Engent 3/2/ :45 ENGENT, Inc Second Level Assembly Several issues were encountered initially Reduction of solder joint voids Voids were found in the second level CSP solder joints. Too many voids or overly large voids can affect the solder joint quality. Voids reduce the area of intermetallic compound formation when the voids are formed on the solder wetting area. CSP Solder Joint Voiding ENGENT, Inc

10 Second Level Assembly Reduction of solder joint voids Literature: Longer time above melt, higher peak temperature can cause higher void percentages Two reflow profiles & two reflow environments were designed to compare the voiding activity. Longer soak time, lower time above liquidus help reducing second level CSP solder joint voids. Reflow in air environment created fewer voids than in Nitrogen environment. Reflow condition d was chosen. ENGENT, Inc Second Level Assembly Dip flux Vs. Solder paste printing Solder paste printing was chosen. Dip Flux Solder Paste Printing ENGENT, Inc

11 Second Level Assembly Co-Underfill Vs. Independent Underfill for Q1 Another issue found was the Q1 first level underfill encroachment on the CSP solder balls. The structure of Q1 created difficulty for the first level capillary underfill application and the underfill dispensed tend to flow onto the CSP balls. Yield dropped due to this issue for Q1 second level assembly. One solution was to use a smaller gauge dispense needle. It was low throughput and did not totally eliminate the possibility of underfill encroachment issue. Cross section of initial Q1 second level assembly 1 st Level Underfill Encroachment- 25 Gauge Dispense Needle Solution - 32 Gauge Dispense Needle (Low Throughput) ENGENT, Inc Second Level Assembly Co-Underfill Vs. Independent Underfill for Q1 Another solution was to use Co-underfill process: underfill 1 st and 2 nd level at the same time. Unferfill flow speed control was important during the co-underfill process. Too fast underfill flow speed could trap air in the smaller gap between een flip chip and CSP, which could cause failure during thermal cycle. Reduced the underfill flow speed by using a lower underfill process temperature. Underfill voids around 1 st level solder joints which led to failure in thermal cycle test Underfill around 1 st level solder joints using a reduced underfill flow speed ENGENT, Inc

12 Second Level Assembly Second level assembly matrix Two solder pastes were used to compare their yield and reliability performance. Three underfill methodologies were applied to study their impact on second level assembly yield and reliability. 100% Yield was achieved with the improved reflow profile for both Q1 and Q2. Condition Quadrant/Solder Paste Underfill Method Yield 1 Q1 / SP1 Co-Underfill 36/36 2 Q1 / SP2 Co-Underfill 36/36 3 Q1 / SP1 No Underfill 36/36 4 Q2 / SP1 Independent Underfill 36/36 5 Q2 / SP2 Independent Underfill 36/36 6 Q2 / SP1 No Underfill 36/36 ENGENT, Inc Second Level Reliability Second level reliability testing and results Followed JEDEC standard: JESD22-A104-B, Condition G. Thermal cycle test: -40 C~+125 C, 10 minutes dwell, 15 minutes ramp time. Failure criteria: 20% resistance change. Probed every er 100 cycles. cles Reliability failure data is shown below. Solder Paste/ Underfill Methode Air-To-Air Thermal Cycles Q1 SP1/Co-Underfill 0/36 0/36 0/36 0/36 0/36 0/36 0/36 0/36 0/36 0/36 Q1 SP2/Co-Underfill 0/36 0/36 0/36 0/36 0/36 0/36 0/36 0/36 0/36 0/36 Q1 SP1/No Underfill 0/36 0/36 0/36 2/36 8/36 18/36 25/36 33/36 36/36 36/36 Q2 SP1/Ind. Underfill 0/36 0/36 0/36 0/36 0/36 0/36 0/36 0/36 0/36 0/36 Q2 SP2/Ind. Underfill 0/36 0/36 0/36 0/36 0/36 0/36 0/36 1/36 2/36 5/36 Q2 SP1/No Underfill 0/34 0/34 0/34 2/34 5/34 8/34 12/34 22/34 26/34 26/34 Note: For Q2 SP1/ No Underfill, two parts were not be considered due to handling damage ENGENT, Inc

13 Second Level Reliability Second level reliability test and results Weibull plot for Q1 and Q2 under No Underfill condition. Under No Underfill, Q2 had a better reliability performance than Q1. ReliaSoft's Weibull Probability - Weibull Weibull Q1-SP1-No UF W2 RRX - RRM MED F=36 / S=0 Q2-SP1-No UF W2 RRX - RRM MED F=26 / S=8 Unreliability, F(t) Time, (t) Fei Xie Engent 10/14/ :43 ENGENT, Inc Second Level Failure Analysis Second level failure analysis For No Underfill Q1 and Q2, failure analysis showed the failure happened at the 2 nd level solder joints rather than 1 st level solder joints. This was caused by the 2 nd level CTE mismatch while there was no CTE mismatch between the silicon die and silicon substrate of the1st level. Crack of a failed Q1 second level package assembled on condition3 after 1000 AATC cycles ENGENT, Inc

14 Summary and Conclusions Robust yield was achieved on both fine and coarser pitch 3D-WLCSP second level assembly. An air reflow environment and the reflow profile with higher soak time, lower peak temperature t and time above liquidus id were found to reduce voids at the CSP solder joints. Co-underfill process was studied to overcome the first level underfill encroachment on Q1 package. A lower underfill process temperature could reduce the underfill voids during the co-underfill process. Two solder pastes and three different underfill methodologies were evaluated for the 3D WLCSP second level assembly. The reliability assessment on both first level and second level packages showed that 3D-WLCSP packages can be manufactured with robust yields and high thermal cycle reliability. ENGENT, Inc

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