Surface Preparation Challenges in Crystalline Silicon Photovoltaic Manufacturing

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1 Surface Preparation Challenges in Crystalline Silicon Photovoltaic Manufacturing Kristopher Davis 1,3, Andrew C. Rudack 2,3, Winston Schoenfeld 1,3 Hubert Seigneur 1,3, Joe Walters 1,3, Linda Wilson 2,3 1 Florida Solar Energy Center, 2 SEMATECH, Inc. 3 U.S. Photovoltaic Manufacturing Consortium April 23, 2014 The data contained in all slides of this presentation is protected data produced under agreement no. DE-EE with the U.S. Department of Energy and may not be published, disseminated, or disclosed to others outside the Government until five (5) years from the date the data was produced, unless express written authorization is obtained from the recipient. Upon expiration of the period of protection set forth in this Notice, the Government shall have unlimited rights in this data. This Notice shall be marked on any reproduction of this data, in whole or in part.

2 U.S. PVMC Overview CNSE UCF DOE funded (SunShot Initiative/PVMI) c-si program has ten current members actively engaged in four research projects

3 Typical Al-BSF c-si Cell and Module Process Wafer Inspection POCl 3 Diffusion PECVD SiN x Cell Test & Sort Damage Removal & Texturing PSG Removal & Edge Isolation Screen-Print FS/BS Metal & Co-Firing Module Line

4 Typical Al-BSF c-si Cell and Module Process Wafer Inspection p-type (B doped) CZ mono-crystalline Ingot/brick multi-crystal Inspection Dimensions (LxWxD) Resistivity Physical damage Cracks/chips Minority Carrier Lifetime Bulk/surface recombination Remove saw damage SiC slurry Diamond wire Etch 5-15 microns KOH/NaOH + DI rinse cracks surface defects Texturization Damage Removal & Texturing Upright pyramids Reduced reflectance Better light trapping

5 Typical Al-BSF c-si Cell and Module Process Furnace operation POCl 3 Diffusion Phosphorous Oxychloride 900 C drive-in n + emitter formed p-type wafer Forms pn-junction Thin PSG film also forms Needs removal for PECVD SiN x deposition HF-based PSG removal DI water rinse Removes PSG layer Edge isolation PSG Removal & Edge Isolation Removes n + doped regions from back and edges, which prevents shunting Doped n + emitter on wafer front remains

6 Typical Al-BSF c-si Cell and Module Process PECVD SiNx Screen-Print FS/BS Metal and Co-Firing PECVD film deposition Hydrogenated amorphous SiN x Silane + ammonia Passivation SiN x provides chemical and field effect passivation for n-type surfaces Hydrogen also provides grain boundary passivation in multi-si Cleaning before this step is critical! Anti-reflection coating Reduces surface reflectance Screen-printing of pastes Front side (Ag-based) etches through SiN x layer to contact emitter Back side (Al-based) forms BSF (reduces rear surface) Front and rear electrical contacts established Drying oven (200 C) Co-fire at 800 C Etching through ARC

7 Typical Al-BSF c-si Cell and Module Process Cell Test & Sort Module Line Cell efficiencies (%) I-V (current/voltage) Cells binned Current density at maximum power point Minimizes mismatch losses due to series connection Cells are series connected in modules solder/tabbing ribbon encapsulated Typ. EVA Glass (Front/back/both) Frame (maybe - $) Electrical J-box Module solar tester

8 Surface Preparation in SEMI SEMI PV Standards 52 PV standards written/adopted since 2009 Some PV specific Most adapted from SEMI SC Specifications None address Surface Preparation and Cleaning in PV Manufacturing Material, not process specifications

9 Surface Preparation in ITRS Granularity Specific parameter targets Multiple areas represented Front end surface preparation technology requirements are clearly defined 2013 rewrite being published published Roadmap for Moore s Law? Path and the steps

10 ITRS Table FEP11 Front End Surface Preparation Technology Requirements (2011) 10

11 Surface Preparation in ITRPV General path no granularity Surface Preparation is not specifically mentioned: Recommends no significant increase in $/cell Identifies increasing manufacturing complexity Achieve cost targets through: Materials Processes Products

12 ITRPV - Cost of Ownership Focus not to recommend detailed technical solutions Materials Silver content Frame mass Glass thickness Silicon thickness Poly-silicon $ Glass reflection Glass absorption Processes Products Ingot size/mass Diamond wire Tool uptime Throughput Yield SPC Automation Cell/module power Advanced cell n-type mono-si p-type HPmc-Si Cell efficiency Square format cell Rear contact cells Frameless modules 72-cell modules Poly-silicon quality Copper content UV Transmission Kerf loss Recombination currents Balance of Systems $

13 ITRPV - Cost of Ownership Focus Throughput Silver content Wafer thickness New ITRPV category: Too Expensive for PV

14 Advanced Cell Architectures Surface preparation becomes increasingly important: Passivation and Cleaning Defect drive-in, effect on recombination losses Contribution to efficiency Texturing/ARC Black silicon PERC, HIT, IBC require better cleaning to realize efficiency

15 Summary c-si PV Manufacturing can learn from c-si SC Manufacturing don t reinvent the wheel Surface preparation and cleaning is one area where lessons learned in SC Manufacturing can be applied to PV PV roadmap and standards update with granularity Processes can be improved and metrology implemented Data from PVMC s projects can be used to justify the effort and cost for improved surface preparation and cleaning

16 References A. Goodrich et al: A wafer-based monocrystalline silicon photovoltaic road map: Utilizing known technology improvement opportunities for further reductions in manufacturing costs. Solar Energy Materials & Solar Cells 114 (2013), SEMI Photovoltaic standards available online at < > The International Technology Roadmap for Semiconductors, 2011, is available online at < The International Technology Roadmap for Photovoltaic, 2013, is available online at < >

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