All-wet stripping process for highly implanted photoresist

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1 All-wet stripping process for highly implanted photoresist Close Executive OVERVIEW A new all-wet stripping process eliminates the need for dry plasma ashing processes in the removal of highly implanted photoresist, while maintaining low defectivity levels and high yield performance at least equivalent to the process of record. The elimination of the ashing step reduces undesirable substrate damage and material losses, improves cycle time, frees up fab floor space, and reduces capital investment and operating costs. Ron Nan, Freda Lee, Jey Hung, SMIC, Shanghai, P.R.C.; James. M.M. Chu, Jack Yuan, David Yang, FSI International, Hsinchu, Taiwan R.O.C., Jeffery W. Butterbaugh, FSI International, Chaska, MN USA In CMOS fabrication, ion implantation is used to modify the silicon substrate for various band gap engineering needs. Typically, patterned photoresist (PR) is used to define the ion implant location. After ion implantation, the patterned photoresist must be completely removed and the surface must be prepared for the next round of patterning and ion implantation. Ion implantation forms a tough layer at the surface of the photo resist, making it difficult to remove. Implanted photoresist is typically removed using dry plasma ashing, followed by wet chemical cleaning. Three loops of ion implant process isolation (well) loop, transistor channel loop, and transistor structure loop are used to build a CMOS device. The well loop alone accounts for nearly one-third of the total process layers, and can involve more than 21 steps of ion implantation and photoresist stripping in the case of 90nm logic CMOS fabrication. Thus, any reduction in cycle time multiplies quickly to provide a significant benefit in total processing time. All-wet photoresist advantages An all-wet photoresist removal process has been proposed to eliminate the potential for plasma-induced substrate damage and reduce substrate material loss [1, 2]. In addition, eliminating the plasma ash step dramatically reduces the ion implantation patterning cycle time, which can be especially important for foundry CMOS fabrication. In a high-volume production environment, adoption of such an all-wet photoresist stripping process can only be justified if it matches the final yield performance of the existing process of record (POR). In the methodology discussed in this article, therefore, all-wet post-ion implantation photoresist resist stripping qualification is

2 started from the well loop for both nmos and pmos, with multiple implantation steps. The qualification results show equivalent physical defect control and >99.9% yield performance similarity compared to the ash plus wet clean POR. Estimated benefits resulting from the adoption of this process include a >60% reduction in process cycle time and a >300% improvement in productive cleanroom space utilization. The ViPR all-wet photoresist removal solution developed by FSI is a batch spray process with point of use (POU) mixing of pre-heated (150 C) sulfuric acid and room temperature hydrogen peroxide (SPM), capable of achieving a temperature of up to 200 C on the wafer surface due to exothermic mixing. The all-wet process sequence is used for complete removal of implanted photoresist, with low defectivity. A three-stage methodology was used to systematically develop and qualify the PR all-wet process in the existing production flow: In stage one, the process condition for damage-free all-wet implanted PR stripping was determined by tuning the high temperature SPM step conditions. In stage two, the ammonium hydroxide-hydrogen peroxide (APM) step was tuned for the lowest defectivity and material loss matching. Stage two included tuning the intermittent de-ionized water rinse steps, APM ratio, final de-ionized water rinse steps, and final nitrogen spin dry. In stage three, production split-lots were used with in-line metrology to characterize any remaining physical defects and with final yield electrical measurements at the wafer acceptance test (WAT). Process results: Stages 1 and 2. First, the post-ion-implant photoresist all-wet stripping process condition was determined through short loop wafer test. The test results indicate the well loop post-ion-implant photoresist can be effectively stripped within five minutes of SPM exposure. Then, the chemical process-induced material loss behavior that takes place on polysilicon and silicon oxide are explored by blanket wafers with extended chemical exposure time.

3 Figure 1. Material loss behavior of APM conditions in PR all-wet and post-ash clean. The etch rate behavior from both the manufacturing baseline (post-ash clean) process and the all-wet stripping process are shown in Fig. 1. The etch rate data were used to set the all-wet stripping process parameters to minimize the fall-on defect control performance and to match process-induced material loss to the manufacturing baseline on current device geometries. A process using five minutes of SPM exposure followed by two minutes of APM exposure was used for all four well loops in this work. Yield lot results: Stage 3. The yield lot wafers were prepared with a 300mm standard process flow, and split at the well loop photoresist stripping steps between the existing POR (plasma ash followed by wet cleaning) and the all-wet process. After well loop ion implantation, the split wafers were merged and followed the rest of the baseline process steps to complete the CMOS fabrication. Inline defect scanning was used to measure the physical defect performance during processing, and automatic electrical probing was used in the wafer acceptance test (WAT) for final yield performance comparison over selected performance items. Yield performance benchmark To achieve a volume production comparison between the post-ion implant photoresist all-wet stripping process and current baseline (ash + post-ash clean) process, a proprietary statistical control technique, called the harmonization confidence [3], was used to benchmark the wafer final yield performance. This technique uses step-by-step identical characterization during the fabrication process and final yield performance analysis through various wafer acceptance tests (WAT),

and then employs a proprietary algorithm to evaluate the harmonization confidence and determine the similarity of process results. Figure 2. The well loop fall-on defect control result.

The physical scan determined any possible pattern damage, photoresist residue, and fall-on particle on the wafer.

4 and then employs a proprietary algorithm to evaluate the harmonization confidence and determine the similarity of process results. Figure 2. The well loop fall-on defect control result. Physical defect scanning of the yield lot wafers is done on an in-line defect scan tool after the post-ion implant photoresist stripping process on each layer. The physical scan determined any possible pattern damage, photoresist residue, and fall-on particle on the wafer. The developed damage-free post-ion implant photoresist stripping processes for both baseline and all-wet process gave the same defect performance on yield lot wafers. The fall-on particles results (Fig. 2) shows the allwet process has achieved equivalent defect performance on both nmos and pmos well loops. Yield performance index matching to POR. In final WAT, the electrical performance for the device saturation current (I dsat ), off-state current (I off ), and threshold voltage at constant current (V th ) were measured on two test keys on both nmos and pmos. The overall device yield performance comparison was made using the harmonization confidence technique, described earlier, to check the similarity of process results and to qualify device functionality. Figure 3 shows the harmonization confidence level for the all-wet stripping split compared to the POR split is >99.9% for all parameters, which is well above the targeted goal of 99%.

Compared to the POR (ash + wet), this all-wet process can reduce the photoresist stripping cycle time from 70 minutes to about 25

5 Figure 3. Wafer acceptance test result comparison by harmonization of the confidence level. Operational benefit review Process cycle time. Compared to the POR (ash + wet), this all-wet process can reduce the photoresist stripping cycle time from 70 minutes to about 25 minutes for each mask about one-third of the POR baseline cycle time. Considering the seven mask layers of the well loop, total cycle time through all-wet photoresist stripping is reduced from eight hours to about five hours, which is a >60% reduction in cycle time.

A ratio of throughput rate per unit space is used to demonstrate the difference in Fig. 4. The all-wet process cell has a ratio of 26.

6 Figure 4. Cleanroom space productivity (wafer per hour vs. space occupation). Cleanroom space occupation. Compared to the baseline process cell configuration (two ashers + one wet bench), this all-wet process cell also reduces the required cleanroom space for a given throughput requirement. A ratio of throughput rate per unit space is used to demonstrate the difference in Fig. 4. The all-wet process cell has a ratio of compared to the baseline process cell ratio of By this criterion, the all-wet process cell shows >300% increase in cleanroom space utilization. Conclusion An all-wet photoresist removal process has been developed that reduces the number of process steps and eliminates the potential for plasma-induced substrate damage, while also minimizing substrate material loss. As demonstrated in the process qualification experiment detailed in this article, this stripping methodology delivers equivalent defect control and comparable yield control (>99.9%) when compared with the current manufacturing baseline process (plasma ashing followed by wet clean). In addition, the all-wet process demonstrates the capability to reduce the ion implantation cycle time by >60%, while delivering a >300% improvement in cleanroom space utilization. References

7 1. K. K. Christenson, J. W. Butterbaugh, T. J. Wagener, N. Pyo Lee, B. Schwab, M. Fussy, J. Diedrick, Solid State Phenomena, 134, p. 109 (2008). 2. B. K. Kirkpatrick, J. J. Chambers, S. L. Prins, D. J. Riley, W. Xiong, X. Wang, Solid State Phenomena, 145, p. 245 (2009). 3. U.S. Patent , "Method and System for Processing Stability of Semiconductor Devices," SMIC, (2006). Biographies Ron Nan received his BS in automation from Shanghai U., and MS in microelectronics from Fudan U., and is process section manager at SMIC F-8 18, Zhangjiang Rd. Pudong New Area, Shanghai , P.R.C; ph.: ext 18213; Freda Li received her MS in materials science and BS in materials science from Sichuan U., and is a process engineer wet clean and CMP at SMIC. Jey Jey Hung received his ME in chemical engineering from Taiwan U., and is an assistant director at SMIC. James M.M. Chu received his MS in system engineering from National Cheng Kung U., Taiwan, and is currently a PhD candidate at the university; he is a field application manager at FSI International, Hsinchu, Taiwan R.O.C. Jack Yuan received his BS degree in chemistry science from Lanzhou U. and Masters in material science from Shanghai U., and is an application engineer at FSI International, Hsinchu, Taiwan R.O.C. David Yang received his MS in atomospheric physics from National U., Taiwan, and is a senior application engineer at FSI International, Hsinchu, Taiwan R.O.C. Jeffery W. Butterbaugh received his PhD in chemical engineering from MIT, and is chief technologist at FSI International, Chaska, MN USA. More Solid State Technology Current Issue Articles More Solid State Technology Archives Issue Articles To access this Article, go to:

Chapter 2 Problems. The CMOS technology we need to realize is shown below, from Figure 1-34 in the text. S P + N P + N WELL P +

Chapter 2 Problems. The CMOS technology we need to realize is shown below, from Figure 1-34 in the text. S P + N P + N WELL P + Chapter 2 roblems 2.1 Sketch a process flow that would result in the structure shown in Figure 1-34 by drawing a series of drawings similar to those in this chapter. You only need to describe the flow