Effect of Underfill Entrapment on the Reliability of Flip-Chip Solder Joint

Transcription

1 Y. C. Chan M. O. Alam K. C. Hung H. Lu C. Bailey EPA Centre, Department of Electronic Engineering, City University of Hong Kong, Hong Kong, China; School of Computing and Mathematical Science, The University of Greenwich, Greenwich, UK Effect of Underfill Entrapment on the Reliability of Flip-Chip Solder Joint The application of underfill materials to fill up the room between the chip and substrate is known to substantially improve the thermal fatigue life of flip chip solder joints. Nowadays, no-flow underfill materials are gaining much interest over traditional underfill as the application and curing of this type of underfill can be undertaken before and during the reflow process and thus aiding high volume throughput. However, there is always a potential chance of entrapping no-flow underfill in the solder joints. This work, attempts to find out the extent of underfill entrapment in the solder joints and its reliability effect on the flip chip packages. Some unavoidable underfill entrapments at the edges of the joint between solder bumps and substrate pads are found for certain solder joints whatever bonding conditions are applied. It is interesting to report for the first time that partial underfill entrapment at the edges of the solder joint seems to have no adverse effect on the fatigue lifetime of the samples since most of the first solder joint failure in the no-flow flip chip samples during thermal cycling are not at the site of solder interconnection with underfill entrapment. Our modeling results show good agreement with the experiment that shows underfill entrapment can actually increase the fatigue lifetime of the no-flow flip chip package. DOI: / Introduction In the near future, conventional leaded packages are not expected to be able to handle high pin count integrated circuits. Consequently, the use of area array packaging technology is expected to increase dramatically. Flip chip technology is ideally placed to meet the demands for higher density, greater performance, and lighter weight products by the electronics industry. At present, state-of-the-art flip chip assembly technology cannot match the high throughputs of existing surface mounting technology SMT lines because the current method for manufacture of flip chip assemblies is time consuming. The traditional flip chip assembly process is to dispense flux, pick and place the die onto the substrate, and perform solder reflow. Only after this may the underfill be dispensed and cured. The processes that increase production time are 1 cleaning of the flux residues, 2 underfilling of the chip, and 3 the time needed to cure the underfill material. Underfilling is achieved by dispensing the liquid underfill along dual adjacent edges of the chip and allowing it to flow under the chip by capillary action. The flow time may be long for high density area array chips with a risk of void formation. Flux residues may impede flow and there are linked constraints on the stand-off gap between chip and substrate and the underfill flow properties. To eliminate the process bottlenecks associated with flip chip assembly outlined above, the so-called no-flow underfill process has recently been invented 1 9 that enables underfill addition and cure to occur before and during the reflow process. The noflow underfill also has the self-fluxing ability to remove the metal oxide and prevent the melted solder from reoxidation during reflow 2. To ensure that solder interconnects connect to the pads on the substrate, these underfill materials do not contain filler material and hence have a higher coefficient of thermal expansion CTE than those used in the traditional capillary flow process. This may lead to low package reliability and thus create a technical barrier in applying no-flow underfill technology 3. Considering the real manufacturing application of no-flow underfill technology, researchers and scientists try to formulate no-flow Manuscript received May 2003; final revision, April Review conducted by: B. Sammakia. underfill materials with CTE as low as possible. Wong s group 4 has incorporated the inorganic silica fillers into the no-flow underfill epoxy system. Although the CTE of the pre-filled versions of no-flow underfill materials can be achieved down to 30 ppm/ C, the incorporation of the inorganic fillers may hinder the solder joint interconnection formation and limit the wetting of the solder bump onto the substrate pad 4.We 5 have studied the reliability of the BGA assembly using no-flow underfill by thermal shock and bending cycle. The experimental results have shown that the no-flow underfill can greatly enhance the mechanical fatigue lifetime, but cannot improve the thermal reliability of BGA assembly because the CTE of no-flow underfill is still too great. In addition, another technical barrier in applying no-flow underfill technology is the underfill entrapment between solder bumps and substrate pads due to the poor wetting of solder to the pad and the non-uniformity of solder bump height, thus affecting the integrity of solder joint interconnection or ruining the entire package 6. No flow underfill could be entrapped partially or fully between the solder bump and substrate pad. Through electrical interconnection test, open solder joint is sorted out easily. However, the solder joint which is formed with partially entrapped underfill materials could not be sorted out through electrical measurement method during the process flow. This type of partial entrapment of the underfill materials may remain in the packages. This is why, it is important to know the reliability issues of such partial entrapment of underfill materials in flip-chip packaging. No work has been done before on such underfill entrapment which passes electrical continuity test but have not soldered properly. In this work we studied how the entrapment of the no-flow underfill materials effect the reliability of the flip-chip packages. We applied no-flow underfills into the flip chip bonding between solders and electroless Ni pads and investigated the integrity of the reflowed solder interconnects. The reliability of these types of flip chip packages under thermal cycling was conducted. Computational modeling was performed to explain the experimental results. Journal of Electronic Packaging Copyright 2004 by ASME DECEMBER 2004, Vol. 126 Õ 541

2 Table 1 Properties of the no-flow underfill materials Property NF1 NF2 Glass transition temperature Tg ( C) CTE (10 6 / C) Storage 25 C GPa Viscosity Pa.s Moisture absorption % Experimentation 2.1 Fabrication of Substrates With Electroless Ni Pad PCB substrates are fabricated by electroless Ni-P plating on the Cu pad. Immersion gold Au plating was immediately layered on top of the electroless Ni-P to avoid oxidation of the nickel surface. In order to maintain close to the optimum concentration of the plating solution and ensure the optimum deposit quality, a complete automatic titration setup was used to check and monitor the content, the ph value and the plating temperature, in the plating tanks. Fig. 2 Thermal shock conditions 2.2 Samples Preparation for No-Flow Flip-Chip Bonding The samples used in this study were the dummy flip-chip package in which the bump diameter and pitch were 190 and 457 m respectively, and the solder bump material was eutectic 63Sn/ 37Pb. The test board for flip chip assembly composed of FR-4 PCB. The substrate metallization was copper plated with electroless nickel and gold flash on top. The diameter of the test board pads was 150 m. A daisy chain design was used to measure and test the electrical continuity through all solder-joints. There were two types of samples studied for two different no-flow underfill materials NF1 and NF2. The detailed properties of the materials are summarized in Table 1. At first, the test boards were baked at 150 C for 1 hour before assembly to remove moisture. The substrate and chip were placed and aligned in a Karl Suss Manual flip chip bonder. Accurate volume of no-flow underfill was then dispensed by syringe onto the bond site to form a dome-shape using a LY9801D dispensing machine. The chip was then placed onto the substrate. The bonded samples were then reflowed using a 5-zone air convection oven BTU VIP-70N in a compressed air environment. The timeresolved temperature during reflow between the component and the test board was measured using a wireless profiler Super M.O.L.E, E /10. Both no-flow underfills NF1 and NF2 were cured during the modified reflow profile, which is shown in Fig. 1. No additional post cure was required. After reflow, the no-flow flip chip assemblies were checked by electrical measurement and inspected with X-ray inspection system and Scanning Acoustic Microscope SAM. 2.3 Thermal Shock Test. In order to investigate the effect of no-flow underfill entrapment on the fatigue failure, samples of NF1 and NF2 were subjected to thermal shock through 1000 cycles, which was performed in an air-to-air condition in a TABAI TSA-70L thermal shock chamber. The temperature range of thermal cycling was from 25 to 125 C and samples were held at each temperature for 15 minutes as shown in Fig. 2. The electrical continuity of the no-flow flip chip samples was monitored throughout the reliability test. The detection of first open solder joints through electrical interruption was used as the failure criteria 10. The number of cycles at solder joint failure was recorded. 2.4 Cross-Sectional Study of the Solder Joint. All the failed samples were mounted in epoxy and then ground and polished carefully to find out the open/defective joint as well as the joints where some no-flow underfill has been entrapped. Optical microscopy was used as a primary tool after each successive polishing. Scanning electron microscopy SEM was used to identify any crack in the solder joints. Fig. 1 Measured reflow profile for no-flow flip chip package 3 Results and Discussion 3.1 Flip Chip Bonding Using No-Flow Underfills. The challenge of implementation of no-flow underfill before reflow is that, adjustment of the bonding or placing force of the head of the flip-chip bonder is such that good contact of solder bump to the substrate pad and smooth compressive flow of no-flow underfill can be obtained. It is because too little force will lead to no contact between solder bump and substrate pad but too large force will cause serious deformation of solder bump, and thus trapping of thick layer of no-flow underfill may occur after reflow see Fig. 3. This thick layer of underfill entrapment may hinder the solder joint interconnection formation and limit the wetting of the solder bump onto the substrate pad. This type of underfill entrapments can be easily detected through electrical continuity test. Figure 4 shows the cross-section of the no-flow flip-chip solder joint, which presents good bonding between solder bump and substrate pad. Clearly in this case there appears to be no underfill trapped at the interface of the solder joint. We can say that this joint is sound both from an electrical and mechanical point of view. However, in our experimental results see Fig. 5, even though gold plated electroless Ni substrate and good bonding force for placing the chip have been selected, we still found some solder 542 Õ Vol. 126, DECEMBER 2004 Transactions of the ASME

3 Fig. 3 Optical micrograph showing trapping of thick layer of no-flow underfill after reflow joints with different degrees of underfill entrapment. The possible reason may be due to the non-uniformity of solder bump height. Figure 6 shows the schematic diagram of no-flow flip-chip bonding with a perfect interconnection, b underfill entrapment at one edge, both edges or surrounding the periphery of the joint, and c no interconnection due to occurrence of underfill layer between solder and pad. Normally, we can get good no-flow flipchip bonding in our samples, which is defined as no open of solder joints using electrical measurement. That means we may get solder joint interconnections with cases a and b in Fig. 6 as sound joints from the electrical test. One interesting question will be immediately asked does the underfill entrapment affect the reliability of the no-flow flip-chip package after thermal cycling? 3.2 Thermal Cycling for No-Flow Flip-Chip Samples Before the thermal shock test, the samples were inspected using SAM to see whether there were voids inside the underfill layer, especially the location of any voids near the solder joint. It was found that most of the no-flow flip-chip samples for both NF1 and NF2 showed no voids inside the underfill layer. Only a few Fig. 5 Optical micrograph showing the cross-section of the no-flow flip chip solder joint, which presents a good solder joint interconnection but with underfill entrapment between solder and substrate pad samples contain voids white spots inside the underfill layer See Fig. 7. Voids that appeared inside the underfill layer in our samples were quite small and located at the center but not near the solder joints. Normally, this type of void should not affect the long-term reliability. The number of cycles to failure for NF1 and NF2 samples are summarized in Table 2. We also present the works done by Wong s group W1, W2 & W3 in Table 2 for comparison 3. It is found that the increase in CTE will lead to a decrease in cycles to failure. The underfill materials surrounding the solder bumps help to relieve strains and stress occurring in the joint. In this study, we are concentrated on the underfill entrapment into the solder joint of flip-chip package. To find the failed solder joint after the thermal cycle test and also to locate underfill entrapped solder joints, we have carried out a tedious cross-sectional study of the solder joint from one side of the flip-chip to the other side. Surprisingly, our experimental results show that most of the first solder joint failure in the no-flow flip chip samples during thermal cycling are not at the site of solder interconnection with underfill entrapment although we found such defective joints at the outer most solder joints i.e. corner joints where maximum stress occurs. Lack of 100% metal-to-metal contact at the solder joint was supposed to fail easily. However, in reality it has not been found Fig. 4 Optical micrograph showing the cross-section of the no-flow flip chip solder joint, which presents a good bonding between solder bump and substrate pad Fig. 6 Schematic diagram of no-flow flip chip bonding with a perfect interconnection, b underfill entrapment at one edge, both edges or surrounding the periphery of the joint, and c no interconnection due to occurrence of underfill layer between solder and pad Journal of Electronic Packaging DECEMBER 2004, Vol. 126 Õ 543

4 Fig. 8 A model with trapped underfill. The center is filled with solder and therefore the joint still has good electric connection. Fig. 7 SAM picture of no-flow flip chip sample. Few voids white spots inside the underfill layer are observed. in any of the joints of our samples either for NF1 or NF2 underfill materials. So, one may ask whether underfill entrapment will enhance the fatigue resistance of the solder joint which may increase the lifetime of the no-flow flip chip package. In order to clarify this, we used computational modeling in conjunction with experiments to help identify the phenomena that would be too costly and even impossible to identify by experiments alone. Especially in this study of underfill entrapment, it is quite difficult to obtain systematic results of the underfill entrapment effect since the occurrence of this entrapment is random and the degree of underfill entrapment during no-flow flip chip assembly cannot be easily controlled. 3.3 Modeling for Underfill Entrapment. A threedimensional model of this package has been developed which includes details of the pads on both the substrate and die. The PHYSICA 11 multiphysics modeling framework has been used in this analysis to predict the stress-strain profiles across the package during a thermal cycle. The detailed three-dimensional model has captured all of the important local features around the solder joint. This broad parametric study over Young s Modulus E and CTE of the underfill has been used in providing fatigue lifetime data for the flip-chip component under cyclic thermal loading. During a thermal cycle the eutectic Sn-Pb solder will be operating at high homologous temperature. In such circumstances the major deformation phenomenon is time dependent creep that occurs within the solder during the thermal cycle. Each thermal cycle consists of four stage: temperature increase (125 C), dwell at this temperature, temperature decrease ( 25), dwell at this temperature. Each stage in the cycle lasts for 15 minutes, where the solder materials has time to deform and stress. To model creep deformation of solder on this parametric study, a sinh creep law has been applied 12. In this study the accumulated effective creep strain in the solder connections is analyzed and then used as the damage indicator in the Coffin-Manson empirical relationship to predict number of cycles to failure. To simulate the effect of underfill entrapment at the edges of the solder joint, a most universal model is considered for this study to cover most of the features found in our experiments. Figure 8 shows this model of a solder joint with entrapped underfill. The entrapped underfill has a doughnut shape with the center still filled with solder and therefore the joint still has good electric connection. In our modeling results, it is interesting to find that the fa- Table 2 Material properties and thermal shock cycles to failure of different no-flow underfill materials Material Tg CTE Cycles to failure NF NF W W W3 # # Addition of filler inside the no-flow underfil Fig. 9 Accumulated creep strain distribution in solder a no trapped underfill and b with trapped underfill. Only solder material is shown. 544 Õ Vol. 126, DECEMBER 2004 Transactions of the ASME

5 tigue lifetimes of this model are 14% higher than that of the model without trapped underfill. This phenomenon can be explained if we examine the creep strain distribution as shown in Fig. 9. In Fig. 9 a, the maximum darkest region is clearly shown to be close to the pad. In Fig. 9b, the creep strain distribution for model with underfill entrapment is shown. Clearly we can see that the location and magnitude being lower of creep strain has changed. The entrapped underfill materials act as cushion materials, which absorb thermal shock and nullify the creep strain. Therefore, due to a small amount of underfill entrapment we expect an increase in fatigue lifetime of the no-flow flip chip package. 4 Conclusions Partial underfill entrapment in the solder joint for flip chip packages could not be detected during an electrical continuity test. So, from reliability concerns it might be a serious concern whether this partial underfill entrapment at the edges of the solder joint nucleates the fracture during thermal cycling. In this paper, we attempted to find the effect of such underfill entrapment on the reliability of the flip chip package. Surprisingly, it was found that underfill entrapment seems to have no adverse effect on the fatigue lifetime of the samples since most of the first solder joint failure in the no-flow flip-chip samples during thermal cycling are not at the site of solder interconnection with underfill entrapment. We have done both experiments and modelling work to reach such a conclusion. From the modeling work of the sound solder joint, high creep strain was found close to the substrate pad and also near edges of the solder joint. However, if underfill entrapped into the edges of the solder joint, creep strain distribution of the remaining solder joint changes and severity of the creep strain reduces. We proposed that entrapped underfill act as a cushion materials which absorb the thermal shock. Hence our modeling results show that underfill entrapment can actually increase the number of cycles to failure. Acknowledgments The authors would like to acknowledge the financial support provided by Innovation and Technology Commission Innovation and Technology Fund Ref. ITS/182/00, City University of Hong Kong Project no and RGC Funding for Co-operative Research Centres CRC Project no The authors also thank C.P. Wong of Georgia Institute of Technology, Jordan Au of Emerson & Cuming and Dicky Wong of PAM Ltd for providing no-flow underfill materials. References 1 Wong, C. P., Shi, S., and Jefferson G., 1997, High Performance Low Cost Underfills for Flip Chip Applications, IEEE 47 th ECTC Proceedings, San Diego, California. 2 Shi, S. H., and Wong, C. P., 1999, Study of the Fluxing Agent Effects on the Properties of No-Flow Underfill Materials for Flip-Chip Applications, IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 22 2, pp Shi, S. H., Yao, Q., Qu, J., and Wong, C. P., 2000, Study on the Correlation of Flip-Chip Reliability With Mechanical Properties of No-Flow Underfill Materials, International Symposium on Advanced Packaging Materials, pp Fan, L. H., Shi, S. H., and Wong, C. P., 2000, Incorporation of Inorganic Filler into the No-Flow Underfill Material for Flip-Chip Application, International Symposium on Advanced Packaging Materials, pp Tu, P. L., Chan, Y. C., and Hung, K. C., 2001, Reliability of the MicroBGA Assembly Using No-Flow Underfill, Microelectronics Reliability, Microelectron. Reliab., 41 12, pp Tu, P. L., 2001, Reliability Studies of Micro Ball Grind Array Assembly, Ph. D. thesis, City University of Hong Kong, pp Jianmin, Q., and Wong, C. P., 2002, Effective Elastic Modulus of Underfill Material for Flip-Chip Applications, IEEE Trans. Compon., Packag. Manuf. Technol., Part A, 25 1, pp Zhuqing, Z., and Wong, C. P., 2001, A Novel Approach to Incorporate Silica Filler into No-Flow Underfill, 2001 Int l Symposium on Electronic Materials and Packaging, pp Dutta, I., Gopinath, A., and Marshall, C., 2002, Underfill Constraint Effects during Thermomechanical Cycling of Flip-Chip Solder Joints, Journal of Electronic Materials, 31 4, pp Chan, Y. C., Tu, P. L., Tang, C. W., Hung, K. C., and Lai, J. K. L., 2001, Reliability Studies of BGA Solder Joints Effect of Ni-Sn Intermetallic Compound, IEEE Trans. Compon., Packag. Manuf. Technol., Part B, 24 1, pp PHYSICA, Multi-Physics Ltd, London. 12 Darveaux, R., and Banerji, K., 1995, Reliability of PBGA Assembly, Ball Grid Array Technology, McGraw-Hill, pp Popelar, S. F., 1998 A Parametric Study of Flip Chip Reliability Based on Solder Fatigue Modeling, International Electronics Manufacturing Technology Symposium, pp Bailey, C., Lu, H., and Wheeler, D., 2002, Computational Modeling Techniques for Reliability of Electronic Components on Printed Circuit Boards, Appl. Numer. Math., , pp Journal of Electronic Packaging DECEMBER 2004, Vol. 126 Õ 545