THREE-DIMENSIONAL IC provides a promising solution

Transcription

1 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 12, NO. 2, JUNE A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application Cheng-Ta Ko, Zhi-Cheng Hsiao, Yao-Jen Chang, Peng-Shu Chen, Yu-Jiau Hwang, Huan-Chun Fu, Jui-Hsiung Huang, Chia-Wen Chiang, Shyh-Shyuan Sheu, Yu-Hua Chen, Wei-Chung Lo, and Kuan-Neng Chen, Senior Member, IEEE Abstract Thin wafer/chip stacking with vertical interconnect by a Cu through-silicon via (TSV) and a Cu/Sn microjoint is one of the candidates for 3-D integration. The insertion loss of the two-chip stack was evaluated with different TSV pitches, microbump diameters, and chip thicknesses to realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnection. In addition, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key technologies, including TSV interconnection, microbumping, hybrid bonding, wafer thinning, and backside RDL formation, were well developed and integrated to realize 3-D integration. This paper presents a complete study of the structure design, the process condition, and the electrical and reliability assessment of the wafer-level 3-D integration scheme. This 3-D integration scheme with excellent electrical performance and reliability provides a promising solution for 3-D memory application. Index Terms Hybrid bonding, wafer level, 3-D IC, 3-D integration. I. INTRODUCTION THREE-DIMENSIONAL IC provides a promising solution to extend and get beyond the Moore s law (more than Manuscript received September 26, 2011; revised April 2, 2012; accepted April 6, Date of publication April 18, 2012; date of current version June 6, This work was supported in part by the Ministry of Education in Taiwan under the ATU Program, by the National Science Council through Grant NSC E , and by the Ministry of Economic Affairs in Taiwan. C.-T. Ko is with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, and also with the Electronics and Technology Research Institute, Hsinchu 31040, Taiwan. Z.-C. Hsiao, P.-S. Chen, Y.-J. Hwang, H.-C. Fu, J.-H. Huang, C.-W. Chiang, Y.-H. Chen, and W.-C. Lo are with the Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute, Hsinchu 31040, Taiwan. Y.-J. Chang and K.-N. Chen are with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan ( knchen@mail.nctu.edu.tw). S.-S. Sheu is with the Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute, Hsinchu 31040, Taiwan, and also with the Department of Electrical Engineering, National Central University, Zhongli 32001, Taiwan. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TDMR Moore) as the next generation semiconductor technology. It possesses lots of advantages including small form factor, high performance, low power consumption, potentially low cost, easy for high density heterogeneous integration, and could be widely used for product applications such as CIS, LED, MEMS, memory stacking, logic and memory stacking, and high performance chips stacking, etc. For realization, various 3-D integration platforms have been addressed and developed in the worldwide companies and research institutes [1] [4]. The key technologies, including through-silicon via (TSV), thin wafer handling, wafer bonding and interconnection are necessary to carry out these 3-D platforms. Vertical interconnection by Cu TSV combination with Cu/Sn microjoint is an attractive option for 3-D integration [5] [10]. However, this approach is usually limited by chip-to-chip (C2C) or chip-to-wafer (C2W) bonding scheme followed by underfill filling for reliability enhancement. Considering the mass production in future, a wafer-level 3-D integration platform with simplified process flow is essential to be developed to increase the through-put and lower the cost. In this paper, a wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding is demonstrated. The microbumps are adopted for inter-wafer connection to achieve vertical interconnection with TSVs. The strength and reliability of stacked structures are effectively increased with the adhesive sealing around and serving reinforcement of mechanical stability to endure the severe wafer thinning and follow-up processes. With this 3-D integration scheme and bonding approach, there are no demands for thin wafer handling technique with carrier temporary bonding and de-bonding. It does not need to meet the challenge of ultra-fine gap underfill filling and flux cleaning. Therefore, the process flow could be simplified with cost reduction effectively. In addition, different from the high bonding temperature requirement on Cu Cu thermo-compression bond, Cu/Sn and BCB hybrid bonding can be performed under 250 C with lower force, which decreases the induced thermo-stress and possible damage, and satisfies low thermal budget requirement on most devices. The structure design, complete process flow and conditions, assessment results of electrical performance and reliability of the 3-D integration scheme are disclosed in the paper /$ IEEE

2 210 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 12, NO. 2, JUNE 2012 Fig. 2. TSV insertion loss behavior on different zone. (Pitch: 20 μm). Fig. 1. Two-chip stack structure with vertical interconnect by Cu TSV and Cu/Sn microjoint for insertion loss simulation analysis: (a) side view, (b) top view. II. EVALUATION OF CU TSV AND MICROJOINT INTERCONNECT Thin chip stacking with vertical interconnection by Cu TSV and Cu/Sn microjoint is one of the candidates for 3-D integration. To realize the signal transmission effects in high-speed digital signaling via TSV and microjoint interconnect in 3-D IC, the insertion loss of two-chip stack, as shown in Fig. 1, was evaluated with different TSV pitches, microbump diameters, and chip thicknesses. In this paper, 3-D field solver HFSS was used to simulate the stacked structure. The lump port was set between signal and ground, and the setting silicon size is 1 mm 1 mm. The microbump Cu/Sn ratio is 2:3, with the setting resistivity Ω. m and Ω. m respectively for Cu and Sn. A. TSV Insertion Loss Behavior on Different Zone TSV has to be electrically isolated from the silicon substrate with a thin silicon dioxide film which causes a capacitive effect. Therefore, high-speed digital I/O signals suffer from the capacitive loading as well as the frequency-dependent loss from the lossy silicon substrate, which results in degradation of the eye opening and timing jitter in the high-speed digital system [11]. Fig. 2 presents TSV insertion loss behavior dominated by TSV capacitance, silicon conductivity, and TSV inductance, respectively in low, middle, and high frequency region. The silicon dioxide, silicon conductivity, and TSV pitch effect frequency range for insertion loss were studied previously [11], [12]. As the TSV thin silicon dioxide film thickness decreases, Fig. 3. Simulation result of TSV pitch effect on insertion loss (TSV pitch = 20 μm 60 μm). the insertion loss increases in low frequency region due to the capacitive effect between signal via and ground via increasing. As the silicon substrate conductivity increases, the insertion loss increases in middle frequency region because the resistance between signal via and ground via decreases. As the TSV pitch increases, the insertion loss increases in high frequency region. B. Insertion Loss versus Pitch Fig. 3 presents the insertion loss of the stacked structure shown in Fig. 1 with different TSV pitches. As the pitch decreases, the silicon substrate capacitance and conductance between the signal and ground TSVs increase, which results in the increased insertion loss [12]. Therefore, as the TSV pitch increases from 20 μm to 60 μm, the insertion loss improves in middle frequency region ranging from 1 GHz to 8 GHz

3 KO et al.: WAFER-LEVEL THREE-DIMENSIONAL INTEGRATION SCHEME WITH Cu TSVs 211 Fig. 4. Simulation result of microbump diameter effect on insertion loss (microbump diameter = 10μm 18 μm). as shown in Fig. 3. However, as the pitch increases in high frequency region ranging from 8 GHz to 20 GHz, the insertion loss drops quickly due to the increase of TSV loop inductance. Therefore, the pitch of TSV is an important design parameter when system works on higher frequency. Fig. 5. Simulation result of chip thickness effect on insertion loss (chip thickness =40μm 60μm). C. Insertion Loss versus Microbump Dia. (Fixed TSV Pitch) Microbump electrical characteristic affects the electrical performance of 3-D integration system. Fig. 4 shows the simulation result of microbump diameter effect on insertion loss. As the TSV pitch fixed (20 μm), although the microbump diameter increases, the insertion loss does not significantly improve because the microbump is surrounded by the lossless BCB other than the lossy silicon substrate. In addition, the fat and short structure of microbump would be the secondary reason as it is still very conductive. D. Insertion Loss versus Chip Thickness In 3-D integration scheme, chip/wafer thickness directly determines the TSV height which affects the TSV electrical performance in high-speed digital transmission. Fig. 5 shows the simulation result of chip thickness effect on insertion loss (microbump diameter: 10 μm, pitch: 20 μm). As the chip thickness increases, the height and impedance both increase. Therefore, the insertion loss increases. However, the insertion loss does not change significantly in low frequency region due to the silicon dioxide film thickness in TSV unchanged. III. STRUCTURE DESIGN AND 3-D INTEGRATION DEMONSTRATION In this paper, Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding scheme was designed to demonstrate Fig. 6. Structure design and schematic process flow of wafer-level 3-D integration scheme. a) Cu/Sn microbump formation on top (with TSV) and bottom wafer; (b) BCB covering and patterning; (c) Hybrid bonding; (d) Thinning and backsides RDL. a wafer-level 3-D integration platform. Several kinds of TSV diameters with different microbump sizes and pitches were designed in the test vehicle. Fig. 6 shows the structure design and schematic process flow. Cu/Sn microbumps were fabricated on bottom wafer and Cu TSVs of top wafer, respectively, as shown in Fig. 6(a). In Fig. 6(b), BCB was subsequently spincoated and lithographed to expose the microbumps and form the hybrid scheme. Fig. 6(c) shows that two wafers were then aligned and hybrid bonded at 250 C. After bonding, top wafer was thinned to expose TSVs and backside RDL formation with bottom wafer support, as shown in Fig. 6(d). If required, a third wafer (or more) can be further added to achieve multi-layer 3-D structures.

4 212 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 12, NO. 2, JUNE 2012 Fig. 8. Formation of 10 μm Cu/Sn microbump in 20 μm pitch. Fig. 7. Fabrication of 5 μm size/50 μm depth TSV in 20 μm pitch performed by (a) DRIE formation with scallop less than 100 nm, and (b) followed by ECP-Cu filling without any void and seam inside. Several key techniques have to be well developed and integrated to perform the 3-D integration scheme, including TSV interconnection, microbumping, hybrid bonding, wafer thinning and backside RDL formation. The section below discloses the process conditions and results in detail. A. TSV Interconnection By the definition of photoresist as etching mask, TSVs were formed by deep reactive ion etch (DRIE). The well-known Bosch process [13] was applied where SF 6 was used in etching cycle whereas C 4 F 8 in passivation cycle to achieve anisotropic etch of silicon. With optimization of the alternative cycle time, the etch rate could be optimized with minimum sidewall scallop. Fig. 7(a) presents 5 μm size/50 μm depth TSV formation with scallop about 92 nm only. After DRIE, the SPS-200 and EKC chemicals were used to remove the etching mask and polymer generated during DRIE process. The silicon dioxide and TiN/Cu were subsequently deposited on the via surface as dielectric and barrier/seed layers, respectively. With the smaller sidewall scallop, it facilitates the continuity of the deposition layers and then smoothes the ECP-Cu filling process. TSV filling was performed by using Raider-M CFD3 plating tool from AMAT. Fig. 7(b) presents 5 μm size/50 μm depth TSV in 20 μm pitch fully filled with ECP-Cu without any void and seam inside. After TSV filling, the surface Cu overburden and TiN barrier were removed by chemical mechanical polishing (CMP) to complete the TSV exposure for front side interconnection. B. Microbumping In this research, Cu/Sn microjoints were employed for vertical interconnect between stacked wafers. Via in pad design was adopted and fine pitch microbumping technique was developed to integrate with TSV to achieve high density interconnection. After Cu pad/trace and oxide passivation formation, the Cu/Sn Fig. 9. (a) BCB covering and patterning around Cu/Sn microbumps without residue on bumps; (b) Cu/Sn microbump and BCB hybrid bonding conditions were optimized to perform the bonding integrity. microbumps were fabricated on the pads by electroplating technique. An adequate barrier and seed layer thickness was applied to minimize the undercut after etching but keep good wafer-level plating uniformity. Fig. 8 demonstrates the Cu/Sn microbumps formation with 10 μm size in 20 μm pitch. With the precise control, the undercut less than 1 μm and bump height uniformity less than 10% could be achieved. In addition, good bumping uniformity ensures the follow-up wafer bonding uniformity. C. Hybrid Bonding As aforementioned, Cu/Sn microbump and BCB adhesive hybrid scheme was applied for wafer-to-wafer (W2W) bonding to achieve the intrinsic interconnection and adhesive sealing simultaneously. The photosensitive BCB with excellent mechanical resistance and bonding properties had been qualified to be compatible with solder bump (and even Cu Cu) for hybrid integration, and could be performed by 250 C low temperature bonding [14]. After Cu/Sn microbump formation, BCB was spin-coated and UV-lithographed to expose the microbumps to form the hybrid scheme as Fig. 9(a) shows. Because both bump and adhesive are bonding media, the total thickness difference between them needs to be optimized to ensure the bonding integrity on both parts. In addition, due to BCB covering and patterning after bump formation, BCB residue on bump surface was observed and it induced the microjoint bonding failure. In

5 KO et al.: WAFER-LEVEL THREE-DIMENSIONAL INTEGRATION SCHEME WITH Cu TSVs 213 Fig. 11. Image of a complete 3-D integration wafer with four kinds of designs. Fig. 10. (a) The demonstration of 300 mm wafer thinning down to 25 μm thickness; (b) Backside TSV Cu-protrusion image and profile. the study, a post lithographic treatment was adopted to clean the bump surface to ensure metal intimate contact. Microbump with 5 μm thickness (3 μm Cu and 2 μm Sn) combination with 4 μm thick BCB was applied on one wafer side. Two wafers were aligned and hybrid bonded at 250 C using SUSS manual bonder. The misalignment may be up to several μm in manual mode. As the results shown in Fig. 9(b), 2 μm total thickness difference and an adequate surface treatment application realize the complete bonding performance. Both BCB and microjoint parts are well bonded. Sn metal is almost consumed and Cu 6 Sn 5 IMC is observed. The interconnect joints are well protected with BCB perfect sealing around. Fig. 12. wafer. Cross-sectional SEM image of one design in the 3-D integration D. Wafer Thinning and Backside RDL Formation Wafer thinning, TSV Cu-protrusion and backside RDL formation are the key technologies to perform the wafer-level 3-D interconnection after bonding/stacking. With coarse and fine grinding followed by CMP stress release treatment, 300 mm wafer thinning down to 25 μm thickness had been realized without any crack and chipping as Fig. 10(a) demonstrates. In this 3-D integration platform, the permanent bonded TSV wafer was thinned down to 40 μm with 2 μm TSV Cu-protrusion implemented by CMP. Fig. 10(b) shows the Cu-protrusion image and profile. The thinned TSV wafer was sequentially spin-coated by PI passivation, and lithographed to expose TSV again for backside RDL interconnection. With the bottom wafer support, the backside processes could be implemented smoothly and completed. Based on the successful development and integration of key technologies, a complete 3-D integration scheme has been achieved as shown in Fig. 11. Herein the TSV wafer was fabricated first, stacked on the bottom wafer using Cu/Sn microbump and BCB hybrid bonding with excellent bonding integrity and uniformity, thinned down to 40 μm without any crack and chipping, and completed with backside RDL formation. Four test vehicles were designed to investigate the electrical performances of 3-D integration. Fig. 12 presents the cross-section image of one design in the 3-D integration wafer. 5 μm TSV, 10 μmmicrobump,20μm pitch, 40 μm thin wafer, and 250 C low temperature W2W hybrid bonding have been successfully integrated in this 3-D integration scheme. IV. ELECTRICAL PERFORMANCE AND RELIABILITY Electrical characteristics of the 3-D integration scheme were evaluated through the bond chain structures. The linear characteristic of total resistances and number of via chains with a series of Cu TSVs and Cu/Sn microjoints interconnection indicates excellent bonding integrity and electrical performance. Fig. 13 shows characteristics of total resistances of via chains and locations on wafer. The deviation below 20% indicates good integration performance and uniformity across whole wafer. The total daisy chain resistance equals number of via chain multiply single TSV and microjoint resistance plus trace resistance plus probe contact resistance. Herein the average of total daisy chain resistance in Fig. 13 is about 5.3 Ω with 100 via chains connected in series. The Kelvin structure was designed to investigate the characteristic of single TSV and microjoint interconnect, and the measurement results show the average of single TSV and microjoint resistance is about 45 mω. Fig. 14 shows characteristics of voltage and current on one 5 μm Cu TSV and 10 μm Cu/Sn microjoint under multiple current stressing. The characteristic curves are almost the same, which implies excellent electrical performance and stability

6 214 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 12, NO. 2, JUNE 2012 Fig. 13. wafer. Characteristics of total resistances of via chains and locations on Fig. 15. Three-Dimensional SRAM demonstration: (a) The proposed Semi- Master Slave (SMS); (b) TSV wire delay characterization; (c) The crosssectional SEM image and schematic diagram of 3-D SRAM stacking. Fig. 14. Characteristics of voltage and current on one 5 μm CuTSVand 10 μm Cu/Sn microjoint under multiple current stressing. even after 1000 cycles of current stressing. In addition, via chains were evaluated by multiple current stressing, showing excellent stability as Fig. 14 presents. It also indicates the developed 3-D integration scheme possesses excellent stability and reliability. V. T HREE-DIMENSIONAL MEMORY DEMONSTRATION With the excellent electrical performance and reliability, the developed 3-D integration scheme could be applied for many applications. One of the potential applications is memory stacking as Fig. 15 demonstrates. Fig. 15(a) presents the proposed Semi-Master Slave (SMS) with design of self-timed differential-tsv (STDT) signal transfer [15]. Fig. 15(b) shows the characteristics of TSV wire delay. The delay significantly decreases with STDT design. Fig. 15(c) presents the crosssectional SEM image and the schematic diagram of two-layer 3-D SRAM stacking. New 3-D SRAM circuit design with TSV and microbump interconnect realizes low power, high capacity and high-speed wide I/O applications. VI. CONCLUSION The insertion loss of two-chip stack with vertical interconnect by Cu TSV and Cu/Sn microjoint was evaluated with TSV pitch, microbump diameter and chip thickness effect. As the TSV pitch increases, the insertion loss improves in middle frequency region but turns to become worse and drops quickly in high frequency region due to the loop inductance increasing. The insertion loss does not improve significantly as the microbump diameter increasing because the microbump is surrounded by the lossless BCB other than the lossy silicon substrate, and the fat and short structure of microbump is still very conductive. As chip thickness increases, the insertion loss increases as well due to the TSV impedance increases. The TSV pitch, microbump resistance and chip thickness are the important parameters when system working on higher bandwidth. A wafer-level 3-D integration scheme with Cu TSVs based on Cu/Sn microbump and BCB adhesive hybrid bonding was demonstrated. Key techniques including TSV interconnection, microbumping, hybrid bonding, wafer thinning and backside RDL formation were well developed and integrated to realize it. 5 μm TSV,10μm microbump,20μm pitch, 40 μm thin wafer, and 250 C low temperature W2W hybrid bonding have been successfully integrated in the 3-D integration scheme. The 3-D integration scheme, with excellent electrical performance and reliability, is potentially to be applied for 3-D memory application. ACKNOWLEDGMENT The authors would like to thank H.-H. Chang, W.-L. Tsai, C.-K. Lee, S.-W. Chen, Y.-F. Chen, and T.-H. Yu for the experiment assistance. REFERENCES [1] Presentation J. Q. Lu, Wafer-level 3D hyper-integration technology platform, [2] F. Niklaus, J. Q. Lu, J. J. McMahon, J. Yu, S. H. Lee, T. S. Cale, and R. J. Gutmann, Wafer-level 3D integration technology

7 KO et al.: WAFER-LEVEL THREE-DIMENSIONAL INTEGRATION SCHEME WITH Cu TSVs 215 platforms for ICs and MEMs, in Proc. 22nd Int. VMIC, T.Wade,Ed., 2005, pp [3] P. Ramm, European activities in 3D system integration The e-cubes project, in Proc. 12th Annu. Pan Pacific Maui, Feb. 1, [4] P. Garrou, Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, vol. 2. Hoboken, NJ: Wiley, [5] M. Umemoto, K. Tanida, Y. Nemoto, M. Hoshino, K. Kojima, Y. Shirai, and K. Takahashi, High-performance vertical interconnection for highdensity 3D chip stacking package, in Proc. Electron. Compon. Technol. Conf., Las Vegas, NV, Jun. 1 4, 2004, pp [6] P. Benkart, A. Munding, A. Kaiser, E. Kohn, A. Heittmann, H. Huebner, and U. Ramacher, 3-dimensional integration scheme with a thermal budget below 300 C, Sens. Actuators A, Phys., vol. 139, no. 1/2, pp , Sep [7] U. Kang, H. J. Chung, S. Heo, D. H. Park, H. Lee, J. H. Kim, and S. H. Ahn, 8 GB 3D DDR3 DRAM using through-silicon-via technology, IEEE J. Solid-State Circuits, vol. 45, no. 1, pp , Jan [8] J. Hwang, J. Kim, W. Kwon, U. Kang, T. Cho, and S. Kang, Fine Pitch Chip Interconnection Technology for 3D Integration, in Proc. Electron. Compon. Technol. Conf., Las Vegas, NV, Jun. 1 4, 2010, pp [9] R. Agarwal, W. Zhang, P. Limaye, R. Labie, B. Dimcic, A. Phommahaxay, and P. Soussan, Cu/Sn microbumps interconnect for 3D TSV chip stacking, in Proc. Electron. Compon. Technol. Conf., Las Vegas, NV, Jun. 1 4, 2010, pp [10] C. J. Zhan, J. Y. Juang, Y. M. Lin, Y. W. Huang, K. S. Kao, T. F. Yang, S. T. Lu, J. H. Lau, T. H. Chen, R. Lo, and M. J. Kao, Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30 μm pitch lead-free solder micro bumps and reliability characterization, in Proc. Electron. Compon. Technol. Conf., Lake Buena Vista, FL, May 31 Jun. 3, 2011, pp [11] C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, High frequency electrical model of through wafer via for 3-D stacked chip packaging, in Proc. Electron. Systemintegr. Technol. Conf., Dresden, Germany, Sep. 5 7, 2006, pp [12] J. Kim, J. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, K. Park, S. Yang, M. S. Suh, K. Y. Byun, and J. Kim, High-frequency scalable electrical model and analysis of a through silicon via (TSV), IEEE Trans. Compon., Packag. Manuf. Technol., vol. 1, no. 2, pp , Feb [13] N. Ranganathan, K. Prasad, N. Balasubramanian, and K. Pey, A study of thermo-mechanical stress and its impact on through-silicon vias, J. Micromech. Microeng., vol. 18, no. 7, pp , Jul [14] C. T. Ko, K. N. Chen, W. C. Lo, C. A. Cheng, W. C. Huang, Z. C. Hsiao, H. C. Fu, and Y. H. Chen, Wafer-level 3D integration using hybrid bonding, in Proc. 3D Syst. Integr. Conf., Berlin, Germany, Nov , 2010, pp [15] M. F. Chang, W. C. Wu, C. S. Lin, P. F. Chiu, M. B. Chen, Y. H. Chen, H. C. Lai, Z. H. Lin, S. S. Sheu, T. K. Ku, and H. Yamauchi, A larger stacked layer number scalable TSV-based 3D-SRAM for highperformance universal-memory-capacity 3D-IC platform, in Proc. Symp. VLSI Circuits, Kyoto, Japan, Jun , 2011, pp nanotubes. Zhi-Cheng Hsiao received the M.S. degree in mechanical engineering from National Taiwan University of Science and Technology, Taipei, Taiwan, in Since 2003, he has been with the Electronics and Technology Research Institute, Hsinchu, Taiwan. The focus of his research includes MEMS technology, microbumping technology, wafer-level packaging, and 3-D integrated circuit technologies. Yao-Jen Chang received the B.S. degree in electrical engineering from Tamkang University, New Taipei, Taiwan, in He is currently working toward the Ph.D. degree in the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. From 2009 to 2010, he was an Intern with the Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute, Hsinchu. His research interests include RF ICs, 3-D integrated circuit technologies, and carbon Peng-Shu Chen received the M.S. degree in computer and communication engineering from National Taipei University of Technology, Taipei, Taiwan, in Since 2009, he has been with the Electronics and Technology Research Institute, Hsinchu, Taiwan. His research focuses on high-speed digital circuit design and methodology. Yu-Jiau Hwang received the B.S. degree in applied foreign languages from Ta Hwa Institute of Technology, Qionglin, Taiwan, in Since 1994, she has been with the Electronics and Technology Research Institute, Hsinchu, Taiwan. The focus of her research includes wafer-level packaging, mask design, embedded passive device packaging, and 3-D integrated circuit technologies. Cheng-Ta Ko received the B.S. and M.S. degrees in chemical engineering from National Taiwan University, Taipei, Taiwan, in 2000 and 2002, respectively. He is currently working toward the Ph.D. degree in the Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan. Since 2002, he has been with the Electronics and Technology Research Institute, Hsinchu, where he is currently a Project Manager with the Packaging Technology Division. The focus of his research includes wafer-level packaging, system-in-package technology, flexible electronic packaging, and 3-D integrated circuit technologies. technologies. Huan-Chun Fu received the M.S. degree in electrical engineering from Chang Gung University, Kwei-Shan Tao-Yuan, Taiwan, in From 2000 to 2001, he was with RD3, TrueLight Corporation. Since 2002, he has been with the Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan, where he is currently an Engineer with the Packaging Technology Division. The focus of his research includes wafer-level packaging, electrical and optical circuit boards, and 3-D integrated circuit

8 216 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 12, NO. 2, JUNE 2012 Jui-Hsiung Huang received the B.S. and Ph.D. degrees in chemical engineering from National Taiwan University, Taipei, Taiwan, in 2000 and 2007, respectively. Since 2008, he has been with the Electronics and Technology Research Institute, Hsinchu, Taiwan, where he is currently an Engineer with the Packaging Technology Division. The focus of his research includes electrochemistry in metallization, wafer-level packaging, embedded active device packaging, and 3-D integrated circuit technologies. Chia-Wen Chiang received the M.S. degree in materials science and engineering from National Tsing Hua University, Hsinchu, Taiwan, in Since 2004, she has been with the Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute, Hsinchu. The focus of her research includes integrated passive device technology, wafer thinning technology, wafer-level packaging, and 3-D integrated circuit technologies. Shyh-Shyuan Sheu is currently working toward the Ph.D. degree in the Department of Electrical Engineering, National Central University, Zhongli, Taiwan. In January 2003, he joined the Electronics and Technology Research Institute, Hsinchu, Taiwan, as an IC Designer. His research involves memory, display, and CMOS image sensor circuit design and technology. Yu-Hua Chen received the Ph.D. degree in chemistry from National Taiwan University, Taipei, Taiwan, in Since 2001, he has been with the Electronics and Technology Research Institute, Hsinchu, Taiwan, where he is currently a Deputy Division Director with the Packaging Technology Division. The focus of his research includes wafer-level packaging, system-in-package technology, flexible electronic packaging, and 3-D integrated circuit technologies. Wei-Chung Lo received the Ph.D. degree in chemistry from National Taiwan University, Taipei, Taiwan, in Since 1997, he has been with the Electronics and Technology Research Institute, Hsinchu, Taiwan, where he is currently the Director of the Packaging Technology Division. Dr. Lo is currently the Executive Secretary of the Advanced Stacked-System and Application Consortium, the Program Committee Chair of the International Microsystems, Packaging, Assembly and Circuits Technology Conference, and the Chair of the Advanced Microsystem and Packaging Alliance, the largest package alliance in Taiwan. Kuan-Neng Chen (M 05 SM 11) received the Ph.D. degree in electrical engineering and computer science and the M.S. degree in materials science and engineering from the Massachusetts Institute of Technology, Cambridge. He is currently a Professor with the Department of Electronics Engineering, National Chiao Tung University (NCTU), Hsinchu, Taiwan. Prior to the faculty position, he was a Research Staff Member of the IBM Thomas J. Watson Research Center. He is the Editor of the book 3D Integration for VLSI Systems. He has authored more than 120 publications in book chapters, journals, and international conference proceedings and is the holder of more than 60 patents and patent applications. He started 3-D integrated circuit (3-D IC) research in His current research interests are 3-D ICs, through-silicon via technology, wafer bonding technology, phase-change material devices, and nanodevices. Dr. Chen is an alternate council member of the Electronics Devices and Materials Association and a member of the Phi Tau Phi Scholastic Honor Society. He was the recipient of the NCTU Distinguished Faculty Award, the NCTU Outstanding Industry Academia Cooperation Achievement Award, the Advantech Young Professor Award, and the EDMA Outstanding Youth Award. He was also the recipient of several IBM awards, including five IBM Plateau Invention Achievement Awards and two awards from the Exploratory Technology Group. He is currently a Committee Member of IEEE 3DIC, IEEE SSDM, and DPS.