System-in-Package Research within the IeMRC

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1 LANCASTER U N I V E R S I T Y Centre for Microsystems Engineering Faculty of Applied Sciences System-in-Package Research within the IeMRC Prof. Andrew Richardson (Lancaster University) Prof. Chris Bailey (University of Greenwich)

2 Project Statistics Design for Manufacture Methodology for SiP Academic partners : Lancaster University & Greenwich Industrial partners : NXP, Flowmerics, Coventor & Selex 206K Nov 2005 Nov 2007 Focus : Reliability Engineering of SiP assemblies Solder ball and assembly reliability modelling Embedded test & reliability indicators Uptake potential : Through application of knowhow on NXP demonstrator, capture of code within tools Generic application of embedded test strategies

3 What is System-in-Package, or SiP? The integration of several Integrated Circuits and components of various technologies (RF, analogue, digital, in Si, in GaAs) in a single package, resulting in one or several electronic systems Related key words: Heterogeneous Integration, System-on-Chip, SoP Stacked Structures Side-by-Side Structures Embedded Structures

4 Market Trends : Industry moves to WLP WLP Market Projection Mu shipment TechSearch 4Q04 CAGR % Gartner 1Q06 CAGR % Gartner TechSearch Expected CAGR > 25% Source: Gartner 1Q06 + TechSearch 3Q Both TechSearch and Gartner confirms a significant growth of WLP deliveries 70% of WLP applied to Integrated Passives in 2005

5 Move to full silicon-based SiPs Proportion of SiP 100% silicon-based 100% SiP Silicon-based SiP MCM MCM + discrete passives on laminate + Integrated Passive MCM + discrete passives on laminate passives on laminate = leadframe based + WL-CSP passives on laminate + Integrated Passives MultiChip Modules (MCM) Multi-Chip Modules (MCM) year year

6 NXP SiP Platforms Trend PCB Discretes Solutions PCB MCM Solutions Integration Trend PCB Laminate + SMDs Solutions PCB Laminate + SMDs + Passive die PCB Double Flip Chip assembly Active Die Passive/Interconnect die SMDs / Components PCB PCB Wafer Level Packaging 3D WLP SiPs

7 WL-SiP: challenges Larger WL-CSP modules (because SiP are larger than current WL-CSP parts) Board Level Reliability (solder fatigue issue) Larger WL-CSP modules Board Level Reliability (solder fatigue issue) Assembly flow Final Test Marking Packing Storing Customer acceptance Customers and assemblers (pick & place, under fill dispensing on PCB) Designers (sockets for evaluation boards) PCB makers: downwards CTE curve to be supported

8 Lancaster University Centre for Microsystems Engineering 4 academic staff, 5 RA s, 4 PhD s Delivered against 3.4M in grant income over the past 10 years Leads the European Design for Micro & Nano Manufacture community through the FP6 Network of Excellence (PATENT-DfMM)

9 University of Greenwich Centre for Numerical Modelling and Process Analysis 5 Profs, 20+ Post Docs, 40 + PhD s One of largest groups in UK Electronics and Microsystems 2 Profs, 3 Post Doc s, 5 PhD s Over 2m of support since 1998 in electronics and microsystems modelling.

10 Modelling Methodology SiP Data Inputs (Geometry, Materials, Failure Data) Manufacturing High Fidelity Modelling (Multi-Physics) Design of Experiments Response Surface Analysis OPTIMISATION Reduced Order Models (Multi-Physics) Uncertainty Analysis Sensitivity Analysis Design Optimisation Test/Reliability Optimal SiP Structures

11 SiP Structure

12 Design Variables 1. PCB thickness (HPCB) 2. Board level solder joints stand-off-height (SOH) 3. Passive die thickness (HDIE)

13 Design Steps Flow 1. Identify design points 2. Simulate responses at each point: Joint Lifetime Package Warpage 3. Construct Reduced Order Design of Experiments FEA at experimental points Response Surface Modelling (ROM) Sensitivity Analysis 1. Account for Uncertainties in Design Variables Design for Reliability Design for Robustness Reliability Uncertainties Robustness Design Task as Optimisation Problem / Design Solution

14 Finite Element Calculations 1) Warpage of the package: D w 2) Fatigue life of solder joints: N f Warpage at 125C Solder Joints Damage

15 Step 1: Virtual DoE Central Composite Design (CCD) 15 Design points FEA Responses for Cycles to failure (N f ) Warpage of SiP (D w ) Factorial Point Axial Point Central Point

16 Step 2: Generate Reduced Order Model RoM to represent: Warpage of SiP Lifetime of solder joints Fast predictions for SiP Statistical tests for accuracy ANOVA Efficiency measures, etc

17 (a) Deterministic Optimal Design Design task solved using numerical optimisation techniques Optimal design Warpage reduced by 22 % Lifetime Satisfied Deterministic Formulation

18 (b) Probabilistic Design Design variables have uncertainties Design variables modelled with Gaussian distribution Standard deviations: a) HPCB: σ HPCB = 16 um; b) SOH: σ SOH = 2 um; Probabilistic Optimal design Critical Response 2 Design Variable A Critical Response 1 c) HDIE: σ HDIE = 2.5 um; Deterministic Optimal design Design Variable B

19 Design for Reliability Constraints re-defined in terms of probability of failure Monte Carlo simulations Evaluation of the distribution of the response values Probabilistic Formulation 800 Frequency % of designs have required life-time Fatigue Life (cycles) Uncertanty at Reliable Optimum

20 Design for Robustness Design for Robustness design that has minimum uncertainty (variation) of its responses Focus is on life-time Probabilistic Formulation Frequency ± 1σ σ=14 cycles Fatigue Life (cycles) Uncertanty at Robust Optimum

21 Solder Ball Reliability Objective : Build an Analytic Method of Reliability for Solder Joint in Package Inter Metallic Layer (IMC) So ACK, Chan YC. Reliability studies of surface mount solder joints effect of Cu-Sn intermetallic compounds. IEEE Trans Comp Pack Manuf Technol Part B 1996; 19: Weibull distribution β : Weibull slope parameter η : Characteristic life parameter N : Random thermal life cycles to failure δ : IMC layer thickness

22 Inter Metallic Layer Growth Reflow profile δ : IMC layer thickness t : Reflow time T : Temperature of reflow Dependence on reflow time (given temperature) : Dependence on temperature (given time) : * Ts : saturated temperature * More accurate than polynomial fitting proposed in Huang W, Loman JM, Sener B. Study of the effect of reflow time and temperature on Cu-Sn intermetallic compound layer reliability. Microelectronics reliability. 42(2002)

23 Results : 3D plots - Low reflow temperature or avoid the interval [190,240]??????? - As small a reflow time as possible

24 Further Recent Results Effects of process conditions on reliability of lead-free packages Solder joint volume Undefils Reflow temperatures Pad Geometries thermal cycling test ( 4 0oC/ + 125oC) Twin die stacked packages Die thickness (bottom and top) Core thickness Substrate thickness

25 Conclusions Work to date focused around silicon based WL-SiP Embedded health monitoring Strategies for non-electrical functions Reliability simulation structure & assembly Investigated effect of underfill on solder reliability Investigated the impact of moulding process Developed ROM for specific SiP structures Software environment developed Future Work Extend to SoP eg. Ceramic based Investigate integration into EDA tools

26 Acknowledgments Dr Nobert Dumas (Lancaster) Dr Dongsheng Liu (Lancaster) Dr Nadia Strussavich (Greenwich) Dr Stoyan Stoyanov (Greenwich) And Industrial partners