Test Item Priority Estimation for High Parallel Test Efficiency under ATE Debug Time Constraints

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1 Test Item Priority Estimation for High Parallel Test Efficiency under ATE Debug Time Constraints Young-woo Lee 1, Inhyuk Choi 1, Kang-Hoon Oh 2, James Jinsoo Ko 2 and Sungho Kang 1 1 Dept. of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea 2 Teradyne Inc., Seoul, Korea 1 {roberto, ihchoi}@soc.yonsei.ac.kr, 2 {kang-hoon.oh, jin-soo.ko}@teradyne.com and 1 shkang@yonsei.ac.kr Abstract Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution. Keywords; parallel test efficiency; test program optimization; test item priority estimation; automatic test equipment; costs of test I. INTRODUCTION System-on-chip (SoC) circuits must be necessarily tested to reduce the assembly cost and to maintain the high quality of devices. It is the continuous challenges of the semiconductor production to reduce the costs of test (COT), and the test time is an important part of the COT [1]. As the competitive design markets have thinner profit margins, it is more necessary to keep a constant check on the lower total cost and the faster time to market [2]. For this reason, the test time optimization is a primary goal to reduce the increasing COT [3]. The parallel testing is widely used in the testing industry, which has successfully provided the COT reduction for years [4] [6]. It is a traditional test technique to simultaneously perform the same test item on the multiple devices under test (DUTs) without compromising the test cost increases [7] [9]. Thus, it enables much more test data throughput in the identical test time budget [10]. According to [1] and [11], the parallel testing of four devices can reduce the test cost up to 50%, comparing to the serial testing. To decrease the overall time for testing a large volume of devices, semiconductor manufacture companies implement the parallel testing for mass production [12]. The ideal test time of the parallel testing is exactly equal to the test time of the serial testing. The test time per each device of the parallel testing becomes 1/N of the serial testing, where N is the number of multiple sites. However, the actual test time of the parallel testing is increased by performing the serial testing of some test items, which is caused by an inefficient test program or a lack of the tester resource. These problems, such as the lack of the tester resource or the test time overhead of the automatic test equipment (ATE) for controlling multiple sites, can only be solved by upgrading the tester resource or changing the newest ATE; the COT is highly increased [13]. In contrast, the inefficient ATE test program is a soluble problem without increasing the COT. It can be solved by optimizing the ATE test program for the high parallel test efficiency (PTE). The test program optimization is to improve the PTE by debugging on the ATE, and it also enables the test time reduction. The increased test time caused by the inefficient ATE test program can be reduced to the ideal test time of the parallel test by optimizing all test items in the ATE test program on the assumption that we had an infinite amount of time. Unfortunately, a given debug time for the test program optimization is only available until mass production starts. Consequently, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. Under this ATE debug time constraints, it is important to select cost-effective test items for optimizing the test program in order to enhance the PTE. Our test item priority estimation method can provide the cost-effective solution to reduce the COT under the ATE debug time constraints. II. BACKGROUND This section introduces some important notions that will be used throughout the rest of the paper, and briefly decribes an example of the ATE test program optimization method for high parallel test efficiency. A. Parallel Test Efficiency (PTE) The parallel testing is the test method to perform the same test item on the multiple sites at the same time. The PTE is the performance indicator of the ATE to test multiple sites in parallel. The international technology roadmap for semiconductors (ITRS 2005) defines the PTE as shown in (1), where N is the number of multiple sites [14]. (N Sites) is the test time for the N number of DUTs, and (S Site) is the test time for the single DUT. This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(misp) (No. 2015R1A2A1A ). 150

2 Relative Cost per Unit Number of Sites Fig. 1. Relative cost of capital (ATE) per unit tested % 96.0% 94.0% 90.0% 86.0% 84.0% 80.0% Fig. 1 represents the relative cost of capital (ATE) per unit tested as functions of the number of multiple sites, which is announced by [15]. The dual site parallel test already cuts test costs by 50% in an ideal case of the PTE where the test time of multiple sites is exactly equal to the time required to test a single site, i.e. PTE = 100%. B. Test Program Optimization Method for High PTE The highest throughput for the multi-site testing can be achieved by improving the PTE of the ATE. To improve the PTE, it is essential to optimize the test program by debugging on the ATE. The debugging method can be done by following the steps described below. Firstly, the test engineer selects the test item to debug, and then they measure the code execution time of each line in the specific test item by using a Visual Basic s time-stamp or a Timelines tool [15]. These estimated execution times can help to find the inefficient ATE test program code while debugging to enhance the PTE. However, the test engineer still needs to analyze each line of code whether the test program can be optimized or not. It is often difficult and time consuming to find the improper code for the high PTE, but it can drastically reduce the test time. Fig. 2 shows the optimization method for the high PTE in part of the single test item as an example; the used tester platform is UltraFLEX [15]. The red box in Fig. 2 represents the partial ATE programming code in IG-XL to apply the device power supply (DPS) per each site. The previous source code is to serially apply the site-specific value of the double variable to the DPS. After optimizing the test program, it simultaneously applies the site-specific value for the multiple sites with using the site-double variable. This method can reduce the considerable test time as much as the number of sites. The blue box in Fig. 2 shows another example of the optimized source code to enhance the PTE. The execution time of the general C code is much faster than the ATE code because it takes more time to communicate between the ATE and the host computer. The execution time can get worse if the ATE code operates in the site serial mode; the data transfer time of the parallel multi-threading for the multiple sites is much more rapid than the serial threading method. In contrast, the general C code does not significantly affect the time-related increase, despite of processing it sequentially via a for-eachsite-loop. For this reason, the ATE code is potentially more effective when it is located out of the site serial sequence (i.e. the for-each-site-loop), if the ATE code supports the multi-site functions. In summary, the test program optimization can help to improve the PTE and also to reduce the test time. However, it is difficult to find a sticking point in the single test item, because some test item consists of approximately 800 lines of code and also is very complicated to understand. Nonetheless, the test program optimization is the fundamental requirement to reduce the COT. III. PROPOSED IDEA A. Motivation In general, the selection method of the test item for debug is obtained by using the equation of the PTE [14]. Each single test item is sorted in the ascending order of priority by the value of PTE results. However, the equation of the PTE is only useful for the total test time difference between the serial testing and the parallel testing, not for the test time of each single test item in the ATE test program. When the PTE of the single test item is calculated, the original equation of the PTE does not involve the total test time of whole test items, which means the PTE result of the single test item is not associated with a proportion of the total test time. For this reason, some test items have almost no impact on the total test time or the PTE of whole test items even though each PTE result of these test items is extremely low. In contrast, some other test items can cause serious problems for production such as the high test time or the low PTE of the device, despite the very high PTE result of each of these test items. These can eventually lead to a Fig. 2. Simple example of the optimization method for the high parallel test efficiency. 151

3 difficult decision; it is hard to determine which test item has a higher priority to efficiently improve the total PTE of the device. The number of test items in the test program depends on the type of the device, but it is approximately a thousand in case of the highly complex SoC device. As already mentioned, the available ATE debug time for the test program optimization is just until mass production starts. Consequently, it is very important to rapidly select the costeffective test items in order to improve the total PTE of the device. Then, the selected test items are required to optimize the test program by debugging on the ATE, given the time constraints of the production schedule. In order to efficiently reduce the COT, we propose the test item priority estimation method as the cost-effective solution. B. Test Item Priority Estimation (TIPE) for High PTE The proposed method is to sequentially select the most cost-effective test item in order to optimize the ATE test program for the high PTE. The proposed equation of the TIPE is based on the equation of PTE with using the weight value of each test item, as shown in (2). The weight is specified by assigning a certain number computed as in (3), where N is the number of multiple sites and M is the number of total test items in the ATE test program. The following notations Total (N Sites) and Total (S Site) are used to refer to the total test time of all test items for the N number of DUTs and the single DUT, respectively. (N Sites) is the test time of the specific single test item for N DUTs. Equation (4) represents the simple description of the weight in order to more easily understand the weight as in (3). To obtain the weight value of each test item, it is required to firstly calculate an average of the total test time difference between the N DUTs and the single DUT (T Avg.); this value can be computed by (5). Then the weight value of the specific test item is obtained by dividing the average of the total test time difference by the test time difference of the specific test item. The TIPE value is calculated by multiplying the PTE value by the weight value, and it is performed on the weight value basis; the baseline of the weight value is 1. The weight value of each test item is determined by the proportion of impacting on the total test time. If the specific test item with the extremely low PTE result has almost no impact on the total test time, the weight value will be obtained as greater than 1. Then the TIPE value will be increasing more than the original PTE value. In contrast, the weight value is set as less than 1 if the specific test item with the high PTE results makes the total test time worse. The TIPE result of this specific test item will be lower than the original PTE value and it will be assigned as the higher priority. Next Test Item (CURRENT) No Initialize Variable Value named ADDRESS as 0 Calculate TIPE (CURRENT) ADDRESS = ADDRESS + 1 No TIPE (CURRENT) TIPEADDRESS? Yes Newly Insert TIPE (CURRENT) and Test Item (CURRENT) into CellADDRESS End of Test Item? Yes Start Create TIPE table End Fig. 3. Flow diagram of the TIPE method. TIPE (CURRENT) : TIPE value of the current test item TIPEADDRESS : TIPE value in CellADDRESS CellADDRESS : ADDRESS-th table cell in TIPE table In summary, the weight value makes it possible to change the original PTE value of each test item, depending on the relative importance of the cost-effective test item, and then the PTE result table is newly reordered by the equation of TIPE. C. Operation Flow of TIPE Method Fig. 3 represents the flow diagram of the TIPE method. Firstly, it is required to create the new TIPE table and the number of the TIPE table rows equals to the number of test items. Next the variable value named ADDRESS is initialized, and then the TIPE of the current specific test item can be calculated by the equation of TIPE. To store the calculated TIPE value to the appropriate location in the TIPE table, the TIPE value of the current specific test item is repeatedly compared to the TIPE value of the next cell until the current TIPE value is less than the next cell value in the TIPE table. After that, the name and the TIPE value of the current test item are newly inserted into the activated cell, respectively. This sequence continuously repeats the same operation flow from the second step until the end of the test item. After this whole flow, the name and the TIPE value of the all test items will be completely contained in the TIPE table, which is sort of the more cost-effective test item in the ascending order. Consequently, the TIPE table provides the cost-effective solution that the test engineer can easily select the higher priority test item from the top down in order to efficiently debug for improving the total PTE of the device under the ATE debug time constraints. IV. EXPERIMENTAL RESULTS In this section, the proposed TIPE method is evaluated by using the actual industrial SoC circuits, and we assumed that the parallel performance of the ATE could support the perfect parallelism. The used complex SoC device has the 983 test items, and the number of the multi-site testing can support up to 4 sites under the given test infrastructure. The total test time 152

4 No. Test Item # (Single Site) (Multiple Sites) PTE TIPE % 0.00% % 0.00% % 0.00% % 0.00% % % % 32.96% % 35.46% % 36.49% % 34.31% % 35.86% % 36.16% % 39.07% % 36.45% % 44.41% % 46.29% % 46.23% % % % 55.86% % % % 84.23% % 37.65% % 88.04% % 45.23% % % % 58.28% % 98.55% % % % % % 39.40% % % No. Test Item # (Single Site) (Multiple Sites) PTE TIPE % 0.00% % 0.00% % 0.00% % 0.00% % 0.63% % 0.82% % 3.88% % 6.27% % 7.51% % 8.92% % 10.32% % 11.20% % 11.91% % 12.03% % 21.17% % 22.09% % 26.55% % 26.90% % 29.20% % 30.78% % 32.45% % 32.87% % 32.96% % 33.54% % 33.99% % 34.31% % 35.46% % 35.86% % 36.16% % 36.43% Fig. 4. Comparison of selected results for the test program optimization among 983 test items. (a) 30 test items sorted by the ascending order of PTE values. (b) 30 test items sorted by the ascending order of TIPE values. of the device is and seconds for the single site and multiple sites, respectively, which is measured by the UltraFLEX test system. According to the equation of PTE, the initial PTE of the device is 92.93%. A. Comparison of Cost-effective Performance As discussed in the previous section, it is required to select the cost-effective test items to improve the PTE until mass production starts. The proposed method provides the costeffective solution for the high PTE of the device in order to reduce the COT. It is assumed that the available ATE debug time is only for 30 test items as an example. Fig. 4 (a) and (b) represent the comparison table of the selected 30 test items among the 983 test items by the PTE and the TIPE, respectively. The previous method is that the test items are selected by sorting the ascending order of the PTE result, as shown in Fig. 4 (a). The total test time can be decreased from to seconds after optimizing the test program of those selected 30 test items. As a result, the total PTE of the device is also improved from 92.93% to 93.62%. However, it would be more efficient solution for the COT reduction if we had selected other test items by the TIPE method. For example, the PTE value with a blue fill color in panel (a) of Fig. 4 indicates that it has little or no impact on the total test time or the total PTE of the device in spite of the low PTE; whereas each TIPE value is highly increased by the weight value of (3). Fig. 4 (b) represents the result of the other selected 30 test items by using the proposed method, which is sorting the ascending order of the TIPE result. The different 30 test items are also determined by the proposed TIPE method as an example. Each TIPE value with the red fill color in panel (b) of Fig. 4 is lower than the original PTE value, and those test items are assigned as the higher priority to efficiently debug for improving the total PTE of the device, compared to the selected 30 items shown in Fig. 4 (a). As a result, the total test time can be decreased from to seconds by using the proposed method, and the total PTE of the device is increased from 92.93% to 95.68%. In summary, the total test time by using the proposed method is seconds faster than the previous one, and it also provides 2.06% higher total PTE of the device. In this case, the proposed method shows better performance results under the same number of selected 30 test items to debug for the high PTE. B. Capability of Early Identification for Skipped Test Item The TIPE method is also capable of detecting the skipped test item during the multi-site parallel testing. The test time for the single site is supposed to be faster than the test time for the multiple sites. However, it can be faster if the test item is not executed by the inefficient ATE test program during the parallel testing. In this case, the original PTE value is 100% despite of the abnormal testing. In contrast, the TIPE value is 153

5 PTE (%) % 99.00% 98.00% 97.00% 96.00% 95.00% 94.00% 93.00% 92.00% Number of selected test items to debug Previous method Proposed method Number of test items Total (sec) Previous method Proposed method Max Fig. 5. Experimental results after the test program optimization as functions of the number of selected test items to debug under the same ATE debug time constraints. (a) Total PTE of the device. (b) Total test time of the device. drastically decreased by the absolute value of the test time difference of the specific test item between the single site and the multiple sites as shown in (3) and (4). For example, the 11th test item (#613) or the 15th test item (#510) as described in Fig. 4 (b) shows that the test time for the single site is greater than the test time for multiple sites. Both TIPE values are extremely decreased from the 100% PTE result to 10.32% and 21.17%, respectively. According to the sharply decreased TIPE value, the proposed method enables the early identification of the skipped test item during the production by checking or debugging in the ascending order of the TIPE values. C. Summary of Experimental Results Fig. 5 (a) shows the total PTE results of the device by the previous and proposed method after optimizing the test program, as functions of the number of selected test items to debug. According to this graph in Fig. 5 (a), the proposed method continuously maintains higher total PTE result of the device than the previous method under the same ATE debug time constraints. Fig. 5 (b) represents the comparison table of the total test time of the device as functions of the number of selected test items to debug. The proposed method always provides the faster total test time if the number of selected test items is more than four test items. Consequently, those experimental results represent that the proposed method is the more cost-effective solution under the same ATE debug time constraints. V. CONCLUSION As the process technology is becoming more advanced, the SoC device is getting more complex and also consists of more kinds of the intellectual property (IP) blocks. For this reason, we can easily expect that the number of test items would also increase in proportion to the process technology. To reduce the COT, it is required to select the cost-effective test items in order to optimize the ATE test program for the PTE enhancement until mass production starts. However, it is difficult to determine which test item has a higher priority to efficiently debug for the high PTE of the device. Our new TIPE method can provide the better solution to rapidly find the cost-effective test items for reducing the COT under the ATE debug time constraints. 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