A Three-Step Approach For Low Power Scheduling Of Real- Time Embedded Systems

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1 A Three-Step Approach For Low Power Scheduling Of Real- Time Embedded Systems Rajesh Prathipati and Rabi Mahapatra Dept of Computer Science Texas A&M University College Station, TX ABSTRACT As batteries power an increasing number of electronic systems, power efficient design of real-time embedded systems becomes more important. In this paper we present a three-step low power static scheduling method for jointly scheduling periodic and aperiodic task graphs on variable voltage processors. The proposed method determines the lowest possible processor speed for each task while guaranteeing the deadlines. During the idle intervals, the scheduling method determines the feasible power mode and puts the processor in it. Our scheduling method provides a general framework and leads to significant power savings compared with the other known approaches. 1. INTRODUCTION Dynamic voltage scaling and power management techniques represent the two system-level power reduction strategies to extend the device s battery life. Dynamic voltage scaling refers to dynamically varying the speed of a processor by changing the clock frequency along with the supply voltage. Dynamic power management refers to the use of power-down modes when the processor is idle to reduce processor power consumption. The input specifications of real-time embedded systems are typically in the form of a task graphs. A task graph is a directed acyclic graph in which each node is associated with a task and each edge is associated with the amount of data that must be transferred between the two connected tasks. Task graphs can be periodic or aperiodic. Each task of a periodic task graph inherits the task graph s period. Each task in a periodic task graph can have a different deadline. An aperiodic task is invoked for execution at any time and may have a hard deadline or a soft deadline. All hard deadlines must be met. However, one only needs to minimize the response times of soft aperiodic tasks. For hard aperiodic tasks, generally a minimum inter arrival interval, τ, denoting the minimum time interval between two consecutive instances of an aperiodic task graph is specified. A hard aperiodic task graphs can arrive at the embedded systems for execution at any time and an execution slot must be available at the required time to meet the deadline. In this work, the worst-case execution time of hard aperiodic task graphs are calculated during Step 1 and a periodic behavior is modeled out of every aperiodic task graph by creating an execution slot which repeats at an appropriate periodic intervals to serve the hard aperiodic task with out causing it and the periodic tasks to miss the deadline. The scheduling method then generates the priority list containing the priorities of tasks while guaranteeing the deadlines and precedence constraints. In the second step, the scheduling method determines the lowest possible processor speed for each task while guaranteeing the deadlines of all the tasks. In the third step, the tasks are scheduled according to their priorities and are executed at the speeds determined by Step 2. The processor will be put in an appropriate low power/power down mode during idle intervals. Most of the work done so far concentrated only on periodic and independent tasks with shorter response times. In other words, every job completes before the next job in the same task is released. This is rather a special case. In this work, we consider a general case where the response times are arbitrary. This work also provides a general framework that encompasses both periodic and aperiodic tasks with precedence constraints. The proposed approach offers significant power savings compared with other known approaches. The rest of the paper is organized as follows. Section 2 gives a brief review of the work done so far in this area. Section 3 presents the various steps of the proposed approach. In Section 4 we illustrated an example to demonstrate the working of the proposed approach. Experimental results are discussed in Section 5. The Section 6 concludes the paper. 2. RELATED WORK Power-conscious fixed-priority scheduling algorithm based on rate-monotonic approach is proposed in [3]. This method yields power reduction by exploiting slack times. The work presented in [6] tries to determine the optimal voltage under which to execute the tasks and also takes in to account the idle intervals that arise dynamically. In [9] two algorithms are proposed to determine the voltage settings for a variable voltage processor that utilizes a fixed priority assignment to schedule jobs. The first algorithm determines the minimum constant speed needed to complete each job. The second algorithm builds on the first one and determines the minimum constant voltage (or speed) needed to complete a set of jobs and produces a voltage schedule. The above approaches are limited to periodic and independent tasks only. The scheduling method in [7] employs a reservation list, in which tasks are sorted by deadlines, to schedule the tasks at lowest possible voltage. The task with the earliest deadline is picked up from the list to schedule. The scheduler checks if the task is able to execute at low voltage by deadline without influencing any unscheduled task, which is in the reservation list. It will schedule tasks at low voltage if possible. An on-line scheduling algorithm for real-time tasks on variable voltage processor, where it is assumed that the release times of jobs are not known a priori is proposed in [11]. Dynamic power management (DPM) policies specifically tailored to battery-powered systems are presented in [12]. Battery-driven DPM strives to enhance lifetime by automatically adapting

2 discharge rate and current profiles to battery state-of-charge. An online scheduling algorithm based on EDF that attempts to minimize the energy consumed by a periodic task set is proposed in [10]. The above approaches are limited to independent tasks only. Power conscious algorithms for joint scheduling of periodic and aperiodic tasks that employs off-line table driven scheduling are proposed in [2]. This approach employs the off-line table driven scheduling which may not be applicable in general. The work in [5] proposes two battery aware scheduling schemes. The first one tries to optimize the discharge power profile by shifting the tasks forward and backward and the second one performs variable voltage scheduling via slack-time reallocation in order to flatten the discharge profile. This work is limited only to periodic and independent tasks. The work in [4] performs joint scheduling of distributed periodic and hard aperiodic tasks by determining the static schedule that meets timing and synchronization requirements. An acceptance test that determines whether there is enough slack/leeway is used to schedule the aperiodic tasks on the fly. This approach doesn t guarantee the acceptance of all hard aperiodic tasks and doesn t guarantee the satisfactory response time for soft aperiodic tasks. An energy priority scheduling heuristic proposed in [8] uses workload descriptions to compute energy-efficient schedules. The above three approaches are limited to periodic and independent task sets and a general framework is lacking. 3. LOW POWER SCHEDULING In this section, we describe the three steps of proposed low power scheduling approach in detail. 3.1 STEP 1: PRIORITY LIST GENERATION Each application-specific function executed by an embedded system is made up of several sequential and/or concurrent tasks, I = {T 1,T 2,,T N }, arranged in the decreasing order of their statically assigned priorities. The following parameters are defined for each task T i. p i period. e i execution time. D i Deadline φ i phase T i Set of tasks with priorities i or higher than i. The specification of real-time embedded systems will be typically in the form of task graphs. Task graphs can be periodic or aperiodic. A hard aperiodic task graphs can arrive at the embedded systems for execution at any time and an execution slot must be available at the required time to meet the deadline. We will formulate this as an execution slot size estimation and allocation problem. The worst-case execution time of a hard aperiodic task graph and the interval between the two successive execution time slots will be determined. Basically, we model a periodic execution slot for the corresponding hard aperiodic task graph Execution Slot Size Estimation Let a hard aperiodic task graph T j have m tasks, deadline dl j (relative to the earliest start time of the task graph), minimum inter-instance time interval τ j. Let π ij represents the execution time of task i in aperiodic task graph T j. The total time taken to execute task graph T j is given by µ j = i=1 Σ m π ij µ j = 0 if µ j > dl j µ j, can be seen as a large enough interval to allow the execution of T j, so that its deadline is guaranteed to be met. The maximum time interval between the successive execution slots of an aperiodic task graph T j must be dl j -µ j if dl j -µ j < τ j τ j if dl j -µ j τ j to guarantee that all the deadlines will be met. Hence, we can model a periodic task with period equal to min{dl j -µ j, τ j }, deadline equal to dl j and execution time of µ j for every aperiodic task graph T j Handling of Soft Aperiodic Jobs Each newly arrived soft aperiodic task will be placed in a queue. An aperiodic job-scheduling algorithm is optimal if it minimizes either the response time of the aperiodic job at the head of the aperiodic job queue or the average response time of all the aperiodic jobs for the given queuing discipline. A deferrable server with period P s and execution budget E s is used to serve the soft aperiodic tasks. The execution budget of the server is consumed at the rate of one per unit time whenever the server executes. The execution budget of the server is set to E s at time instants kp k, for k =0,1,2, Resultant System Model The input specification in the form of aperiodic and periodic task graphs has been transformed in to a set of periodic task graphs. (The periodic task graph modeled for every aperiodic task graph effectively contains only one periodic execution slot. When the aperiodic task graph arrives, the scheduler schedules the constituent tasks in the execution slot according to their precedence constraints). Algorithm 1 is used to generate the priority list, which specifies the priorities of the tasks in all task graphs, given the list containing the resultant periodic task graphs. The priorities are generated in a way that satisfies the deadlines and precedence constraints. Algorithm 1 : Generate the priority list 1: Input: A list G containing the periodic task graphs 2: Output: A priority list σ with the tasks arranged in decreasing order of priorities. 3: While (G) 4: Initialize ActiveList A to NULL 5: Remove the task graph T with the smallest period from G. 6: Add the Level 1 nodes of T to ActiveList A 7: If A=0 then return σ. 8: While A 0 9: Remove the node n in A with least slack time. 10: Append n to σ. 11: While (successor(n) 0) do 12: v := extract one node from successor(n) 13: Update the activelist A with node v. 14: End While. 15: End While 16:End While 17: Output σ.

3 3.2 STEP 2: MINIMUM SPEED DETERMINATION DEFINITION : A level-π i busy interval (t 0,t] begins at an instant t 0 when (1) all jobs in T i released before the instant have completed and (2) a job in T i is released. The interval ends at the first instant t after t 0 when all the jobs in T i released since t 0 are complete. In other words, in the interval (t 0,t], the processor is busy all the time executing jobs with priorities π i or higher, all the jobs executed in the busy interval are released in the interval, and at the end of the interval there is no backlog of jobs to be executed afterwards. Hence when computing the response times of jobs in T i we can consider every level-π i busy interval independently from other level-π i busy intervals. We say that a level-π i busy interval is in phase if the first jobs of all tasks that have priorities equal to or higher than π i and are executed in this interval have the same release time. Otherwise, we say that the tasks have arbitrary phases in the interval. The schedulability analysis for a fixed-priority scheduling is based on the Critical Instant Theorem [17] that says that if a task meets its deadline whenever the task is requested simultaneously with requests for all higher priority tasks then the deadline will always be met for all task phasing. In order to determine the lowest possible speed for each task T i we will first determine, initially starting with T 1, the factor by which every level-π i busy interval can be stretched with out causing the tasks in T i to miss the deadline. A minimum among them is chosen which will become the limiting factor and the busy interval, level-π k, that corresponds to this is a limiting busy interval. All the tasks in the system were extended by this limiting factor consequently scaling down the voltage by this factor. The above procedure is repeated on busy starting from π k+1. This procedure is repeated until the limiting busy interval is π n at which point the scaling factor for all tasks in the system will be determined. Algorithm 2 presented below shows in detail how the scaling factor thereby the voltage reduction is determined for each task in the system. Algorithm 2: Determination of Minimum Speed of each task 1: Input: A prioritylist of tasks in the decreasing order of their priorities. 2: Output: A voltagefactor table containing tasks and their corresponding scaling factor. 3: limit_interval 1; 4: voltagefactor[i] 1; i =1,2,..n. 5: while limit_interval n 6: for i limit_interval to n do 7: determine the response time of the first job in task T i according to t l+1 = e i + k=1 Σ i-1 t l /p k e k,. Solve this iteratively until t l+1 = t l. let this final value of t l+1 be W i,1 (t). 8: if ( W i,1 (t) p i,1 ) && ( W i,1 (t) D i,1 ) then 10: S i = { jt k k =1,2, i; j =1,2, min(d i,1,p i,1 ) 11: scale[i] = max{s i,j / k=1 Σ i e k S i,j / T k }, j =1,2,.. S i 12: else if ( W i,1 (t) p i,1 ) && ( W i,1 (t ) > D i,1 ) then task set is not schedulable. 13: endif 14: if (W i,1 (t) > p i,1 ) then 15: compute the length of in-phase level-π I busy interval by solving the equation t = k=1 Σ. i t/p k e k iteratively starting from t (1) = k=1 Σ i e k until t l+1 = t l. The solution t l is length of level-π I busy interval. 16: for j 1 to t l /p i do 17: find response time W i,j of j th job by solving the equation t = W i,j (t+(j-1)p i )-(j-1)p i. Where W i,j ( ) is given by W i,j (t) = je i + k=1σ i-1 t/p k e k. 18: if W i,j (t) ( (j-1)p i, (j-1)p i + D i ] then continue; 19: else task set is not schedulble 20: end for 21: scale[i] = min{w i,j } for j =1,2, t l /p i 22: endif 23: endfor 24: limit_factor min{ scale[i] }. i = limit_interval, n. 25: limit_index = { i limit_factor = min { scale[j] }, j =limitinterval,..n } 26: voltagefactor[j] voltagefactor[j] * limit_factor, j = limit_interval, n. 27: limit_interval limit_index 28: endwhile 29: output voltagefactor 3.3 STEP 3: DYNAMIC POWER MANAGEMENT The tasks are scheduled according to their priorities at the voltages determined during step2. Even then there will be idle intervals that arise from two sources. The first source is idle intervals that are inherently present in fixed-priority scheduling because of different period of each task. The second source is runtime variation of execution time of each task. The scheduler makes use of the idle intervals by dynamically managing the processor power consumption. We use a pre-computed table that specifies the cost (overhead) associated with moving the processor from one power mode to another. Based on this matrix the dynamic power manager determines the power mode to which the processor can be moved and the interval for which the processor should be in that mode so that maximum power saving can be obtained. Algorithm 3 presented below shows how the idle intervals are exploited. For this purpose, we assume that all ready tasks are kept in the readyqueue and the task that is being executed as activetask. Algorithm 3: Dynamic power management 1: Input: signal for the new task arrival or completion of the existing task and voltagefactor table. 2: Output: task to be scheduled or power mode for the idle interval.

4 3: if (newtask has arrived) 4: if priority(newtask) > priority(activetask) then 5: scale the processor to the voltage level given by voltagefactor[newtask]. 6: switch the tasks. 7: endif; 8: else insert the task in readyqueue 9: endif 10: if (activetask has finished) then 11: if (readyqueue is empty) then 12: determine the length of idle interval 13: determine the optimal powermode 14: endif 15: else 16: pick the task with highest priority among all the ready tasks. 17: lookup the index for this task in the voltagefactor table and scale the processor to that level. 18: endif; 19: endif. 20: output the task to be scheduled or nothing 4. ILLUSTRATIVE EXAMPLE In this section we illustrate the working of the three-step approach by applying it to the example task set shown in Figure 1. The task graphs represented by Figure 1(a),(b),(c) are periodic and Figure 1(d) represents aperiodic task graph. The execution times, periods and deadlines are listed in Table 1 and Table 2. T2 T1 (a) Period = 20msec T7 T8 T3 (b) Period = 50msec T10 T5 T9 T4 T6 T11 (c) Period = 70msec (d) Aperiodic Graph, τ = 110msec Figure 1: Periodic, Aperiodic Taskgraphs Task Period Execution time Table 1. Period, Execution time, Deadlines for task graphs in Figure 1(a), 1(b), 1(c). Task τ,min. Inter instance arrival Execution time Deadline T 9 110msec 5msec 110msec T msec 3msec 110msec T msec 2msec 110msec Table 2. τ, Execution time, Deadline for task graphs in Figure 1(d) Periodic behavior is modeled out of an aperiodic task graph shown in Figure 1(d) by creating an execution slot (sum of the execution times of individual tasks) of length 10 msec which repeats at an intervals of 100msec. Let us call this task as T 9. The resultant task set is shown in Table 3. Task Period Execution Deadline time Table 3. Transformed System Model Deadline T 1 20msec 3msec 20msec T 2 20msec 2msec 20msec T 3 20msec 1msec 20msec T 4 50msec 5msec 50msec T 5 50msec 3msec 50msec T 6 50msec 2msec 50msec T 7 70msec 5msec 65msec T 8 70msec 1msec 70msec T 1 20msec 2msec 20msec T 2 20msec 2msec 20msec T 3 20msec 1msec 20msec T 4 50msec 5msec 50msec T 5 50msec 2msec 50msec T 6 50msec 3msec 50msec T 7 60msec 2msec 55msec T 8 60msec 1msec 60msec T 9 100msec 10msec 110msec Step 1: Priority List Generation Algorithm 1 is applied to the task set in Table 3 and the priority list that was generated is as listed in Table 4. The utilization of the task set is calculated as U = i=1 Σ n (e i /T i ). For the task set the utilization was calculated to be The schedulable utilization of the algorithm for n tasks is given by n(2 1/n-1 ) and is calculated to be 0.88, since some of the tasks are simply periodic. So, the limiting factor is 1.49.

5 Task num T 1 1 T 2 2 T 3 3 T 4 4 T 5 6 T 6 5 T 7 7 T 8 8 T 9 9 Table 4. Priorities of tasks Priority Step 2: Minimum Speed Determination The Step 2 takes as its input a priority list generated by the Step 1 and finds the lowest voltage at which each job can be executed as is shown in Table 5. Task T 9 can be scaled by a factor of But the limiting scaling factor is 1.49 because of schedulable utilization. So, the scaling factor for T 9 becomes The processor is put to a minimum voltage level supported that is greater than the calculated voltage. The maximum power reduction obtained due to step 2 is approximately 51% Task num Voltage reduction factor T T T T T T T T T Table 5. Voltage reduction Table Step 3: Dynamic Power Management Power savings using the Step 3 are estimated by simulating the proposed approach on the schedule generated by the Step 2. The number of machine cycles required to move the processor between the various power modes of Strong ARM processor are stored in a table. For the example task set the simulation for StrongARM resulted in a 11.2% additional power saving taking the total power saving to 62.2%. 5. EXPERIMENTAL RESULTS In this section we have compared the performance of proposed approach with the approaches presented in the [6], [9] and [13]. We have used benchmark tasks from popular application domains that are taken from [14], [15] and [16]. The comparison of the results on various benchmarks is as shown in Table 6 indicate that our approach yields superior results compared with other known approaches. Proposed [6] [13] [9] approach CNC [16] 71.1% 40% 62% 35% INS [15] 29.3% 27% % AVIONICS[14] 15% 9% - - Table 6. Comparison of Power Savings on Various benchmarks 6. CONCLUSION In this paper we presented a three-step approach for low power scheduling of embedded real-time systems. The scheduling algorithm presented is capable of handling both aperiodic and periodic task sets. Step 1 is used to prioritize the tasks while guaranteeing the deadlines and precedence constraints. Step 2 is used to determine the lowest possible voltage at which each task can be run. Step 3 is used to exploit the idle intervals that arise during run time. The proposed approach yields better results compared with the other known approaches. 7. REFERENCES [1] K.Lahiri, A.Raghunathan, S.Dey and D.Panigrahi, "Battery- Driven System Design: A New Frontier in Low Power Design," In Proc. Of the Intl. Conf. on VLSI Design, pp , Bangalore, India, January [2] J.Luo and N.K.Jha, Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed realtime embedded systems, In Proc. of the Intl. Conf. Computer-Aided Design, pp , SanJose, CA, November [3] Y.Shin and K.Choi, Power conscious fixed priority scheduling for hard real-time systems, In Proc. 36th Design Automation Conference, pp , New Orleans, LA, June [4] G.Fohler, Joint scheduling of distributed complex periodic and hard aperiodic tasks in statically scheduled systems, In Proc. of 16th Real-time Systems Symposium, pp , Pisa, Italy, December [5] J.Luo and N.K.Jha, Battery-Aware static scheduling for distributed real-time embedded systems, in Proc. Design Automation Conf., pp , New Orleans, LA, June [6] Y.Shin, K.Choi and T.Sakurai, Power Optimization of Real- Time embedded systems on variable speed processors, In Proc. of IEEE/ACM International Conference on Computer Aided Design, pp , SanJose, CA, Nov [7] T.Okuma, T.Ishihara and H.Yasuura, Real-Time Task Scheduling for a Variable Voltage Processor, Proceedings of the 12th International Symposium on System Synthesis, SanJose, CA, November [8] J.Pouwelse, K.Langendoen and H.sips, Energy priority scheduling for variable voltage processors, In Proc. of the Intl. Symposium on low power electronics and design, Huntington Beach, CA, August 2001.

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