Wafer Level Molded DDFN Package Project Duane Wilcoxen

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1 Wafer Level Molded DDFN Package Project Duane Wilcoxen

2 Definition of DDFN (Encapsulated CSP) DDFN package basically is a CSP device with an epoxy coating on all (or most) of the device sides for added protection. The epoxy encapsulation covers the silicon device, but leaves exposed solderable connections for the assembly process. The solderable connection may be copper pads or solder bumps, depending on the package process technology. The final device structure is an epoxy brick with solderable contacts like a chip resistor for flip chip assembly. CSP Bumps Section Silicon Device Epoxy Encapsulation

3 Motivation for DDFN Package DDFN packaging eliminates requirements for wire bonds. All connections are direct solderable metal contacts between die and board Higher Reliability. The epoxy encapsulation provides mechanical protection for the device Better handling protection at assembly. DDFN device structure is similar to a standard chip resistor Known assembly requirements. The DDFN process is ideally suited for small die that are difficult to manage in a wire bonded assembly due to the pick and place requirements of the small die.

4 Example DDFN Package Outline DDFN Package Characteristics: Top View Bottom View 1. Chip scale device fully encapsulated with epoxy. 2. Minimal overall package height. 3. Solderable metal of contact points above die surface. 4. Epoxy covering at least five of six sides of device. Structure Cross Section

5 Example 0603 DDFN Package E Dimension b Metal bump standoff height D L Die thickness Marking depth D 0.62+/ E 0.32+/ b 0.22+/ L / Die Thickness Gold Bump Standoff Height Backside Epoxy Thickness Total Thickness (Max.) 0.200~0.250mm 0.010~0.030mm 0.025~0.030mm 0.250~0.275mm

6 D-DFN0603 vs Std. DFN0603 Top View Bottom View Top View Bottom View Structure Cross Section Structure Cross Section D-DFN0603 DFN0603 D-DFN eliminates WIRE connection of DFN device to improve performance and reduce manufacturing variability.

7 Transferring an Existing Design into Wafer Level DDFN DDFN package sizes can be standardized to create specific final package dimensions with smaller die inside. Device designs would include extra silicon to fill un-usable area required for epoxy molding. For a given DDFN Package Design, there is a maximum available die space for layout, with 0.05mm of layout area on each side of the die required for scribe lane trenching and epoxy fill for side walls. DDFN device structure is an epoxy brick with solderable metal connections spaced for flip chip assembly.

8 Advantages of Wafer Level Encapsulation Wafer level processing leverages economies of scale manufacturing for maximum process UPH with minimal component level processing. Only component level operation in flow is placement of final package into carrier tape. Micron level resolution of surface dimensions using wafer level photo processing techniques for better dimensional control. Singulation dicing process is carried out with single scribe lane cut with precise control of epoxy sidewall thickness. Precise control of materials usage and improved efficiency at wafer level with reduced waste.

9 DDFN Final Package Dimensions Final Package Size = 0.62X0.32mm Die Sawing Process To Be Specified with MAXIMUM 40um Kerf

10 DDFN Design Dimensions Nominal Dimensions of DDFN Features DDFN DDFN DDFN DDFN DDFN DDFN DDFN DDFN Final Package Size um 1000 X X X X X X X X 540 Final Package Height um Chip Size (Max. Layout Area) um 890 X X X X X X X X 430 Stepping Distance um 1040 X X X X X X X X 580 Effective Scribe Width um Final Bump Size um 480 X X X X X X X X X X X X 150 PV Opening Size um 435 X X X X X X X X X X X X 105 Estimated Die per Wafer (150mm wafer) Remarks: These values are from the DDFN Design Specification for the final targeted values. Samples will be created to confirm the final results and the tolerance levels for each of the parameters.

11 Wafer Level DDFN Process Flow Process Step Resp. Comments Front End Device Fabrication Diodes Production processing on 150mm or 200mm wafers Thick Plated Ni Metal Bumps on Bond Pads K-Bump Plated 30um Ni Bump Trench Cut Wide Scribes (140um wide / 300um deep) K-Bump Open gaps between die for epoxy fill No split All wafers have 150um scribe Compression Mold Epoxy Material K-Bump Epoxy surface coverage to fill trenches and completely cover Ni bumps Device Side Epoxy Surface Removal K-Bump Face grind of epoxy to expose Ni pads and provide flat wafer surface Re-Plate NiAu Surface Connection K-Bump Plate solderable metal on bump surface Substrate Backside Grind to 10mils K-Bump Post grind substrate thickness of 250um Backside Epoxy Lamination K-Bump Backside Epoxy Lamination Mold to 25um Final Electrical Test / Laser Mark CAT Wafer Level E-Test and Laser Marking Wafer Saw / Dicing CAT Singulation Process Tape and Reel CAT Back End process can be performed as standard CSP product or using a DFN component level operation for test, marking and TnR.

12 K-Bump E-CSP Operation: Wafer Level Molded DDFN Package K-Bump Wafer Level DDFN Process Flow ENiG Plating (K-Bump) Trench Partial Saw (K-Bump) Epoxy Mold (K-Bump) Polish top-side to expose bump (K-Bump) TnR w/dfn0603 setup (SAT or CAT) Singulate (SAT or CAT) Test, Laser Mark (SAT or CAT) Back-side Epoxy Coat (K-Bump) Back-side Grind (K-Bump)

13 WLM DDFN Production Module Step Tool Process Incoming Inspection Olympus Microscope Semi-Automatic Thick Ni Plating Ni Plate System Automatic Trench Cut Disco DAD3350 Saw Automatic Epoxy Mold Front Apic Yamada Mold Automatic Mold Cure Blue M Oven Semi-Automatic Grind Face Side Epoxy Disco DFG8540 Automatic ENiG Re-Plating NiAu Plate System Automatic Tape Front-side Laminator Automatic Grind Back Side Silicon Disco DFG8540 Automatic Stress Relief HF Dip Tank / IPA Dryer Automatic Detape Front-side Delaminator Automatic Epoxy Laminate Back Lintec 3500F/8DBS Automatic BSL Cure Blue M Oven Semi-Automatic Ship Semitool SRD Semi-Automatic Supporting metrology equipment are not included in the flow. These are not required to be automated. Manual processes are prone to high breakage due to the Manual Handling aspect.

14 DDFN Project Accomplishments DDFN Design Guide Established: Device specs completed for packages of DDFN0505-3, DDFN0606-3, DDFN0603-2, DDFN0806-3, DDFN1006-3, DDFN Thick ENIG Bump Process Defined: 30um NiAu plating process setup and verified for DDFN designs. Trench Dicing Process Defined: Trench dicing process setup and defined for 140um wide trench at 300um depth. Adequate process control has been demonstrated for epoxy trench formation. Process optimization to be completed to improve UPH of process. Face Side Epoxy Mold Operation Defined: Face side epoxy molding operation has shown to be capable with adequate repeatability. Epoxy dispense control needs additional development to improve accuracy and repeatability. Dispense volume targets have been established for different device designs. Face Side Polish Process Defined: Face side epoxy polish process has shown to be capable to clear epoxy mold residue while maintaining NiAu bump surface condition. Process optimization to be completed for volume production operations.

15 DDFN Standard Reliability Testing: Full gamut of standard reliability testing completed on SBR2U20ECSP device. HS / HTRB 1000hrs at 150C Pressure Cooker Test (component and board level) 96hrs Temperature Cycle: >2500 cycles at -55C to 150C Solderability Testing No Failures DDFN Reliability Accomplishments DDFN Automotive Level Reliability Testing: Automotive level reliability testing completed on BJT0806ECSP device. HS / HTRB 1000hrs at 175C Pressure Cooker Test (component and board level) 96hrs Temperature Cycle: 1000 cycles at -55C to 175C Solderability Testing No Failures

16 DDFN0505 Example: MOSFET DM2200UFS Page 16

17 DDFN0505 Example: MOSFET DM2200UFS Page 17 Top View Top View Final Bump Surface Bottom Side View Package Back Side

18 WLM DDFN Process Flow Back End Diodes DDFN Back End Operation: Wafer Level Operations Electrical Test / Back Side Laser Mark Singulation Process Mount on Dicing Frame and Wafer Saw Dicing Final Visual Inspection Pick and Place Operation Place Die in Carrier Tape Back End operation flow will be improved in near future by replacing wafer level test and laser marking with component level processing using an automated small die handling system to improve process UPH and reduce equipment set. Note: Patents Pending on DDFN process flow and device designs.

19 WLM DDFN Process Flow Back End Process Sequence Options for DDFN Back End Standard Flow Current Equipment Small Die Handler Flow Equipment Wafer Level Electrical Test TSK Handler + SineTest or Juno Tester Dicing Frame Mount Longhill Mounter Wafer Level Back Side Laser Mark Dicing Frame Mount EO Technics CSM2000 Longhill Mounter Saw Dicing Singulation Component Electrical Test Disco DFD6341 Saw Dicing Singulation Wafer Level Visual Inspection Disco DFD6341 Camtek Falcon Component Back Side Laser Mark Component Visual Inspection Small Die Handler Ueno Seiki RT20 Pick and Place into Carrier Tape Muehlbauer DS20000 Pick and Place into Carrier Tape Small Die Handling Tool performs test, laser mark, inspection and TnR process. Significantly reduces equipment set for back end process. Visual inspection on handler includes 5 side package inspection. Die pick up directly from dicing film frame reducing issues with bowl feed die damage.

20 WLM DDFN Process Flow Back End Small Die Component Handler 1.Laser alignment inspection 2.Laser marking 3.Mark inspection 4.Pick up TEST2 Test 2 Xyθ alignment TEST1 Ueno Seiki RT20 System Capable of Handling Die to 400X200um Test 1 Xyθ alignment PICKUP Xyθ alignment unit 5S inspection Wafer Ring Auto Loader MAX12 (Option) 6 Rank Bin Taping (Alignment function) Wafer Ring Holder UENO SEIKI CO., LTD.