The Development of a Novel Stacked Package: Package in Package

Transcription

1 The Development of a Novel Stacked Package: Package in Package Abstract Stacked die Chip Scale Packages (CSPs) or Fine-pitch BGAs (FBGAs) have been readily adopted and integrated in many handheld products, most notably cellular phones. Such stacked die CSPs are especially useful to reduce the cost, weight, and size of the memory devices needed to support the increased features and applications in cellular phones today. In addition, they have been used extensively to integrate some logic and analog functions. In these cases, the die stacked in these CSP packages can be tested at the wafer level such that the final stacked die package electrical yield is well over 95%. This high final test yield and fairly low die cost makes such packages economical. However, combinations of devices to be integrated or stacked within a single CSP, in order to meet the needs of next generation cellular phone users, often require the die be fully functionally tested prior to packaging them together in order to assure good final test yield and cost. Known Good Die (KGD) are often difficult to source for such applications and are not always cost effective. In fact, a packaged and tested device can be less cost than a KGD. Therefore, it is desirable for a number of reasons to stack or integrate tested good packages within a CSP to meet the needs of such applications. This paper outlines the development of a novel stacked package CSP, called Package in Package (PIP). In this PIP package, tested good packages are stacked and wire bonded much like the die in a conventional stacked die CSP. The same basic packaging infrastructure and package testing infrastructure is utilized. This paper shows the package level reliability of the PIP package is the same as the stacked die package of today. Thus, there is no compromise in reliability and such PIP packages can meet lead free reflow conditions Stacked die CSPs have come to the fore for applications that require increased functionality, smaller form factors, and lighter weight. Stacked die CSP packages with two, three, four, and even five functional die are now available and in production. Primarily, memory die are stacked that are lower cost and can be well tested in wafer form prior to assembly to assure a cost effective final test yield. If a logic or ASIC die is stacked, it is usually paired with another device that can be tested good in wafer form, such that the final test yield is basically unaffected. However, the next generation of handheld products, most notably cellular phones, require significant amounts of high speed memory, such as SDRAM or DDR, to be paired with the micro processor or ASIC. This type of high speed memory cannot be well tested easily in wafer form. Known Good Die (KGD) is needed for such devices, but KGD is costly and has limited availability and supplier base. In most cases, a tested good package is less Flynn Carson and Young-Cheol Kim ChipPAC Incorporated Kato Road Fremont, CA (510) , flynn.carson@chippac.com costly and has less supply issues than a KGD. Thus, the need for a package that stacks good packages as opposed to wafer probed dice is evident. Introduction The challenge is to stack tested good packages in a small, lightweight, reliable, and cost effective package suitable for handheld applications. The demands of handheld products moving forward are always forcing more functionality into a smaller footprint and lower profile package. Stacking die in a package will always produce the smallest and most cost effective package. But what if the same principles and infrastructure were used to stack packages instead? Instead of stacking die themselves, the die could be housed in very thin Land Grid Array (LGA) type packages and stacked within the package like die. The means of interconnecting these tested good packages stacked within the package would be wire bonding, just as die stacks are interconnected today. The resultant package stack would be encapsulated or overmolded just as a die stack package is today. This final package would be no different in form, fit and function than a current die stack. This paper will describe the development of a novel stacked die package called Package in Package (PiP), in which the bottom die in the package stack is assembled and encapsulated, such that it could be fully functionally tested, and then a thin tested LGA package is stacked on top of this base package, wire bonded, and finally encapsulated like a conventional stacked die package. The package level reliability of this PiP package will be shown to be equivalent to that of a stacked die package and be able to meet Lead-free moisture sensitivity and reliability levels. PiP Structure and Assembly Process The Package in Package structure is shown in Figure 1 and 2. These structures shows two packages stacked within a package. However, it would be possible to stack more than two packages within a package at the expense of increasing package height and complexity. At this time, two packages stacked within a package would be the preferred structure to marry an application ASIC or microprocessor with a high speed memory die or die stack. Figure 1: PiP with Single Die LGA /04/$20.00 c2004 IEEE 2004 IEEE/SEMI Int'l Electronics Manufacturing Technology Symposium

2 Figure 2: PiP with 2 Die + 1 Spacer LGA As is evident in Figures 1 and 2, the bottom die is die attached and wire bonded to the bottom or base substrate. This assembled bottom die can then be individually encapsulated such that it can be fully functionally tested if required. Such encapsulation or overmolding can still be done in the array strip format used to economically mass produce such CSP or Fine-pitch Ball Grid Array (FBGA) packages today. Top Center Mold Gate (TCMG) molding equipment and techniques are required to transfer mold such individual units without mold gates or runners (mold gates or runners would interfere with placement of bond fingers around the periphery of the mold cap that enable interconnect to the top package). Such overmolding enables the strip to be handled such that each unit could be fully tested. Of course, each unit would have to be electrically isolated in order to be suitable for electrical testing, but this can easily be achieved by etching back the plating or bus bar at the edge of each individual unit. It should be noted that more than one die could be stacked within this lower or base package and tested good prior to stacking an LGA on top. Figure 3: PiP LGA with Bond Finger at Periphery The LGA package that is stacked on top of the encapsulated base package is actually an inverted LGA. Figure 1 shows a configuration where one die is stacked within the LGA and Figure 2 shows a configuration where two die with one spacer die in between could be stacked within the LGA. Such die would typically be memory die. These LGA packages would be as thin as current technology allows in order to keep the overall package as thin as possible. The LGA would be assembled like a current single or stacked die CSP package is today, saw singulated, and then place in trays or tape in reel such that they could be tested using conventional handlers, sockets, and test equipment. Figure 3 shows that these LGA packages would have an array of lands such that they could be tested with conventional test sockets. However, it can be seen that each ball pad or pin is also connected to a bond finger or pad at the periphery of the LGA substrate, this is to enable the wire bond interconnect to the base substrate as shown in Figures 1 and 2. This wire bond interconnect to the base substrate is a high density interconnect method that can be done in a small amount of space, thus saving package size and cost. After the inverted LGA package is attached to the base package and wire bonded to the base substrate, the package is encapsulated with mold compound using a conventional transfer mold process. Again, the packages are arrayed on a strip such that they have the greatest density per strip. After this final encapsulant mold process, the units would have solder balls mounted and be saw singulated such that final package is identical to a stacked die CSP or FBGA. The package is now ready for final test. PiP Test Vehicle A development test vehicle was chosen based on an existing stacked die product which includes a Digital Signal Processor (DSP). This 13x13mm 341 ball package has 0.5mm solder ball pitch and is in mass production with Leadfree solder balls today. This package has been fully characterized and qualified at both the package and second (board) level. In die stacked form this package is 1.2mm thick (maximum) and can meet Level 2a Moisture Sensitivity Level (MSL) with 260 C Lead-free reflow temperature (maximum). The current stacked die package has also passed board level temperature cycling test (no failures before 1000 temperature cycles with Lead-free ball) and drop shock test per customer specification. Two basic package configurations were assembled, characterized, and tested at the package level. The first configuration is like that of Figure 1 with a single die stacked in the LGA. The overall package thickness of this configuration is 1.4mm maximum. Table 1 shows the breakdown of the package thickness. As can be seen, 0.075mm die thickness and very thin substrate, mold cap, and loop height technology are required to execute such a package. Such technology is also qualified and required for the five and six die stack packages being qualified and produced today. The second package configuration developed is like that of Figure 2. For this configuration, the maximum package height is 1.6mm and the breakdown of thickness is detailed in Table 2. The base package substrate and LGA package substrate was designed to form a daisy chain by use of a daisy chain die wire bonded in each package. Thus the final assembled package can be second level tested on a test board (board level temperature cycle, drop test, and bend test) after package level reliability is confirmed.

3 Table 1: PiP with Single Die LGA Thickness Option 1 Mold cap clear. LGA thickness Substrate 0.16 Moldcap Die thickness Epoxy D/A LGA adhesive ASIC mold cap Die thickness 0.10 PiP mold cap Substrate thick (2L) Solder ball collps (0.3/0.5 ball/pitch) BGA + LGA (0.275 pad) was based on current package in mass production. The actual LGA size required to accommodate high speed memory is in the 8mm to 12mm range and the base or final PiP package size will be in the 12mm to 16mm range. For this test vehicle a two layer laminate based substrate is used. For actual PiP packages two layer or thin four layer substrates may need to be used in order to accommodate all the routing, considering that the ball pad pitch is commonly 0.5mm pitch and the substrate technology is through hole vias to reduce cost. If the bottom ASIC or microprocessor is designed to accept routing in consideration of the LGA on top (memory nets strategically inputted on one or two sides), then the base substrate can be reduced to two layers to reduce cost and thickness. 13.0mm 11.0mm 8.0mm Total pkg thick nom Table 2: PiP w/ 2+1 Stack LGA Thickness Figure 4: PiP Test Vehicle Base Package Option 2 Mold cap clear. LGA thickness ( 2+1) Substrate Moldcap 2nd Die Film D/A3 Silicon spacer Film D/A2 1st Die Epoxy D/A 1 LGA adhesive ASIC mold cap PiP mold cap Substrate thick. Solder ball height Total pkg thick. BGA + LGA(2+1) (0.275 pad) 1.53 nom Assembly, Characterization, and Reliability of PiP LGA Figure 5 shows the bottom die wire bonded during the assembly process of the test vehicle. Figure 6 shows the bottom die after encapsulation with the LGA package attached to the top and wire bonded down to the base substrate. A cross section of the final encapsulated test vehicle package for the second configuration can be seen in Figure 7. The reliability target for the PiP package is the same as an equivalent die stack package. Thus, MSL Level 2a at 260 C Lead-free reflow temperature is required. After MSL, the package must also be able to meet the following reliability tests: 1000 cycles of -65 C to +150 C (Condition C ) temperature cycle; 168 hours of 121 C/ 100% Relative Humidity (RH)/ 2 atmospheres Pressure Cooker Test (PCT); 1000 hours of 150 C High Temp Storage; and 1000 hours of 85 C/85%RH unbiased Temperature Humidity Bake (THB) test. Figure 4 shows the bottom die size used for the test vehicle is 8x8mm and bottom mold cap size is 11x11mm. This allows for one row of bond fingers on each side of the die. At 0.125mm bond finger pitch, 280 wire bonds can be accommodated on the bottom die. The LGA package used for this test vehicle is 8x10mm and has 88 leads arrayed on the substrate. 5x6mm size die are used within the LGA package. As mentioned before, this package size for this test vehicle

4 Table 3: Base PiP Package Reliability Result MSL Scanning Acoustic condition Microscope (SAT) Result L C IR 0/33 L2AA + 260C IR 0/33 L C IR 0/33 Figure 5: Bottom Die Wire Bonded SAT Result MRT + IR temp PCT T/C "C"(-65C to 150C) condition 96hrs 168hrs 500cycles 1000cycles L C IR 0/17 0/17 0/16 0/16 L2AA + 260C IR 0/16 0/16 0/17 0/17 L C IR 0/17 0/17 0/17 0/17 Figure 6: Molded Base Package with LGA Stacked and Wire Bonded Figure 7: Cross Section of PiP (2+1 Stack in LGA) In order to meet the reliability target the base package and the two different LGA package configurations were evaluated separately to assure reliability before the final PiP package reliability was evaluated and confirmed. For MSL test, although the target is Level 2a with 260 C reflow, Level 2 (260 C) and Level 3 (260 C) were also tested as margin test. Since the PiP package utilizes the same infrastructure and basic construction as stacked die package, materials proven for advanced die stack packages were utilized for the PiP test vehicle assembly and reliability evaluation. The reliability result of the base package is shown in Table 3. Using current proven material sets produced a good MSL result with the 0.30mm thick mold cap and special runner-less transfer molding process. One of the potential risks for the LGA substrate is the use of 0.06mm core two layer laminate substrate with overall thickness less than 0.16mm. Such thin laminate substrate technology has only recently become available from some substrate manufacturers to support volume production. Therefore, two different substrate suppliers were evaluated for each different LGA configuration to determine if there is any difference in reliability or assembly capability. Table 4 shows the result of MSL tests for single die and two die with one spacer configuration. Level 2a and even Level 2 MSL with 260 C reflow can be met. Table 5 shows the reliability result for the same LGA legs as Table 4. There was some difference seen in the Scanning Acoustic Transmission (SAT) check for delamination for each substrate supplier. There was some issue applying zero delamination criteria after 168 hours of PCT with Supplier A. However, the nature of this delamination is recoverable after corrective action from supplier and is not considered a major concern. The temperature cycle result after 1000 cycles was clean for all legs. Based on the reliability results of the base package and LGA tested separately, each PiP configuration was assembled and subjected to final package level reliability tests. The result of the package level test is summarized in Table 6. Each configuration showed the same result and passed MSL Level 2a (260 C) and subsequent internal qualification reliability tests without any failures. Units were electrically tested for opens and shorts as well as tested for delamination using SAT.

5 Table 6: PiP Reliability Summary Table 4: PiP LGA MSL Performance SAT inspection Leg # Die size Structure mold cap PCB MRT Result / thickness (Die) thickness supplier + IR temp 1-1 5X6mm / 3mil mm A L C IR 0 / X6mm / 3mil mm A L2A + 260C IR 0 / X6mm / 3mil mm A L C IR 0 / X6mm / 3mil mm B L C IR 0 / X6mm / 3mil mm B L2A + 260C IR 0 / X6mm / 3mil mm B L C IR 0 / X6mm / 4mil 1 0.3mm A L C IR 0 / X6mm / 4mil 1 0.3mm A L2A + 260C IR 0 / X6mm / 4mil 1 0.3mm A L C IR 0 / X6mm / 4mil 1 0.3mm B L C IR 0 / X6mm / 4mil 1 0.3mm B L2A + 260C IR 0 / X6mm / 4mil 1 0.3mm B L C IR 0 / 80 Table 5: PiP LGA MSL + PCT and T/C Performance SAT Inspection Leg MRT PCT Temp Cycle Cond. "C" + IR temp 168hrs 1000x Zero del Jedec Zero del Jedec 1-1 L C IR 1/40 0 / 40 0/40 0/ L2A + 260C IR 0/40 0 / 40 0/40 0/ L C IR 4/40 0 / 40 0/40 0/ L C IR 0/40 0 / 40 0/40 0/ L2A + 260C IR 0/40 0 / 40 0/40 0/ L C IR 0/40 0 / 40 0/40 0/ L C IR 27/40 0 / 40 0/40 0/ L2A + 260C IR 1/40 0 / 40 0/40 0/ L C IR 35/40 0 / 40 0/40 0/ L C IR 0/40 0 / 40 0/40 0/ L2A + 260C IR 0/40 0 / 40 0/40 0/ L C IR 0/39 0 / 39 0/40 0/40 Test Item MRT 168hrs 336 hrs 500 hrs, cyc 1K hrs, cyc MRT L2a, 260C 0/128 PCT 0/32 0/32 T/C "C" 0/32 0/32 85C/85%RH 0/32 0/32 HTS (150C) 0/32 0/32 Conclusions In order to address the needs of integrating devices of higher value and test complexity in order to assure cost effective final test yield, the Package in Package was conceived as a way to leverage existing die stacking package know-how and advantages. Instead of stacking probed good die or Known Good Die, thin Known Good Packages were stacked within the packages, interconnected by means of wire bonding, and then encapsulated. The advantages of saving package size, thickness, and cost can be obtained by utilizing such an approach. The concern is the number of interfaces added within the package mold cap which may impact reliability. However, development of this PiP package using a test vehicle similar to an existing product in mass production with a known reliability history showed that the PiP version of such package has equivalent package level reliability to the stacked die version. Thus, by utilizing existing material sets and die stacking knowledge, such a PiP package can be realized and show good reliability immediately. Some of the challenges moving forward with the development and commercialization of the PiP package are as follows: Package thickness needs to be reduced. Next generation users of this packaging technology require 1.4mm maximum package height moving to 1.2mm maximum in the near future, with the same or more level of device integration. Design rules, already being formulated, need to be verified and matured. Standards need to be developed, both electrical and package outline design standards, to enable memory device suppliers to design and provide the LGA package embedded in the PiP. Test infrastructure to test the thin LGA as well as the base package needs to mature. Continuous development and implementation into mass production of key enabling technologies such as wafer thinning, ultra low wire bond looping, very thin laminate substrate technology, and encapsulant molding technology and materials needs to occur. The second or board level reliability of such PiP packages including board level temperature cycle, drop test, and bend test needs to be proven.

6 Many of the above challenges are already been addressed and testing completed. Especially regarding second level reliability. A future paper will address the second level reliability of the PiP package, but as would be expected, it follows to second level reliability of an equivalent stacked die package. The Package in Package is a novel and promising concept and initial package development and reliability tests bear that out. A lot of activity is focused on further developing and introducing this package to the market. Acknowledgments Young-Cheol Kim, Geunsik Kim, and Kenny Lee are responsible and have ably characterized and developed this package in ChipPAC Korea. Marcos Karnezos, CTO of ChipPAC Inc, has been a champion of this package and visualized it to begin with. References 1. Karnezos, M, Package-in-Package (PiP): A new 3-D Module for Wireless Applications, MEPTEC Symposium on SIPs or SOCs? The Multi-million Dollar Question Proceedings, The Westin Santa Clara, CA, Feb. 19, 2004.