IN THE last decade, personal electronic devices have proliferated

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1 834 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 5, MAY 212 Measurement and Analysis for Residual Warpage of Chip-on-Flex (COF) and Chip-in-Flex (CIF) Packages Jae-Won Jang, Kyoung-Lim Suk, Kyung-Wook Paik, Member, IEEE, and Soon-Bok Lee, Member, IEEE Abstract A flip-chip package using adhesive interconnection consists of materials which have different coefficients of thermal expansion (CTE). The package experiences temperature higher than room temperature during the assembly process and is also exposed to the thermal cycling load during its lifetime. As a result, flip-chip packages have residual warpage after completion of the assembly process. Excessive warpage causes various reliability problems. Therefore, residual warpage is an essential factor for evaluating the reliability of electronic packages. In this paper, we evaluated the warpage of chip-on-flex (COF) packages using the moiré methods. A chip-in-flex (CIF) package developed to increase the binding force between the chip and the substrate was also evaluated with the same methods. Finite element analysis (FEA) was also performed for comparison with the experimental results. Based on the FEA result, effective design parameters for the CIF package were found to reduce the residual warpage. Index Terms Chip-in-flex package, chip-on-flex package, finite element analysis, residual warpage, shadow moiré, Twyman/Green interferometry. I. INTRODUCTION IN THE last decade, personal electronic devices have proliferated rapidly. Small, mobile electronic products such as cellular phones, notebook computers, and portable multimedia players have become ubiquitous. Over the course of their development, these products have become smaller and smaller. At the same time, to meet consumer demands, each generation of such products has included many enhancements over preceding versions along with more advanced features. In other words, the electronic packages inside of these products are becoming more integrated, smaller, and thinner. This reduction in electronic package size is realized partly by using a flip-chip assembly and adhesive Manuscript received March 11, 211; revised July 6, 211; accepted November 1, 211. Date of publication December 21, 211; date of current version May 3, 212. This research was supported by a grant (211K251) from the Center for Nanoscale Mechatronics & Manufacturing, one of the 21st Century Frontier Research Programs, which are supported by the Ministry of Education, Science and Technology, Korea. Recommended for publication by Associate Editor I. C. Ume upon evaluation of reviewers comments. J. W. Jang and S. B. Lee are with the Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology, Daejeon 35-71, Korea ( jwjang@kaist.ac.kr; sblee@kaist.ac.kr). K. L. Suk and K. W. Paik are with the Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon 35-71, Korea ( stones1@kaist.ac.kr; kwpaik@kaist.ac.kr). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier 1.119/TCPMT /$ IEEE interconnection. Flip-chip assembly using adhesive interconnection offers several advantages: small package size, fine pitch for high input/output density, and environmental compatibility [1], [2]. The flexibility of the flip-chip assembly can also be increased by using a flexible substrate. A chip-on-flex (COF) package, a kind of flip-chip package with a thin and flexible substrate, is studied in this research. The chip and substrate are interconnected electrically by the conductive particles of the anisotropic conductive film (ACF) between the bump of the chip and the pad of the substrate. Furthermore, a chip-in-flex (CIF) package is fabricated by adding two more flexible substrates to a COF package to increase the binding force between the chip and the flex substrate, and reinforce their interconnection. An embedded package, similar structure with CIF package, was widely studied [3] [5]. Christiaens et al. [6] presented a polyimide-based ultrathin chip package, and the whole package was bendable. Kripesh et al. [7] studied a multidie embedded wafer level package, and they investigated the warpage variation with respect to the number of stacking dies through finite element analysis (FEA). All electronic packages experience various external loads, and one of them is the thermal cycling load. For example, when the power is turned on and off, the electronic package is heated up and cooled down, respectively, and these phenomena are repeated. When the package is cooled down to room temperature, it has residual warpage according to the amount of the coefficients of thermal expansion (CTE) mismatch among the component materials, and the structural features. Excessive residual warpage of the package causes several reliability problems by inducing mechanical peel stress, disconnecting one level from the next level of the package and increasing the possibility of die cracking [8] [11]. Therefore, it is essential to investigate the warpage of the package to evaluate its reliability. In this paper, the features of COF and CIF packages were examined. Optical methods were used to measure the warpage and deformation shape of the packages. Residual warpage of the packages was investigated by using shadow moiré and Twyman/Green interferometry which are adequate and widely used to measure small deformations in microelectronic packages. A FEA was conducted for comparison with the experimental results. The effects of the design parameters of

2 JANG et al.: MEASUREMENT AND ANALYSIS FOR RESIDUAL WARPAGE OF COF AND CIF PACKAGES 835 TABLE I SPECIFICATION OF THE CHIP,ACFAND FLEX SUBSTRATES [12] Chip ACF 1st PI 2nd PI 3rd PI Size (mm 2 ) Thickness (μm) Cu electrode thickness (μm) (including adhesive) 2 15 upper: 27, bottom: Fig. 1. Top view. COF. CIF packages. TABLE II THERMO-MECHANICAL PROPERTIES OF MATERIALS [12] [15] Chip ACF 1 ACF 2 3rd PI 2nd PI E (GPa) ν T g ( C) CTE (ppm/ C) Fig. 2. 1st PI 1st PI at the center region Schematic diagram. COF. CIF packages. the CIF package on residual warpage were also evaluated through FEA. Polyimide Silicon Gold Copper ACF ACF below T g : 113, above T g : 5977 below T g : 79.4, above T g : 2812 II. SPECIMENS A COF package consists of a silicon chip, ACF and a flex substrate (PI). The function of the ACF is mechanical and electrical interconnection between the chip and the flex substrate. In a CIF package, two more flex substrates (2nd and 3rd flex substrates) are stacked on a COF package, and different ACFs are used between the 1st and 2nd and the 2nd and 3rd substrates. In this paper, to distinguish the ACFs, the ACF used for COF assembly is denoted as ACF 1 and that used for flex-to-flex (FOF) assembly is denoted as ACF 2.Fig.1 shows the COF and CIF packages. Schematic diagrams of cross sections of the packages are illustrated in Fig. 2. Specifications and thermo-mechanical properties of the materials constituting the packages, such as elastic modulus (E), Poisson s ratio (ν), glass transition temperature (T g ), and CTE are listed in Tables I and II. III. METHODOLOGIES A. Moiré Methods To realize the moiré method, two gratings are needed. One is a reference grating, and the other is a specimen grating which can deform with the specimen. When two gratings with slightly different spatial frequency are superposed, the dark and light bands, so called moiré fringes, are formed. The advantage of moiré method is that moiré fringes magnify the small displacement of the specimen grating. As a result, the small deformation of the specimen can be detected easily by observing the changes in moiré fringes. In this research, two moiré methods, shadow moiré and Twyman/Green interferometry, which are non-contact and real-time measurement methods, are used to measure the out-of-plane deformation of the specimens. 1) Shadow Moiré: Shadow moiré is one of the geometric moiré methods, and its principle is illustrated in Fig. 3. In this method, a real reference grating is needed to measure the out-of-plane deformation. The other is the shadow of the real reference grating on the specimen. Moiré fringes are produced by the superposition of these two gratings [18]. When L is larger than w (L w), the out-of-plane displacement w can be determined by g w(x, y) = tan a + tan b N z(x, y) = gl D N z(x, y) (1) where g is the pitch of the real reference grating and N z is the fringe order at each point in the fringe pattern. In this method, a diffusive surface is required for good fringes visibility. This method was used to observe the shape of whole field of COF and CIF packages. In this paper, the bottom surface of the 1st flex substrate was observed. 2) Twyman/Green Interferometry: Fig. 3 shows the principle of Twyman/Green interferometry. The laser beam is separated into two parts by the beam splitter. These two parts of the beam are incident to the reference mirror and the specular surface, respectively, and are then reflected. Therefore, the target surface of the specimen must have a specular surface. After this process, the wave front shape of the reflected laser beam becomes different from that of the incident laser beam due to the warped surface of the specimen. Interference fringes are created by the interference of these two reflected laser beams, which have different optical path lengths [17]. The relationship between out-of-plane displacement w and fringe order at each point in the fringe pattern N z is w(x, y) = λ 2 N z(x, y) (2) where λ is the wave length of the laser beam.

3 836 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 5, MAY 212 Light source L D a b y x z Specimen CCD W 2 camera g W 1 Grating specimen S(x, y) W 1 Laser Beam splitter Reference path Observer or camera Reference mirror Fig. 3. Schematic diagram. Shadow moiré system (adapted from [16]). Twyman/Green interferometry (adapted from [17]). (c) (d) (e) (f) (g) (h) (i) (j) Fig. 5. (original). π/2. (c) π. (d) 3π/2 phase-shifted moiré images. (e) phase map of COF package. (f) (original). (g) π/2. (h) π. (i)3π/2 phase-shifted moiré images. (j) phase map of CIF package. Fig. 4. Moiré image of COF package at room temperature obtained by using Twyman/Green interferometry. The chip in COF package has a specular surface and its warpage can be directly measured by using this method. However, the amount of out-of-plane deformation of the package at room temperature is too great for this method. Therefore, the process of resolving the fringes can be difficult and prone to error. Fig. 4 shows the residual warpage of the COF package obtained by using Twyman/Green interferometry. The moiré fringes did not emerge over the whole area of the chip surface in COF package and only appeared in the area marked by the dashed circle. In the case of a normal chip-on-board (COB) package, which has a thicker substrate than a COF package, the relationship between the warpage of the chip and temperature shows linear behavior. The warpage of the chip linearly decreased as the temperature increased under T g of the ACF [19]. We assumed that, similar to a COB package, the warpage variation of the chip in COF package would show linear behavior according to varying temperature. Then, we estimated the warpage of the chip in COF package at room temperature by extrapolating the values at higher temperatures. On the other hand, the chip in CIF package is covered with flex substrates. Therefore, we cannot directly measure the warpage of the chip using this method. Alternatively, we measured the 1st flex substrate at the center region (see Fig. 2) of the COF and CIF packages. Because the chip of both packages is located on the 1st flex substrate, it is considered that the shape of the chip is similar to that of the 1st flex substrate. B. Finite Element Method In case of conventional thick package structure, the effect of a pattern layer which has less thickness than the chip and substrate can be neglected [2]. However, in the case of a COF package, the thickness of the pattern layers, such as the Cu pad and Au bump, is about one-fifth of the total thickness y (mm) y (mm) x = Unit: µm at y = y = y (mm) at x = x = Unit: µm at y = y = y (mm) at x = (c) (d) Fig. 6. Contour graph. XZ plane and YZ plane profile of COF package. (c) Contour graph. (d) XZ plane and YZ plane profile of CIF package. of the package. Therefore, in this paper, these pattern layers were modeled to consider their effects. FEA was performed by using ABAQUS to observe the warpage of the COF and CIF packages. The simulation results were compared with the experimental results. In addition, FEA was performed with various design parameters for the CIF package to observe their effects on the warpage of the package. IV. RESULTS AND DISCUSSION A. Moiré Experimental Results 1) Shape of the Whole Field: Fig. 5 shows original and phase-shifted (π/2, π, and3π/2) moiré images from the image obtained by using shadow moiré. The contour interval is 22 μm per fringe order. From these images, we obtained a contour map of the packages by using the phase-shifting method. Fig. 6 shows the contour maps and profile images of the packages. According to these images, it is possible to identify

4 JANG et al.: MEASUREMENT AND ANALYSIS FOR RESIDUAL WARPAGE OF COF AND CIF PACKAGES 837 w c Fig. 7. Cross section schematic diagram. COF. CIF packages at room temperature (residual warpage). (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) Fig. 8. Top view. (original). (c) π/2. (d) π. (e)3π/2 phase-shifted moiré images. (f) phase map of COF package. (g) top view. (h) (original). (i) π/2. (j) π. (k)3π/2 phase-shifted moiré images. (l) phase map of CIF package. some differences between the shapes of the COF and CIF packages. The shape of the COF package was symmetrical to the XZ plane, and it showed a concave profile in the YZ plane. On the other hand, the CIF package showed a concave shape in both the XZ and YZ planes. The shapes of the 1st flex substrate in the center region of each package are also totally different. For the COF and CIF packages, these substrates showed convex and concave profiles, respectively. Fig. 7 shows an YZ plane schematic diagram of the COF and CIF packages. These distinctions arise from a structural difference between the COF and CIF packages. The 1st flex substrate of both packages had an initial curvature after completion of the lithography process for forming the Cu electrode on the polyimide. Therefore, both packages had a concave shape overall. After completing the COF assembly process, the package was cooled from assembly temperature to room temperature. ACF 1 contracted significantly as temperature decreased due to its high CTE. The 1st flex substrate also contracted more than the chip because the CTE of the 1st flex substrate is higher than that of the chip (see Table II). Therefore, the 1st flex substrate in the center region of the COF package showed a convex shape. However, the area of 1st flex substrate at the center region is approximately 19 times smaller than that of whole 1st flex substrate (see Table I). As a result, the COF assembly process does not affect the initial curvature of 1st flex substrate except the center region. On the other hand, fabrication of the CIF package required two more flex substrates than the COF package, as well as use of the FOF assembly process. The thickness of ACF 2 is approximately 2.5 times greater than that of ACF 1. As a result, when the CIF package was cooled from assembly temperature to room temperature, ACF 2 contracted more than ACF 1. Therefore, the 1st flex substrate in the center region of the CIF package showed a concave shape opposite to that of the COF package. Furthermore, from this result, it is clear that the warpage of the chip in CIF package is affected by the thickness of the ACF 2. wc y (mm) y (mm) x = Unit: µm at y = y = y (mm) at x = x = Unit: µm at y = y = y (mm) at x = (c) (d) Fig. 9. Contour graph. XZ plane and YZ planeprofileimagesof COF package. (c) Contour graph. (d) XZ plane and YZ plane profile images of CIF package. Warpage (µm) Warpage at room temperature Temperature ( C) Fig. 1. Warpage variation of the chip in COF package according to temperature variation. 2) Warpage of the Chip: a) Warpage of 1st flex substrate at the center region: We obtained out-of-plane deformation of original and phase-shifted (π/2, π, and3π/2) moiré images of the 1st flex substrate in the center region of the COF and CIF packages through shadow moiré (Fig. 8). Due to the small measured area (6 6mm 2 ), we changed the reference grating to one which has a finer spatial frequency than that used to measure the whole field of the package. In the fringes patterns, the contour interval is 6.5 μm per fringe order. Fig. 9 shows contour graph and profile images of the COF and CIF packages. b) Chip warpage at high temperature: We observed the variation of chip warpage in the COF package through Twyman/Green interferometry as the temperature increased. The specimen was heated from room temperature to 6 C during the experiment. The warpage of the chip at room temperature was obtained by extrapolating the warpage at temperatures higher than room temperature (Fig. 1). The experimental results, including the

5 838 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 5, MAY Experimental result FEA result x-axis x-axis Warpage (µm) 2 COF w c CIF w c Fig. 11. y-axis y-axis Finite element model images. COF. CIF packages. TABLE III INITIAL WARPAGE OF THE FLEX SUBSTRATES IN THE PACKAGES (UNIT: μm) COF package CIF package Average Standard deviation warpage of the 1st flex substrate in the center region ( )of the COF and CIF packages and that of the chip (w c )incof package, are plotted in Fig. 12 and were compared with the values obtained from FEA. B. FEA Results FEA was performed to investigate the warpage of the COF and CIF packages. One quarter of both packages were modeled by imposing symmetric boundary conditions with 3-D elements as shown in Fig. 11. An isothermal load from 11 C to 25 C was applied. At the elevated temperature (11 C) closed to T g of ACFs (see Table I), the flex substrates in the packages have initial warpages. Initial warpages obtained from moiré experiments under the elevated temperature with the similar procedure for observing residual warpage (see Table III) were considered in the FEA. The specifications and thermo-mechanical properties of the packages used for FEA are listed in Tables I and II. 1) Warpage of the Packages: Fig. 12 shows a comparison between the warpages of the packages obtained by using different methodologies, the moiré experiment and FEA. The deformation shapes of the 1st flex substrate at the center region and the chip in both packages obtained by using FEA were the same as obtained by using the moiré experiment. The center region of the COF package was convex (positive sign) and that of the CIF package was concave (negative sign). As shown in Fig. 12, the absolute of the COF package is smaller than that of the CIF package. For the COF package, was larger than w c. As has been stated, the 1st flex substrate has an initial warpage. As the temperature increases, the movability of the ACF 1 increases. Since CTE mismatch causes the COF package to become convex, the ACF 1 can move slightly from the center to the outside of the chip. In addition, the Cu pad and Au bump, which have lower CTEs than the ACF 1, are located at the edge of the chip. These resulted in nonuniform thickness of the ACF 1.TheACF 1 at 4 Fig. 12. Comparison of the warpage obtained from the experiments and FEA. (As stated in Section III, w c of the CIF package cannot be obtained from the experiments.) Relative displacement (µm) Relative displacement (µm) Original 1 µm reduction 2 µm reduction 3 µm reduction Distance from the chip center (mm) Original (31 µm) 25 µm 2 µm 15 µm 1 µm 5 µm Distance from the chip center (mm) Fig. 13. Warpage change according to reducing. Thickness of the ACF 2. Initial warpage. the center is thicker than that at the edge. From these results, and w c of the COF package showed different values. The experimental and simulation results showed a good correlation. These results provide validation of the warpage of the chip in CIF package obtained from FEA. According to the simulation result, the warpage was approximately 4 μm and showed a concave shape. This value is over twice the warpage of the chip in COF package. 2) Effective Design Parameters of CIF Package: From the results of moiré experiments and FEA, it is clear that the warpage of the CIF package is greater than that of the COF package, and this increased warpage is caused by the thickness of the ACF 2. Initial warpage of the flex substrate can also have an effect on its residual warpage. Fig. 13 shows the warpage shape of the chip change according to how much the thickness of the ACF 2 is reduced. The out-of-displacement value at the chip center was shifted to zero. The original CIF package has an ACF 2 approxi-

6 JANG et al.: MEASUREMENT AND ANALYSIS FOR RESIDUAL WARPAGE OF COF AND CIF PACKAGES 839 mately 72 μm thick. From the result, it is clear that residual warpage of the chip was reduced as the thickness of the ACF 2 decreased. The warpage of the chip was reduced approximately 3% (from μm to μm) when the thickness of the ACF 2 was reduced from 72 μm to42μm. We also obtained a change in residual warpage by reducing the initial warpage of the flex substrate [Fig. 13]. As a result, the warpage of the chip was reduced approximately 68% (from μm to 13.4 μm) when the initial warpage of the flex substrate was reduced from 31 μm to5μm. Therefore, we can control the warpage of the chip by changing these two factors, the thickness of the ACF 2 and the initial warpage of the flex substrate. V. CONCLUSION The residual warpages of COF and CIF packages were observed by using the moiré method. FEA was conducted to compare with the experimental results and to evaluate the effects of the design parameters of the CIF package on residual warpage of the chip. From the moiré experiments, it was observed that the shapes of the packages differed from one another. The 1st flex substrate at the center region of the COF package was convex, but that of the CIF package was concave. The absolute warpage of the 1st flex substrate at the center region of the CIF package was larger than that of the COF package. FEA results showed that the warpage of the chip in CIF package was twice as large as that of the COF package. The reasons for these results are that the ACF 2 is thicker than the ACF 1 and also there was excessive initial warpage of the flex substrate. FEA results showed that residual warpage of the chip in CIF package was reduced as the thickness of the ACF 2 and the initial warpage of the flex substrate were decreased. Therefore, we expect that minimizing the warpage of a CIF package can be realized by modifying the design parameters, the thickness of the ACF 2 and the initial warpage of the flex substrate. From the experimental and FEA results, the ACF 2 used for enhancing the reinforcement between the chip and the 1st flex substrate induced large warpage of CIF package, and the warpage becomes larger as the thickness of the ACF 2 increases. That is, for reducing the warpage and assuring the reliability of CIF package, the ACF 2 should be minimized. On the other hand, for assuring the interconnection between the chip and the 1st flex substrate, it is needed to increase the thickness of ACF 2. Therefore, the design of CIF package must be determined carefully according to the function of the package in a device, service condition, etc. REFERENCES [1] A. M. Lyons, E. Hall, Y.-H. Wong, and G. Adams, A new approach to using anisotropically conductive adhesives for flip-chip assembly, IEEE Trans. Compon. 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Im, A study on the thermomechanical behavior of semiconductor chips on thin silicon substrate, J. Mech. Sci. Technol., vol. 22, no. 8, pp , Aug. 28. Jae-Won Jang received the B.S. degree in mechanical engineering from Pusan National University, Busan, Korea, in 28. He is currently pursuing the Ph.D. degree as the Integrated Masters Ph.D. Program in mechanical engineering with the Korea Advanced Institute of Science and Technology, Daejeon, Korea. His current research interests include reliability physics of flexible and 3-D stack packages, optical measurement techniques, and finite element analysis.

7 84 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 5, MAY 212 Kyoung-Lim Suk received the B.S. degree in nanotechnology and advanced materials engineering from Sejong University, Seoul, Korea, in 27, and the M.S. degree in materials science and engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 29. She is currently a Ph.D. student with the Department of Materials Science and Engineering, KAIST. Her current research interests include flip-chip assembly and adhesive materials for advanced packaging, nano-materials, and their applications for highly reliable electronic packaging. Kyung-Wook Paik (M 95) received the B.S. degree in metallurgical engineering from Seoul National University, Seoul, Korea, the M.S. degree from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, and the Ph.D. degree in materials science and engineering from Cornell University, Ithaca, NY, in 1979, 1981, and 1989, respectively. He was a Research Scientist at KAIST from 1982 to 1985 and was responsible for the development of gold bonding wires. After the Ph.D. degree, he was with General Electric Corporate Research and Development, Niskayuna, NY, from 1989 to 1995 as a Senior Technical Staff Member, interconnect multichip module technology and power-integrated circuit packaging. He rejoined KAIST as a Professor with the Department of Materials Science and Engineering in In his Nano-Packaging and Interconnect Laboratory, he currently works in the areas of flip-chip bumping and assembly, adhesives flip-chip, embedded capacitors, and display packaging technologies. He was a Visiting Professor with the Packaging Research Center, Georgia Institute of Technology, Atlanta, from March 1999 to February 2, and was involved in packaging education and integrated passives research programs. He was visiting Portland State University, Portland, OR, from February 25 to August 25, and was working in the areas of flip-chip polymer materials evaluation. He has published more than 8 technical papers. He holds 16 U.S. patents and four U.S. patents are pending. Dr. Paik has been the Chairman of the Korean IEEE COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY chapter since 1995 and is a member of the International Microelectronics and Packaging Society, the Semiconductor Equipment and Materials International, and the Materials Research Society. Soon-Bok Lee (M 11) received the B.S. degree in mechanical engineering from Seoul National University, Seoul, Korea, the M.S. degree from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, and the Ph.D. degree in mechanical engineering from Stanford University, Stanford, CA, in 1974, 1976, and 198, respectively. He became a Professor with the Mechanical Engineering Department, KAIST, in He is an author within Korea s electronics industry. He has published more than 29 technical papers. His current research interests include reliability in electronics packaging, thin films, micro- and nano-scale measurement, characterization of materials at elevated temperatures, fatigue, fracture mechanics, and failure analysis of various structures in industry. Dr. Lee has been actively involved in the National Reliability Enhancement Program as a Chairman and Committee Member of the National Reliability Council for parts and materials in the Ministry of Knowledge Economy from 21 to 28. He has organized the 3rd International Symposium on Electronics Materials and Packaging in 21, the 5th International Conference on Experimental Mechanics in 26 as a General Chairman, and the 1th International Conference on Mechanical Behavior of Materials in 27 as a General Co-Chairman. He served as a Vice President of the Korea Reliability Society (KORAS) and a President of the Reliability Division in Korean Society of Mechanical Engineering (KSME). He is a member of KSME, KORAS, the American Society of Mechanical Engineers, and the Society of Experimental Mechanics.