CHIP SCALE PACKAGING FOR MODERN ELECTRONICS. by Joseph Fjelstad Reza Ghaffarian Young-Gon Kim

Transcription

1 CHIP SCALE PACKAGING FOR MODERN ELECTRONICS by Joseph Fjelstad Reza Ghaffarian Young-Gon Kim ELECTROCHEMICAL PUBLICATIONS LTD 2003

2 CONTENTS PREFACE ACKNOWLEDGEMENTS BIOGRAPHIES SECTION ONE Section 1 - CSP Market and Infrastructure CHAPTER ONE Introduction to Chip Scale Packaging 1.1 Introduction 1.2 Background 1.3 The Emergence of Chip Scale Packaging 1.4 Chip Scale Packaging Types 1.5 Bare Chip Technologies 1.6 Summary CHAPTER TWO CSP Markets and Applications 2.1 CSP Structures Categorised by Package Structure 2.2 CSP Applications Digital Camcorders The First CSPs Card PCs Feature Ceramic Packages Lead Frame-based Packages From Phones to Comput Mobile Phones Drive CSP Volumes 2.3 CSP Applications Expand beyond Portable Products 2.4 CSPs for Games 2.5 CSPs: The Future

3 XU Chip Scale Packaging for Modern Electronics CHAPTER THREE Design Guidelines for PCBs for use with CSPs 3.1 Introduction BGA and CSP Standards Area Array Package Planning Contact Layout and Device Outlines Chip-scale Area Array Variations Fine-pitch BGA Contact Array Planning Packaging Technology Considerations PCB Design Guidelines for BGA Contact Matrix Options Füll Matrix Perimeter Matrix Thermally Enhanced Matrix Staggered Matrix Selective Depopulation \ Defining Contact Assignment Attachment Site Planning Circuit Routing for Array Devices Circuit Density Considerations Fine Line/Circuit Layer Trade-off Rigid PCB Material Selection PCB Material Attributes Via Hole Planning Fine-pitch BGA Land Pattern/Via Hole Planning Providing for Higher Circuit Density Microvia Technology Design Guidelines for Microvia Laser-drilled Microvia Process Design Guidelines for Laser-via PCB Structures Photo-defined Microvia Process Plasma-drilled Microvia Process Microvia Technology Availability Economics for Microvia Mechanical Drilling Photo-defined Sequential Build-up Laser Drilled Microvia Technology Specifying Surface Finish for CSP Circuit Structures Tin/Lead Coating Ni/Au Finishes Electro Plating Process Ni/Au Electroless or Immersion Plating Pd/Ni or Pd/Cu Electroless (Palladium) Plating Alternative Surface Finish for Device Attachment Organic Solderability Preservative (OSP) PCB Assembly Process Considerations BGA Assembly Process Development Solder Paste Printing Solder Stencil Requirements for Area Array Devices 39

4 Contents xiu Defining Stencil Aperture Geometry Features Needed for Assembly Fiducial Size and Shape Reflow Solder Processing Reflow Solder Process Solder Process Verification for Area Array Packages X-ray Inspection for Area Array Packages Assembly Process Summary Summary 41 CHAPTER FOUR Interconnection Substrates for Chip Scale Packages 4.1 Introduction Substrate Technology Drivers Product Market Sectors Substrate Technology Issues Substrate Interconnect Wireability Substrate Options Frequency Drivers for Substrates Non-reinforced Materials Printed Circuit Substrate Manufacturing Capabilities High-density Substrate Manufacturing Options Sequential Processing Co-lamination Processing Piercing Post Processing Microvia Manufacturing Options Mechanically Drilled Microvias Punched Microvias Laser-drilled Microvias Photo-lithographically Defined Microvias Plasma Etched Microvias Chemically Etched Microvias Mechanically Abraded Microvias Discussion Summary 58 CHAPTER FIVE Chip Scale BGA Packäging Standards 5.1 Introduction Definitions Chip Size Package (CSP) Fine Pitch Ball Grid Arrays (FBGAs) Die Face Up Die Face Down ImpactofDieShrink The Evolution of Standards for CSP Market Drivers for CSP Standardisation 61

5 XIV Chip Scale Packaging for Modern Electronics 5.5 Design Guideline Development Package Height Standards Package Parallelism Ball Positional Tolerance Ball Diameter Specification Package Outline Standards for Rectangular FBGAs International Status for Standards International CSP Standards Development Primary Package Variations CSP Industry Trends Conclusion Acknowledgements 72 CHAPTER SIX Encapsulation Materials for CSPs 6.1 Introduction The Röleof Encapsulation x The Evolution of IC Packaging and Encapsulants Encapsulant Materials Encapsulant Resins Epoxy Silicone Polyimides Fillers for Encapsulants Lead Stress Management Controlling Encapsulant-Related Failure Mechanisms for CSPs Effect of Thermal Expansion Mismatch Effect of Die Size Countering the Effects of CTE Mismatch Future Developments in Chip Scale Encapsulants Summary 82 Section 2 - Chip Scale Packages CHAPTER SEVEN Flip-Chip Technology 7.1 Introduction Basics The Package History 7.2 Under Bump Metallisation (UBM) Problems with Aluminium TypesofUBM The IC Transition to Copper 7.3 Bumping Materials Fusible Bumps

6 Contents xv High-lead Solder Stratified Bumps Eutectic Sn/Pb Polymer Bumps, Thermoplastic Non-Fusible Bumps Gold Nickel Polymer, Thermoset Bumping Processes Vacuum Deposition Plating Electrolytic Plating Electroless Plating Printing/Stencilling Metal Fluid Jetting Mechanieal Joining Materials and Agents Flux Solder Paste Conduetive Adhesives Anisotropie Conduetive Adhesives (ACAs) Isotropie Conduetive Adhesives (ICAs) Adhesives, Non-eonductive The Assembly Process Solder Reflow SMT Process with Eutectic Bumps Pre-applied Flux-underfill Assembly Solder Paste Processes Thermomechanical Attachment Adhesive Bonding Isotropie Conduetive Adhesive Assembly Anisotropie Conduetive Adhesive Assembly Non-conductive Adhesive Assembly Testing and Rework Pre-testing In-circuit Testing Encapsulation/Underfill Pre-Applied Flux/Underfills Liquid on Substrate Solid on Substrate Solid on Chip/Wafer Post-Applied Materials CapillaryUnderfill Encapsulant (Over Chip) Substrates for Flip Chips Ceramic Organic, Rigid Organic, Flexible, High Temperature Organic, Flexible, Temperature-limited Features and Benefits Geometrical Considerations 114

7 XVI Chip Scale Packaging for Modern Electronics Footprint Profile Weight Performance Speed I/O Density Process-related Economics Limitations and Issues Known Good Die Challenge High Density Circuit Requirements Assembly Difficulty RamificationsofDieShrink Performance and Reliability Applications Computers and Peripherals Automotive Consumer Products Communications Smart Cards/RFIDs Other FC Products Summary and Conclusions 121 CHAPTER EIGHT Flip-Chip Ceramic Based CSP Features of Flip-Chip Ceramic-Based CSP Advantages Disadvantages Structure of Ceramic Flip-Chip CSP Process for Manufacturing a Ceramic CSP Stud Bumping Conductive Paste Application Underfill Application Dimensional Stability Interposer Manufacturing Process Characteristics of Ceramic Interposers Wiring Rules Conductive Adhesive Underfill Characteristics Underfill Formulation Electrical Properties of Ceramic CSPs Lead Inductance Switching Noise Characteristics High Frequency Characteristics Thermal Resistance Reliability of Ceramic CSP Package Level Reliability Second Level Assembly and Reliability of LGA Solder Joint Dummy Solder Joints 8.24 CSP Interposer Design

8 Contents xvii 8.25 Simultaneous Design Approach Products and Applications Summary 146 CHAPTER NINE Flip-chip CSP Technology Development and Implementation 9.1 Introduction Background Early Development Flip-chip CSP Subclasses Electrical Performance offc-csp Flip-chip Technology Variants Description JACS-Pak Flip-Chip CSP Development and Construction Substrates Metal Finish Bump Redistribution Assembly Process Fluxing Underfilling Solder Ball Attach Package Singulation Overmoulded FC-CSP Factors Affecting the Reliability of a Flip-chip CSP Underfill Fillet Geometry Underfill Material Properties Die Edge Chipping Chip to Substrate Gap Height Design for Reliability Reliability Performance of Flip-Chip CSPs Board Level Reliability Flip-chip CSP Applications Sony's Bold Implementation of Flip-chip CSP Packaging JACS-Pak Product Implementations at Motorola Stud Bump Bonding Based FC-CSPs in Product Applications Broadening of FC-CSP Technology Options 177 CHAPTER TEN Bottom Leaded Plastic (BLP) Package and Its Solder Joint Reliability 10.1 Introduction BLP Package Design DRAM Package Trend BLP Structure Lead Frame Design Standard Process and Materials Die Attach 185

9 XVIU Chip Scale Packaging for Modern Electronics Wire Bond Encapsulation Deflash Solder Plate Trim Test and Burn-in Package Reliability Solder Joint Reliability Design Strategy ATC Test First Design: BLP-I New BLP Design: BLP-II FEM Model Reliability Prediction Model Package Material Optimisation Discussion Package Performance Thermal Performance Electrical Performance Application Summary Acknowledgements CHAPTER ELEVEN Quad Fiat Non-leaded CSP 11.1 Introduction QFN Structure Assembly Flow Technology Development Package Characteristics Package Reliability Application and Development 220 CHAPTER TWELVE Bumped and Leadless Small Outline Packages 12.1 Introduction MicroLeadframe (MLF) Package Package Structure Applications Bump Chip Carrier (BCC) Package Package Structure Small Outline Electroformed Rivet Contact Package (COBIC) COBIC Structure Moulding Compound Selection Manufacturing and Assembly Processes Alternative Structures Thermal Enhancement 230

10 Contents Stacked Chip Constructions Optical Packaging Constructions Package Reliability Electrical and Thermal Performance Summary 233 CHAPTER THIRTEEN Flex Circuit Based Wire Bonded CSP 13.1 Introduction and Background Package Configuration Substrate (Flexible Interposer) Low Temperature Wire Bonding Processing Adhesion to Other Materials Trace Design Assembly Process Substrate Handling Die Attach Wire Bond Encapsulation Solder Sphere Attach Singulation Package Characteristics Electrical Performance Thermal Performance Reliability Reflow Performance Component Level Reliability Board Level Reliability of Assembled MicroStar BGA CSP Summary 252 CHAPTER FOURTEEN Compliant, Flexible Base Material Packages 14.1 Introduction Background Package Objectives I/O Placement Issues Compliant CSP Constructions Fundamental Elements of Construction Flexible Base Film Layer Metal Circuit Redistribution Layer Buffer or Compliant Layer Flexible Link Next Level Connection Contacts Electroformed Bumps Solder Balls Solid Core Balls Principles of Operation 261

11 Chip Scale Packaging for Modern Electronics Early Wire Bonded Variations DieFace-up Fiat Flexible Film Wrap-around Die Face-down Integral Lead Frame I/O Placement Decision Fan-in Only Centre Bond Päd Fan-in/Fan-out Fan-out Multiple Metal Layers Folded, Multichip Structures Variations Addressing Die Shrink 26/ EpoxyRing Elastomer Ring Metal Ring Manufacturing Processes Original Process The Zinger Assembly Process Zinger 1.4 Process Zinger 3.0 Process Zinger 4.0 Process WAVE Process Electrical Performance Signal Trace Analysis Decisions Estimating Values for RCL Parasitics Estimated Resistance Calculation Estimated Self-capacitance Calculation Estimated Self-inductance Calculation Results Factors that Reduce Estimation Accuracy Software Modelled RCL Parasitics Crosstalk Issues Classic Crosstalk Equations Calculating Crosstalk with Software Crosstalk Reduction Methods Thermal Performance Reliability and Failure Analysis Moisture Sensitivity Reliability Testing Conditions Reliability Test Results Failure Mechanisms Summary 296 CHAPTER FIFTEEN 3-D Chip Scale Package (CSP) 15.1 Increased Density Approaches 15.2 Review of 3-D Stacking

12 Contents xxi Bare Die MCM CSP D MCM for Aerospace Applications STAKPAK Samsung 3-D Memory Fujitsu Stack Chip Package (SCP) by Hyundai SCP Design Assembly FluxlessSolderingJointsofAg/Sn High-pressure Mechanical Joining of Silver Mechanical Strength of Lead-to-lead Joint Reliability Popcorn Cracking Test Temperature Cycle Test and Pressure Cooker Test D2CSP Stack by LG Semicon Design and Manufacturing Process Package and Assembly Reliability Rework Applications NEC's Three Dimensional Memory Module (3-DM) Area Array Stack Memory by Micron Fujitsu Stacked MCP (Multi-Chip Package) 325 CHAPTER SLXTEEN Wafer-level Packaging 16.1 Introduction Background Applications and Requirements for Chip Size Packages Perimeter Päd Limitations Chip-level Area Array I/O Pitch Comparison of Wafer-level CSP to Bumped Wafers (C4) Wafer-Level Packaging Drivers Cost Reduction or Savings Cost-efficiency Improvement Cost of Test Reduction Known Good Die (KGD) Solution Standardisationofl/OPin-out Compliant Interconnection Capability Wafer-Level Packaging Technology Overview Wafer-level Packaging Issues Process Complexity and Yield DieMaturity Die Shrink Concerns in Wafer-level Packaging Mechanical Compliance Concerns Alpha Particle Emissions Enhanced Packaging Capability Factors in Cost Analysis 343

13 Chip Scale Packaging for Modern Electronics 16.7 Wafer-level Packaging Options Bumped Wafer Technologies Wafer-level Peripherally Leaded Packaging Peripheral Beam Leaded Wafer-level Package Peripherally Leaded Wafer-level Package with Glass Cover Peripherally Leaded Wafer-level Package with Encapsulated Vertical Pins Wafer-level Area Array Packaging 'Chip-at-a-Time'Wafer-level Area Array Assembly Direct Assembly with Modified Wire Bonding Wafer-level Assembly with Modified Wire Bonding to an Interposer Build-up Processing ofthe Package onthe Wafer Gang Assembly of Packaging onthe Wafer Gang Assembly of Mating Interposers Gang Assembled Wafer-level Leadframe Gang Assembled Wafer-level Rigid Interposer Gang Assembled Wafer-level Flexible Assemblies Flexible Vertical Interconnection Links Performance of Wafer-level Packaging Summary 359 Section 3 - CSP Reliability CHAPTER SEVENTEEN Reliability Verification of CSPs 17.1 Introduction Definitions Reliability Definition Qualification Testing Definition Environmental Stress Screening Testing Philosophy Traditional Practice for Reliability Verification Test Strategy for the Future Reliability Program Standard Development IPC Reliability Promotion Efforts JEDEC Reliability Promotion Efforts Summary of Reliability Approaches Performance-based Reliability Testing of Packages Design for Reliability Test Programme Development Summary of Performance-based Testing Concerns Possible Failure Mechanisms Cracking of Solder Joints Failure Mechanisms Strain Related Failure Vibration Wear-out Failure Influence of Package and Solder Land Design on Failure Influence of Underfill on Solder Joint Reliability Accelerated Test Methods for Evaluation of Solder Joints 373

14 Contents Thermal Cycling and Thermal Shock Thermal Cycling Dwell Time Thermal Cycling Temperature Power Cycling Special Cases Interconnection Failures Inside Packages Failure Mechanisms * Accelerated Test Methods Corrosionof Metallisation at Chip Surface Failure Mechanisms Accelerated Test Methods Test Vehicles Categorisation of Package Types Components with Leads Packages with Rigid Structure and Solder Lands Packages with Organic Structure and Solder Lands Packages with Ceramic Interposer and Solder Balls Packages with Organic Rigid Interposer and Solder Balls Packages with Flexible Interposer and Solder Balls (Rigid Structure) Packages with Compliant Layer Moulded Chips with Solder Balls Packages with Metallised Polymerie Bumps Packages with Metallic Bumps 382 CHAPTER EIGHTEEN CSP Requirements for Aerospace Applications 18.1 Spacecraft on Chip Quality Assurance: A System Approach Electronics Miniaturisation Trends Microelectronics Assembly Reliability Microelectronics Field Reliability Projection Challenges SMA leaded/leadless Reliability SMA Key Variables: a Survey SMA Reliability Evaluation SMA Test Results SMA Cycles-to-failure Analysis BGA Reliability BGA Test Vehicle Configuration BGA-Thermal Cycling BGA - Damage Monitoring BGA Thermal Cycling Results CSP Challenges CSP Definition CSP Implementation Challenges CSP Thermal Ageing Integrity Ball/Package Shear Test SEM Characterisation - As Received Shear Test - As Received SEM of Shear Surfaces - As Received 407

15 xxiv Chip Scale Packaging for Modern Electronics Shear after Thermal Ageing Tin Leach of Aged Solder CSP Outgassing Concerns Assembly Grid CSP Self-alignment CSP Assembly Reliability - Literature Data CTE Absorbed CSPs Extreme CTE Mismatch CSPs Ceramic CSPs Comments on CSP Reliability Data CSP Reliability- Review of Variables and Testing Design Package Variables Solder Balls Assembly TestMethods Failure Mechanisms and CSP Reliability CSP Reliability Projection Low I/O CSPs and SMA Comparison Assembly Reliability of Different I/O CSP Comparison CSP Technology Ranking Metrics Thermal Cycling Test Standard Thermal Cycling Test Standards CSP Assembly and Test Results Quality of Solder Joints Grid CSP Shear Forces CSP Thermal Cycling Test Results Lessons Learned and Recommendations Lessons Learned from SM and BGA for CSP CSP Assembly Reliability Tests 428