Asia/Pacific Semiconductor Packaging and Assembly Facilities, 2002 (Executive Summary) Executive Summary

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1 Asia/Pacific Semiconductor Packaging and Assembly Facilities, 2002 (Executive Summary) Executive Summary Publication Date: October 24, 2002

2 Author Philip Koh This document has been published to the following Cluster codes: SEMC-WW-EX-0176 For More Information... In North America and Latin America: In Europe, the Middle East and Africa: In Asia/Pacific: In Japan: Worldwide via Entire contents 2002 Gartner, Inc. All rights reserved. Reproduction of this publication in any form without prior written permission is forbidden. The information contained herein has been obtained from sources believed to be reliable. Gartner disclaims all warranties as to the accuracy, completeness or adequacy of such information. Gartner shall have no liability for errors, omissions or inadequacies in the information contained herein or for interpretations thereof. The reader assumes sole responsibility for the selection of these materials to achieve its intended results. The opinions expressed herein are subject to change without notice

3 Asia/Pacific Semiconductor Packaging and Assembly Facilities, 2002 (Executive Summary) Background and Methodology Field Definitions This report contains Gartner Dataquest's SPA facilities database located in the Asia/Pacific region. The SCSIAP program will conduct annual surveys, complemented by secondary research, to maintain this database. This document will be published once a year and represents Gartner Dataquest's best insights and estimates into the locations and capabilities semiconductor packaging and assembly facilities in Asia/Pacific. Some facilities in this report may not contain all information because of a lack of response. The tables in this report cover only established SPA facilities. A packaging and assembly facility consists of equipment utilized for the purpose of performing "back end" semiconductor manufacturing. This will include, but is not limited to, the receipt of semiconductor die in wafer or individual dice format; preparation and attachment of the die to a substrate (wafer bumping, die attach, TAB, or flip chip interconnect); wire bonding (if required); encapsulation (molding) or sealing; second-level interconnect (leadframe trim/form, solder ball) formation; and singulation into individual packaged units. The following field definitions include the internal as well as external fields of Gartner Dataquest's dynamic database. These definitions correspond with the questions included on the survey. The following fields are a subset of the total database. Company Indicates the operator of the packaging and assembly fabrication line. For contract assembly companies, that is, "packaging foundries" that trade capacity for capital investment in the back-end fabrication, Gartner Dataquest lists those contract assemblers. Campus Displays the industrial parks location of the semiconductor packaging and assembly facilities. City/state Displays the detailed location information. This reference is usually a city or town but could be an often-used district name (for example, Science Park in the city of Hsinchu, Taiwan). If this field lists a district, GartnerDataquestwilllistthecityintheStateorProvincefield.Insome cases, a reference to a state or province will be included in the city or district field to create a unique identifier for this location. Country Indicates the broadest location identifier in this report. This reference is usually a country, except in the case of the United Kingdom (see "State or Province" above). Because Japan is a single-country region, there is no regional qualifier for assembly facilities in Japan. Plant name Provides a reference to a particular manufacturing location to distinguish it from other assembly facilities owned by that company. Although Gartner Dataquest makes every attempt to match the nomenclature used by the company, occasionally some additional qualifiers (for example, "Phase 1") will appear to provide insight to the facility's history or organization. Date and quarter of initial production Showsthedatewhenproduction initially began for the facility Gartner, Inc. 1

4 2 Asia/Pacific Semiconductor Packaging and Assembly Facilities, 2002 (Executive Summary) Factory area Contains the enclosed area within a manufacturing facility that is used for the assembly and packaging of ICs and semiconductors. Employees Refers to the number of operators and engineers currently working in the assembly facility. Package Lists the types of semiconductor packages produced at that facility. Common package designations are as follows: PDIP Plastic dual-in-line package PPGA Plastic pin grid array package SOIC Small-outline integrated circuit package SSOP Shrink small-outline package QSOP Quarter-size small-outline package (25 mm pitch) TSOP Thin small-outline package TSSOP Thin, shrink, small-outline package PLCC Plastic leaded chip carrier package PQFP Plastic quad flat package TQFP Thin quad flat package Power quad Used to define all thermally enhanced plastic quad flat packages (includes enhanced TQFP also) PBGA Plastic ball grid array, pitch greater than 1.0 mm FBGA Fine pitch ball grid array, pitch less than 1.0 mm (does not include chip scale package) TBGA Tape ball grid array EBGA Thermally enhanced plastic ball grid array CSP Chip scale package. Defined as a package no greater than 20 percent larger than the IC die; pitch is less than 1.0 mm; leadframe, laminate or flexible circuit-based FCOB Flip chip on board An unpackaged die that is bonded directly to the PCB or substrate using a "bump" connection FCIP Flip chip in package unpackaged die that is directly attached to apcbsubstrate WLP Wafer level packaging die that is packaged in wafer form instead of individual packages DCA bare die Direct chip attach unpackaged die directly attached to a PCB substrate CSP bare die WLP die that is processed (packaged) in wafer form instead of individual packages W/BCOB AbarediethatiswirebondedtoasubstratePCB TAB Tape automated bonding. Defined as a bare die attached to a flexible circuit tape, as opposed to wire, also called chip-on-tape Ceramic A package made from inorganic materials, usually alumina, as opposed to plastic Ceramic DIP A dual-in-line package made from ceramic material such as alumina Cerquad A quad flat package made from ceramic material such as alumina 2002 Gartner, Inc. October 24, 2002

5 Asia/Pacific Semiconductor Packaging and Assembly Facilities, 2002 (Executive Summary) 3 Ceramic PGA A pin grid array made from ceramic material such as alumina Ceramic BGA A ball grid array package made from ceramic material such as alumina Ceramic CSP A chip scale package made from ceramic material such as alumina Discrete A semiconductor, performing as a single unit, that is packaged alone, such as a transistor SOT Small outline transistor, usually used to package surface-mount discrete devices (transistors) TO 92, 202, 220 Transistor outline, through-hole packages with metal leadframes MCP A multichip package: any package containing two or more dies For the full report, see the Gartner Dataquest Market Statistics "Asia/Pacific Semiconductor Packaging and Assembly Facilities, 2002" (SCSI-AP-MS-0119) Gartner, Inc. October 24, 2002