Development of Next-Generation ewlb Packaging

Transcription

1 Development of Next-Generation ewlb Packaging by Seung Wook Yoon, Yaojian Lin, Pandi Chelvam Marimuthu and *Rajendra Pendse STATS ChipPAC Singapore *Fremont, California USA Ganesh V. P, Andreas Bahr and Thorsten Meyer Infineon Technologies AG Yonggang Jin and Xavier Baraton ST Microelectronics Originally published in the International Wafer Level Packaging Conference Proceedings, Santa Clara, California, October 11 14, Copyright The material is posted here by permission of the SMTA - The Surface Mount Technology Association. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

2 DEVELOPMENT OF NEXT GENERATION ewlb (EMBEDDED WAFER LEVEL BGA) PACKAGING Seung Wook Yoon, Yaojian Lin, Pandi Chelvam Marimuthu and *Rajendra Pendse STATS ChipPAC * Fremont, CA, USA Seungwook.yoon@statschippac.com Ganesh V. P, Andreas Bahr and Thorsten Meyer Infineon Technologies AG Yonggang Jin and Xavier Baraton ST Microelectronics ABSTRACT Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. Fan-in (FI)-WLP typically has a limitation to be less than 6x6mm in order to pass board level reliability requirements such as drop test and temperature cycle due to the mismatch of Si material properties to the PCB. However, the Fan-out (FO)-WLP, has been developed and introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. The most prominent type of FO-WLP is the ewlb technology (embedded Wafer Level Ball Grid Array). Currently 1st generation ewlb technology is available in the industry. This paper will highlight some of the recent advancements in next generation ewlb technologies including multi- RDL, thin ewlb and extra large ewlb as well as double-side with vertical interconnection. These key technologies of next generation ewlb enable 3D ewlb applications such as SoW (SiP on Wafer) and 3D SiP. 3D ewlb can be implemented with through silicon via (TSV) applications as well as discrete component embedding. The process flow of next generation ewlb fabrication, assembly and packaging challenges will be discussed. This paper will also present some of the achievements in package reliability, mechanical characterization and performance. INTRODUCTION Integrated Circuits fabricated on silicon is assembled in different forms of electronic packages and are used extensively in electronic products such as personal, portable, healthcare, entertainment, industrial, automotive, environmental and security systems. Current and future demands of these electronic systems in terms of performance, power consumption, reliable system at a reasonable cost are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-packagesystem co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called ewlb in detail. In just one decade hand phone has transformed from a simple communication device into more complex system integrating features that allow customers to use it as a multipurpose gadget. The carrier technology has jumped from 1G to 3G, changing at the rate of every two years and with room for potential growth with global adoption. Moving forward with this trend, packaging semiconductor devices for handheld electronics has become more challenging than ever before. Growing mismatch in interconnect gap, adding different functional chips for different features and application in similar system footprint and package size reduction to increase battery size for extended usage has opened the window for innovative embedding packaging technology. To meet the above said challenges ewlb was developed [1] which offers additional space for routing higher I/O chips on top of Silicon chip area which is not possible in conventional WLP or WLB. It also offers comparatively better electrical, thermal and reliability performance at reduced cost with possibility to address more Moore [decreasing technology nodes with low-k dielectrics in SoC] and more than Moore [heterogeneous integration of chips with different wafer technology as SiP solution in multi die or 3D ewlb approaches]. WLP applications are expanding into new areas and are segmenting based on I/O count and device. The foundation of passive, discrete, RF and memory device is expanding to logic ICs and MEMS. The WLP segment has matured over the past decade, with numerous sources delivering high-volume applications across multiple wafer diameters and expanding into various end-market 146

3 products. With infrastructure and high volumes in place, a major focus area is cost reduction. One of the most well known examples of a fan-out WLP structure is ewlb technology by Infineon Technologies AG. This technology uses a combination of front- and back-end manufacturing techniques with parallel processing of all the chips on a wafer, which can greatly reduce manufacturing costs. Its benefits include a smaller package footprint compared to conventional leadframe or laminate packages, medium to high I/O count, maximum connection density, as well as desirable electrical and thermal performance. It also offers a high-performance, power-efficient solution for the wireless market.[2] Figure 3. ewlb wafer after packaging with reconstitution, RDL and backend processes. The obvious solution to the challenges was some form of WLP. But two choices presented themselves: fan-in or fan-out. Fan-in WLP is an interconnection system processed directly on the wafer and compatible with motherboard technology pitch requirements. It combines conventional front- and back-end manufacturing techniques, with parallel processing of all chips. There are three stages in the process. Additional fab steps create an interconnection system on each die, with a footprint smaller than the die. Solder balls are then applied and parallel testing is performed on the wafer. Finally, wafers are sawn into individual units, which are used directly on the motherboard without the need for interposers or underfill. The ewlb approach should not be confused with bumped flip chip devices which have a finer pitch, smaller bumps and hence need underfill. Figure 1. Driving force for wafer level packaging Figure 2. Comparison of FI-WLP and ewlb (FO-WLP) ewlb TECHNOLOGY ewlb technology is addressing a wide range of factors. At one end of the spectrum is the packaging cost along with testing costs. Alongside these are physical constraints such as its footprint and height. Other parameters that were considered during the development phase included I/O density, a particular challenge for small chips with a high pin count; the need to accommodate systems in package (SiP) approaches, thermal issues related to power consumption and the device's electrical performance (including electrical parasitic and operating frequency). Figure 4. Schematics of construction of ewlb. Figure 5. ewlb.[3] SEM micrographs of cross-section of 147

4 with the shift to lead free materials, the technical limitations faced by the packaging industry are becoming more challenging. ewlb technology provides a window for packaging next generation devices in a generic, leadfree/halogen free, green packaging scheme. Figure 6. ewlb technology for bridging the interconnection gap between device level and board level interconnections. ewlb, meanwhile, is a fan-out process. The die is surrounded by a suitable material, which spreads the package footprint outside the die. Tested good dice are embedded in an artificial plastic wafer (reconstituted wafer) using a wafer level molding technique. Front end isolation and metallization processes are then used to fanout the interconnections to the surrounding area with lithography and patterning wafer level processes. Again, solder balls are applied and parallel testing is performed on wafer. The reconstituted wafer is then sawn into individual units, which are packed and shipped. With the fan-in approach, the number of interconnects and their pitch must be adapted to the chip's size. ewlb, by contrast, supports a fan out area which is adaptable and which has no restriction on ball pitch. Advantage of ewlb Next generation variations of the ewlb enabling two or more layers of routing, expanding the package size to 12x12mm, allowing for thinner packages, side by side chips within the ewlb, and eventually double sided Package on Package (PoP) ewlb are being jointly developed with our technology partners for introduction in the near future. The current BGA package technology is limited by the organic substrate capability. Moving to ewlb helps overcome such limitations and also simplifies the supply chain. Building the routing layers on package itself allows for higher integration and routing density with less metal layers. ewlb is a next generation platform that will support future integration, particularly for wireless devices and this packaging technology has a number of important features. Transition to ewlb packaging technology enables a significant reduction in recurring costs by eliminating the need for tool up of expensive substrates. NEXT GENERATION; 3D ewlb TECHNOLGOY The first generation of ewlb technology was designed for a single side and 1layerRDL approach. To address the advanced requirements in the market for higher performance and design complexity, new technical items and envelops should be developed and implemented into the current ewlb technology as shown below; Multi-layer RDL ewlb: More than one metal layer can be present in both sides; Thin ewlb : Package thickness is reduced to 0.5mm Multichip ewlb : More than one chip is embedded Large size ewlb: Package size is increased to 12x12mm 2 Double-side ewlb with vertical interconnection: Both sides of reconstituted wafer have isolation and metal layers, connected by means of conductive vias in the plastic portion of the wafer Multi-layer RDL ewlb Packaging In situations where a device may have an interconnect pad arrangement or a flip chip or wafer level component, an additional layer of lateral connections may be employed to rearrange the connections in a manner suitable for wafer level processing. This additional layer is known as a redistribution layer or RDL and fabricated from a thin layer of metal with dielectrics in between. RDL is for higher electrical performance and complex routing to meet electrical requirements. It also can provide embedded passives (R, L, C) using a multi-layer structure. Excellent performance of transmission lines (TMLs) was reported in manufacturing ewlb (Insertion loss GHz, GHz)[4]. Inductors in ewlb offer significantly better performance compared to inductors in standard on-chip technologies. Further improvement of the quality factor of the integrated capacitors by using low-loss thin-film dielectrics on ewlb was reported as well[5]. There was another report that a 77 GHz SiGe mixer packaged as an ewlb had excellent high frequency electrical performance due to the small contact dimensions and short signal pathways which decreased parasitic effects[6]. (a) BGA packaging also faces a challenge with technology nodes beyond 65nm as the device performance density drives the need for flip chip. But advanced flip chip nodes drive fine pitch combined with weaker low-k dielectric structures resulting in flip chip packages that has narrow process margin. In addition, there is a big trend in being environmentally friendly, driving lead free and halogen free, or green, material sets. With ultra low-k and interconnects pitch becoming smaller and smaller and 148

5 (b) (a) Die 1 Die 2 (b) Figure 7. (a) Photo and (b) SEM micrograph of crosssection of 2-layer RDL ewlb. Thin ewlb Packaging For mobile and handheld applications, portability is a critical factor for product selection. The thinner package can provide better board level reliability as well as lighter and thinner profile in system level. Using advanced thinning technologies, ewlb was thinned down to 250 m thickness as shown in Figure 8. The critical technical challenges were handling the thin wafer and grinding and removing of Si/epoxy material together using the same process steps. There was found more than 60% increase in TCoB (temperature Cycle on Board) performance with thinner ewlb. Drop reliability also improved significantly. Figure 9. (a) Schematics of 2-die multichip ewlb and (b) SEM micrograph of cross-section of completed mold filling between two chips. Extra Large ewlb Packaging FI-WLP has its size limitation of ~5x5mm due to board level reliability (BLR) requirement. For 1 st gen ewlb of 8x8mm, it passed successfully industry BLR standard tests. 12x12 mm ewlb packages were designed and fabricated as shown in Fig.10 with 2 or 3 dies. It was found that 12x12mm ewlb passed drop reliability test. To improve further TCoB reliability, various approaches are explored and studied in design, process as well as materials with computational simulation work. With optimized design works, 12x12mm ewlb successfully passed TCoB 500 cycles (-40/125C 2cycles/hr.). Figure 8. Thin ewlb after ewlb packaging process. Multi-chip ewlb Packaging Side-by-side multichip packaging can provide more design flexibility for SiP applications because a chip designer has more freedom in pad location as well as circuit block allocation. 3D ewlb technology utilizes very fine pitch metal line width and space as well as multi-layer RDL process, so it provides better technical solutions for multi-chip packaging. It can be used for various combinations such as, RF receiver and digital device, CMOS PA (power amplifier) and IPD (integrated passive devices) and memory and controller. ewlb uses fine pitch metallization and well controlled interconnection with wafer fab lithography process thus it has great advantage to provide better electrical performance compared to wirebonding and organic substrate technology. Figure x12mm ewlb with 2-die/3-die multichip ewlb. Double-side ewlb Packaging There is 3D ewlb approach with vertical interconnection, both sides of the reconstituted wafer will have isolation and metal layers, connected using conductive vias. It enables 3D SiP or 3D micro module. Key to the miniaturization of 3D SiP is the integration of the packaging steps as a functional part of the die and system solution. The PBGA replaced the lead frame by a printed circuit board (PCB) substrate, to which the die was electrically connected by wire bonding or flip chip technology, before covering with molding compound. ewlb takes the next step, eliminating the PCB, as well as the need to use wire-bonding or flip-chip bumps to establish electrical contacts. Without a PCB, the package is inherently thinner, without thinning the die when lower profiles are required. 149

6 As shown in Figure 11, PoP and SOW takes this integration a step further, placing one package on top of another for greater integration complexity and interconnect density. ewlb makes it a very flexible choice. ewlb technology also offers procurement flexibility, lower cost of ownership, better total system and solution costs and faster time to market. (a) (b) Figure 11. Applications of double-side ewlb packaging; (a) Package-on-package (PoP) and (b) System-on-Wafer (SOW). Table 1. Package Level Reliability Results of next generation ewlb packages. Condition Status MSL1 JEDEC-J-STD-020D MSL1, 260C Reflow (3x) - Pass Temperature Cycling -40C to 125C 1000x Pass (TC) after Precon JESD22-A104 HAST (w/o bias) after 130C / 85% RH 96hrs Pass Precon JESD22-A118 High Temperature 150C 1000h Pass Storage (HTS) JESD22-A103 BST after Multiple Reflow 260C Reflow 20x Pass * Tested by ball shear test and O/S test Board Level Reliability Results For drop reliability, next generation ewlb packages show good drop reliability as reported in 1 st gen ewlb. For 3D ewlb packages described above, all passed industry standard drop reliability tests (JEDEC. Fig. 12 shows Weibull plot of next generation ewlb packages as consolidated data. It shows quite comparable TCoB results even for 12x12mm ewlb. Currently there is more works on improving large size ewlb TCoB performance with design, structure and process optimization. Each step along the path from SiP to PoP (Package on package) to ewlb represents improvements in these two areas. Each of these packages fit unique niches. For example, if size is most important, then stacked die will yield smaller packages. Moving into PoP increases board space, but improves cost structure. ewlb, with its potential to dramatically improve cost effectiveness and reduce entire systems to the size of a postage stamp, represents the best of both worlds. SiP, as the name implies, is a technology that allows the placement of several integrated circuits in one package, providing a complete set of device electronics in a small area. This technique saves board space by integrating devices that were once spread farther apart on the circuit board. Package Level Reliability Results Table 1 shows the package level reliability result of each next generation 3D ewlb packages. They passed JEDEC (Joint Electron Device Engineering Council) standard package reliability test such as MSL (Moisture Sensitivity Level) 1 with Pb-free solder conditions. Test vehicles have 8x8mm Package with 5x5mm daisychain die and 0.5mm pitch. Total ball I/O is 192 and lead-free solder ball is used. All next generation ewlb packages successfully passed all industry standard package level reliability with ball shear test and OS(open-short) test. Figure 12. Weibull Plot of TCoB reliability of next generation ewlb Packages. Warpage Behavior with Temperature Profile Among the 3D technologies, Package-on-Package (PoP) is increasingly becoming mainstream due to its flexibility of combination and sourcing. The top package to be stacked using solder ball interconnects. For successful package on package stacking with high assembly yield, warpage of both the top and the bottom package are critical. If the warpage is too large, open solder joints may occur between the bottom package and motherboard, or between the bottom package and top package. Not only is the warpage at room temperature a concern for co-planarity measurement as a control, but warpage at solder reflow temperatures (up to 260C for lead-free solder) should also be considered since open solder joints occur during solder solidification. As a 150

7 result, warpage control at both temperature extremes is critical for 3D PoP stacking. reduced form factor and overall cost. It will go far beyond this to realize a truly seamless wafer level integrated 3D packaging module as shown in Fig. 14, that will incorporate aspects of 3D stacking, as well as Si package with embedded passive, actives in 3D ewlb packaging with TSV, flip chip, and micro-bump as well as 3-D WLPs. Figure 13. Comparison of warpage behavior of various package types; fcfbga, ewlb and EDS with temperature profile. Themo-Moire technology used for measure package warpage with temperature profile. There is warpage behaviour result with various package types, fcfbga, ewlb and EDS (Embedded Die Substrate). As shown in picture, ewlb showed almost flat during temperature profile and very stable warpage behaviour. But other packages showed serious warpage with direction change as shown in Fig. 13. Warpage variation of thin ewlb was less than 10 m in measured temperature range up to 260 o C. Further Wafer Level Integration with 3D ewlb for Heterogeneous Functionality There is a need for miniaturization at the IC, module (or sub-system), and system levels. At the IC level, scaling continues as it has over the last four decades according to Moore's Law. In addition, 3D chip stacking technology with through silicon vias (TSVs) has garnered a lot of attention recently due to its potential in improving the performance, form factor, cost, and reliability at the subsystem or module level [7-8]. There is still a great deal of research and development required to bring this heterointegration technology to cost-effective implementation with the required reliability and performance needs. In addition to the module level, we must focus on performance, form factor, cost, and reliability of the entire system [9]. Although active and stacked ICs are a highly functional and important component of the overall system, they are only one set of components; many other components including other actives, passives, power systems, wiring, and connectors must be considered in a complete system. As a result, there is a need to think at module and system levels and this need is largely met by the current technology domain in the areas of through silicon vias (TSVs), 3D stacking, and wafer level packaging. There should be further study on integration, focusing on TSVs, 3D stacking and 3D ewlb with better electrical and thermal performance, greater system reliability, and Figure 14. Total solutions for 3-D packaging with ewlb, MEMS and TSV technology. CONCLUSION Advanced packaging plays a crucial role in driving products with increased performance, low power, lower cost and smaller form factor. There are challenges associated in the application of cost effective materials and processes for various reliability requirements. The industry requires innovation in packaging technology and manufacturing to meet current demands and the ability to operate equipment in high volume with large throughput. ewlb technology is an enhancement to standard WLPs, allowing the next generation of a WLP platform due to its fan-out capability. The benefits of standard fan-in WLPs such as low packaging/assembly cost, minimum dimensions and height as well as excellent electrical and thermal performance are true for ewlb as well. The ability to integrate passives like inductors, resistors and capacitors into the various thin film layers, active/passive devices into the mold compound and 3D vertical interconnection opens additional design possibilities for new Systems-in-Package (SiP) and 3D stacked packaging. Moreover, next generation, 3D ewlb technology provides more value-add in performance and promises to be a new packaging platform that can expand its application range to various types of devices as well as 3D TSV integration for true 3D SiP systems. As the world demand for portable and mobile electronics has accelerated, the need to make semiconductors smaller, faster, lighter and cheaper has never been greater. As witnessed by the dramatic evolution of cellular phones, product differentiation today is driven by ever-expanding functionality, feature sets, multi-functionality and faster communications. At the same time, consumers have made clear their desires for feature-rich products in compact form factors to enable maximum portability. ewlb technology is successfully enabling semiconductor manufacturers to provide the smallest possible, highestperforming semiconductors. 151

8 REFERENCES [1] M. Brunnbauer, et al., Embedded Wafer Level Ball Grid Array (ewlb), Proceedings of 8th Electronic Packaging Technology Conference, Dec 2009, Singapore (2006) [2] Graham pitcher, Good things in small packages, Newelectronics, 23 June 2009, p18-19 (2009) [3] M. Brunnbauer, et al., Embedded Wafer Level Ball Grid Array (ewlb), Proceedings of 8th Electronic Packaging Technology Conference, Dec 2009, Singapore (2006) [4] Maciej Wojnowski, Klaus Pressel, Grit Sommer, Mario Engl, Package Trends for Today s and Future mm-wave Applications, EuMIC 2008, 38th European Microwave Conference [5] Badakere GURUPRASAD, Yaojian LIN, Marimuthu Pandi CHELVAM, Seung Wook YOON, Kai LIU, Robert C. FRYE, Inductors from Wafer-level Package Process for High Performance RF Applications, Proceedings of 11th EPTC 2009, Singapore, Dec (2009) [6] M. Wojnowski1, M. Engl, B. Dehlink, G. Sommer, M. Brunnbauer, K. Pressel, and R. Weigel, A 77 GHz SiGe Mixer in an Embedded Wafer Level BGA Package, Proceedings of 50th ECTC, p , May 2008, (2008) [7] Seung Wook YOON, Dae Wook YANG, Jae Hoon KOO, Meenakshi PADMANATHAN and Flynn CARSON, 3D TSV Processes and its Assembly/Packaging Technology, IEEE 3D Conference 2009, September, 2009, San Francisco, CA, US (2009) [8] Yann Guillou, 3D Integration for wireless products; industrial perspective, Newsletter on 3D Packaging, Yole development, July 2009, p.2-4 (2009) [9] Ritwik Chatterjee and Rao R. Tummala, 3D Technology and Beyond: 3D All Silicon System Module, Advanced Packaging, /display_article/339637/36/archi/none/indus/1/3d- Technology-and-Beyond:-3D-All-Silicon-System- Module/) 152