Laser Spike Annealing for sub-20nm Logic Devices
|
|
|
- Margery Stevenson
- 6 years ago
- Views:
Transcription
1 Laser Spike Annealing for sub-20nm Logic Devices Jeff Hebb, Ph.D. July 10, NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
2 Outline Introduction Pattern Loading Effects LSA Applications Dopant Activation Ti silicide Summary 2 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
3 LSA Overview v s CO 2 Laser (10.6μm) Power Control Algorithm Temperature Conversion Reflective Optics p-polarized Hot Chuck Scanning Stage Emission Detector Laser Beam V s Dwell time = w v x Silicon Note: Beam is stationary, wafer scans Key Attributes Within-die Uniformity CO2 Laser: λ ~ 10um P-polarized, brewster angle Within-wafer & Wafer-to-wafer Temperature feedback control 3 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
4 Pattern Loading Effects 4 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
5 Pattern Effects and Parametric Yield System-on-a-Chip A B T Low T High Variations in pattern density lead to local variations in the absorbed radiation during RTP or millisecond anneal This can lead to local variations in peak temperature, and variations in performance of devices which are supposed to be matched Device A gets colder during anneal Device B gets hotter during anneal Device Performance Mismatch! Pattern loading effects during millisecond annealing or RTP can cause device performance mismatch within the die parametric yield loss and degraded circuit speed 5 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
6 Pattern Loading Effects in RTP: Equipment Solution Ref 1 Highlights Lots of recent work on how to change RTP equipment solutions to suppress pattern effects: backside heating 1 or Differential Thermal Energy Control 2 These approaches are being implemented in Fabs for critical processes at advanced nodes Current implementations for dummification are not adequate for critical processes Ref 2 1. X. Yu et al, IEDM P. Timans et al., IWJT NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
7 Pattern Effects in MSA: Layout Design Solution Pre-dummification Post-dummification ΔT > 100 o C (typical) (yp Simulation showed ΔT < 50 o C SC Lin et al., Using genetic algorithm to optimize the dummy filling problem of the flash lamp anneal process in semiconductor manufacturing, J. Intell. Man. (2012) Difficult to reduce to acceptable levels due to short heat diffusion length (~100um) Difficult to make design rules to cover all layouts in a foundry environment 7 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
8 Pattern Loading Effects: Thin Film Interference PLE: DL > FLA >> LSA Re eflectivity (%) FLA/RTP Diode Laser (λ=0.8um) Re eflectivity (%) CO2 θ Bare Si wafer 340 nm oxideonsi +10% oxide thickness -10% oxide thickness 120 nm poly on oxide +10% poly thickness -10% poly thickness LSA CO 2 (λ =10.6um) P-polarized Brewsters Brewster sangle 20 Wavelength (μm) Wavelength (μm) PLE caused by thin film interference variations severe at short λ Long λ+p-pol+brewster s angle make LSA insensitive to device film variations 8 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
9 2 5 Pattern Loading Effects in Millisecond Annealing: Equipment Solution (LSA) LSA Flash Anneal / Diode Laser Fins θ Long λ Brewsters Angle No shadowing or light trapping by Fins Fins Short λ Near normal incidence Can have light trapping by Fins Silicon Silicon Measured reflectance map Measured reflectance map ΔT ~ 10 o C ΔT > 100 o C LSA provides an equipment solution for PLE in millisecond annealing 9 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
10 Applications 10 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
11 LSA Applications for 14/10nm FinFET Devices Fin Hi-k anneal Extension anneal Ti silicide S/D Anneal & Re-activation Device Applications Source/Drain extension annealing Deep Source/Drain annealing Hi-k anneal Dopant re-activation Ti Silicide LSA enables device performance improvements and leakage reduction for FinFETs 11 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
12 Source/Drain (epi) Activation Post-dep properties of Si:P Epi 1 Post-LSA properties of Si:P Epi 1 As-deposited activation efficiency is low Trade-off between growth rate and activation Activation greatly improves with LSA Further improvement with cryogenic a-si + LSA LSA improves activation and device performance by S/D activation in FinFETs 2 Sources: 1.Itokawa et al., IWJT 2012, 2.Yamashita et al, VLSI NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
13 Thermal Profiles of LSA vs. Flash Anneal T1 T2 T2 Active Carr rier Concen ntration ne ear peak (cme Carrier Con ncentration 3) ( De-activation during FLA anneal 1.E (cm -3 ) Peak Active 1E+20 1.E T2=1100C, As 3keV 2e15 Ref: H. Kennel (Intel), RTP Intermediate Temperature, T1 (C) LSA is a true low thermal budget anneal with no dopant de-activation Extra thermal budget of FLA can cause dopant de-activation slower devices 13 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
14 New Channel Materials 7nm pfet 7nm nfet Me elting Tempe erature (C) Si In.5 Ga.5 As InP Ge A. Steegen, Imec Technology Forum, Semicon 2014 New channel materials will suffer damage at much lower thermal budgets than Si Low thermal budget of LSA compatible with new channel materials 14 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
15 Arsenic Activation and Diffusion in Ge SPE Regrowth Thickness for 200usec LSA (calculated) Ge Si Highlights Ge substrates* implanted with As 5keV 2e15 (creates ~10nm self amorphizing layer) Since SPE happens in Ge at much lower temperatures than Si, use low chuck temperatures to reduce thermal budget** Splits: Peak temperature: t 600 to 900C Dwell time: 200 and 800usec Chuck temperature: RT and 200C *Note: Substrates were Ga doped to ~ 6e17cm-2 ** A higher SPE temperature typically results in higher activation * Y. Wang et al., IWJT NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
16 Arsenic Activation in Ge: Results Chuck T=200 o C Chuck T=200 o C 200usec 200 and 800 usec Significant diffusion starts above 760C at 200usec Significantly ifi more diffusion i at 800usec than 200usec * Y. Wang et al., IWJT NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
17 Arsenic Activation in Ge: Results (cont d) Rs vs. Temperature Rs vs. Xj Significant Rs reduction at 800usec due to extra diffusion Chuck temperature RT vs. 200C did not make significant difference * Y. Wang et al., IWJT NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
18 LSA for Titanium Silicide Schottky barrier height Advantages of LSA for Ti silicide φb ρc exp Higher temperature than RTA N D lower contact resistance Dopant concentration Minimal interdiffusion of gate stack layers Process control Minimal pattern effects Closed loop temperature control Becomes critical for Ti silicide where process window is smaller than Ni silicide Refs: D. James, AVS JTG Semicon West (2013) and C. Sohn et al., IEEE Trans. Elec. Dev., Apr NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
19 LSA for Ti silicide: Phase Transformation Study Y. Wang et al, IWJT 2014 Phases detected by XRD: A1: Ti A2: Ti, Ti 5 Si 3 A3: Ti 5 Si 3, possible Ti 5 Si 4 or TiSi 20nmTi with B2/B3: TiSi 2 (C40) 10nm TiN cap B4/B5: TiSi 2 (C54) Examples of φ B (G. Qttaviani et al, o C Phys. Rev. Lett., 1980): TiSi 2 : 0.6V TiSi: 0.5V NiSi: 0.67V Low Rs not required Low Rc is the goal (low φ B ) No need to anneal at temperatures greater than ~1000C, where gate stack could be compromised 19 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
20 Measured reflectance: LSA (10.6um) Pattern Loading Effects (PLE) For Silicides Within-die temperature distribution: Simulated from measured reflectance maps 40 Measured reflectance: Diode Laser (0.8um) ΔT ~ 10C ensity obability D Pr Diode laser LSA Ti Silicide Process Window (estimated) ΔT > 100C T ( o C) Severe PLE of diode laser could impact yield for Ti silicide (PLE >100C) PLE of LSA is well within the process window (PLE~10C) 20 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
21 Summary Long-wavelength LSA provides an equipment-design solution for pattern loading effects in millisecond annealing LSA plays a critical role in reducing series resistance and leakage in today s FinFETs through multiple applications As sub-10nm devices migrate to new channel materials, low thermal budget annealing approaches such as LSA will be become more critical 21 NCCAVS Junction Technology Group Semicon West Meeting July 10, 2014
Process Uniformity Improvements for LSA Millisecond Annealing in the FinFET era Jim McWhirter, Ph.D. July 16, 2015
1 NCCAVS Junction Technology Group SEMICON West 2015 Meeting July 16, 2015 Process Uniformity Improvements for LSA Millisecond Annealing in the FinFET era Jim McWhirter, Ph.D. July 16, 2015 DEVICE PERFORMANCE
Contact Resistance Reduction using Advanced Implant and Anneal Techniques for 7nm Node and Beyond
Contact Resistance Reduction using Advanced Implant and Anneal Techniques for 7nm Node and Beyond Fareen Adeni Khaja Global Product Manager, Front End Products Transistor and Interconnect Group NCCAVS
SCREEN Thermal Products
SCREEN Thermal Products July 16, 2015 NCCAVS Junction Technology Group Semicon West San Francisco, CA 1 SE-75-1628-L1 Agenda Thermal Products Overview Laser Anneal Presentation Formation of Ge n+/p junction
Implant And Annealing Process Integration Issues To Reduce Device Variability For <10nm p+ & n+ Ultra-Shallow junctions
Implant And Annealing Process Integration Issues To Reduce Device Variability For
Ultra-Shallow Junction Formation on 3D Silicon and Germanium Device Structures by Ion Energy Decoupled Plasma Doping
Ultra-Shallow Junction Formation on 3D Silicon and Germanium Device Structures by Ion Energy Decoupled Plasma Doping YS Kim & Hyuckjun Kown CTD, Lam Research 2017 Lam Research Corp. EAG 2017 1 Overview
EECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)
Chapter 3 Silicon Device Fabrication Technology
Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale
Design Consideration and Effect of Parameter Variation on sub-40nm Bulk MOSFET using TCAD Tool
International Journal of Electronics and Communication Engineering. ISSN 0974-2166 Volume 4, Number 3 (2011), pp. 267-274 International Research Publication House http://www.irphouse.com Design Consideration
A Study on Thermal Stability Improvement in Ni Germanide/p-Ge using Co interlayer for Ge MOSFETs
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.17, NO.2, APRIL, 217 ISSN(Print) 1598-1657 https://doi.org/.5573/jsts.217.17.2.277 ISSN(Online) 2233-4866 A Study on Thermal Stability Improvement in
A Proposal of Schottky Barrier Height Tuning Method with Interface controlled Ni/Si stacked Silicidation Process
222 nd ECS Meeting A Proposal of Schottky arrier Height Tuning Method with Interface controlled Ni/Si stacked Silicidation Process Y. Tamura 1, R. Yoshihara 1, K. Kakushima 2, P. Ahmet 1, Y. Kataoka 2,
NiPt salicide process improvement for 28nm CMOS with Pt(10%) additive
NiPt salicide process improvement for 28nm CMOS with Pt(10%) additive Jerander Lai, Yi-Wei Chen, Nien-Ting Ho, Yu Shan Shiu, J F Lin Shuen Chen Lei, Nick ZH Chang, Ling Chun Chou, C C Huang, and J Y Wu
Low D it High-k/In 0.53 Ga 0.47 As Gate Stack with CET down to 0.73 nm and Thermally Stable Silicide Contact by Suppression of Interfacial Reaction
IEDM 2013 Dec 9 th, 2013 Low D it High-k/In 0.53 Ga 0.47 As Gate Stack with CET down to 0.73 nm and Thermally Stable Silicide Contact by Suppression of Interfacial Reaction D. Hassan Zadeh, H. Oomine,
Wet Processing Techniques for Achieving Ultra-shallow Junctions in Future CMOS Devices
Accelerating the next technology revolution Wet Processing Techniques for Achieving Ultra-shallow Junctions in Future CMOS Devices Joel Barnett, Richard Hill, Chris Hobbs and Prashant Majhi 07-October-2010
Junction formation in Ge by coimplant. and pre-heating techniques
Junction formation in Ge by coimplant. and pre-heating techniques Takashi Kuroi Nissin Ion Equipment Co., Ltd. 0 Content Introduction Purpose and Motivation Experimental Acceptor impurity implanted Germanium
CMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI
CMOS Technology Flow varies with process types & company N-Well CMOS Twin-Well CMOS STI Start with substrate selection Type: n or p Doping level, resistivity Orientation, 100, or 101, etc Other parameters
Semiconductor Manufacturing Technology. IC Fabrication Process Overview
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 00 by Prentice Hall Chapter 9 IC Fabrication Process Overview /4 Objectives After studying the material in this chapter, you
MOS Front-End. Field effect transistor
MOS Front-End Back-end Transistor Contact Front-end p-well STI n-well Front-end-of-line includes substrate, isolation, wells, transistor, silicide Field effect transistor MOSFET: Metal-Oxide-Semiconductor
Fig.1: Comparison of various implant species energy and dose on surface amorphous layer depth.
Liquid Phase Epitaxy (LPE) Formation of Localized High Quality and Mobility Ge & SiGe by High Dose Ge-Implantation with Laser Melt Annealing for 10nm and 7nm Node CMOS Technology John Borland 1,2, Michiro
FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag
FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules EE 432 VLSI Modeling and Design 2 CMOS Fabrication
Characterization and Improvement of Reverse Leakage Current of Shallow Silicided Junction for Sub-100 nm CMOS Technology Utilizing N 2 PAI
Journal of the Korean Physical Society, Vol. 49, December 2006, pp. S795 S799 Characterization and Improvement of Reverse Leakage Current of Shallow Silicided Junction for Sub-100 nm CMOS Technology Utilizing
EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009
Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/2009 300mm Fab Tour http://www-03.ibm.com/technology/manufacturing/technology_tour_300mm_foundry.html Overview of IC Technology
Surface Passivation and Characterization of Germanium Channel Field Effect Transistor Together with Source/Drain Engineering
Surface Passivation and Characterization of Germanium Channel Field Effect Transistor Together with Source/Drain Engineering Gaurav Thareja Nishi Group, Electrical Engineering Stanford University ERC Tele-seminar
SiC high voltage device development
SiC high voltage device development 2006. 11. 30 KERI Power Semiconductor Group outline 1. Device design & simulation for power devices 2. SiC power diode process development Ion implantation & activation
COMPATIBILITY OF THE ALTERNATIVE SEED LAYER (ASL) PROCESS WITH MONO- Si AND POLY-Si SUBSTRATES PATTERNED BY LASER OR WET ETCHING
COMPATIBILITY OF THE ALTERNATIVE SEED LAYER (ASL) PROCESS WITH MONO- Si AND POLY-Si SUBSTRATES PATTERNED BY LASER OR WET ETCHING Lynne Michaelson 1, Anh Viet Nguyen 2, Krystal Munoz 1, Jonathan C. Wang
Lecture 0: Introduction
Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power
Process Integration. MEMS Release Techniques Sacrificial Layer Removal Substrate Undercut
Process Integration Self-aligned Techniques LOCOS- self-aligned channel stop Self-aligned Source/Drain Lightly Doped Drain (LDD) Self-aligned silicide (SALICIDE) Self-aligned oxide gap MEMS Release Techniques
Chapter 5 Thermal Processes
Chapter 5 Thermal Processes 1 Topics Introduction Hardware Oxidation Diffusion Annealing Post-Implantation Alloying Reflow High Temp CVD Epi Poly Silicon Nitride RTP RTA RTP Future Trends 2 Definition
Conformal Doping for FinFETs by Self-Regulatory Plasma Doping. 16 nm. Bell Shockley Bardeen Brattain 3. Kilby 1959 Noyce 3) MOS FET
Conformal Doping for FinFETs by Self-Regulatory Plasma Doping Yuichiro Sasaki Katsumi Okashita Bunji Mizuno FETField Effect Transistor SRPD : Self-Regulatory Plasma Doping PD : Plasma Doping 11 %FETFET
Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.
Figure 2.1 (p. 58) Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) selective oxide removal, (c) deposition of dopant atoms on wafer, (d) diffusion of dopant atoms into exposed
Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very
Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very high voltages (10-600 KeV) Use analyzer to selection charge/mass
Atomic Level Material and Device Analysis for FinFET and Nanowire Design
Atomic Level Material and Device Analysis for FinFET and Nanowire Design Victor Moroz, Søren Smidstrup, Munkang Choi, and Alexei Svizhenko July 13, Junction Technologies User Group Meeting 2018 Synopsys,
Low Thermal Budget NiSi Films on SiGe Alloys
Mat. Res. Soc. Symp. Proc. Vol. 745 2003 Materials Research Society N6.6.1 Low Thermal Budget NiSi Films on SiGe Alloys S. K. Ray 1,T.N.Adam,G.S.Kar 1,C.P.SwannandJ.Kolodzey Department of Electrical and
Fabrication and Layout
ECEN454 Digital Integrated Circuit Design Fabrication and Layout ECEN 454 3.1 A Glimpse at MOS Device Polysilicon Aluminum ECEN 475 4.2 1 Material Classification Insulators Glass, diamond, silicon oxide
1. Introduction. What is implantation? Advantages
Ion implantation Contents 1. Introduction 2. Ion range 3. implantation profiles 4. ion channeling 5. ion implantation-induced damage 6. annealing behavior of the damage 7. process consideration 8. comparison
FABRICATION of MOSFETs
FABRICATION of MOSFETs CMOS fabrication sequence -p-type silicon substrate wafer -creation of n-well regions for pmos transistors, -impurity implantation into the substrate. -thick oxide is grown in the
UT Austin, ECE Department VLSI Design 2. CMOS Fabrication, Layout Rules
2. CMOS Fabrication, Layout, Design Rules Last module: Introduction to the course How a transistor works CMOS transistors This module: CMOS Fabrication Design Rules CMOS Fabrication CMOS transistors are
Chapter 4 : ULSI Process Integration (0.18 m CMOS Process)
Chapter : ULSI Process Integration (0.8 m CMOS Process) Reference. Semiconductor Manufacturing Technology : Michael Quirk and Julian Serda (00). - (00). Semiconductor Physics and Devices- Basic Principles(/e)
the surface of a wafer, usually silicone. In this process, an oxidizing agent diffuses into the wafer
Analysis of Oxide Thickness Measurement Techniques of SiO2: Nanometrics Nanospec Reflectometer and Color Chart Eman Mousa Alhajji North Carolina State University Department of Materials Science and Engineering
Monitoring Ion Implantation and Annealing Precision to Reduce Device Variability
Monitoring Ion Implantation and Annealing Precision to Reduce Device Variability John Borland, J.O.B. Technologies, Aiea, Hawaii; Wade Krull, SemEquip, North Billercia, Mass.; Masaharu Tanjo, Nissin Ion
Make sure the exam paper has 9 pages total (including cover page)
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Fall 2010 EE143 Midterm Exam #2 Family Name First name SID Signature Solution Make sure the exam
KEYWORDS: MOSFET, reverse short-channel effect, transient enhanced diffusion, arsenic, phosphorus, source, drain, ion implantation
Jpn. J. Appl. Phys. Vol. 42 (2003) pp. 2654 2659 Part 1, No. 5A, May 2003 #2003 The Japan Society of Applied Physics -Assisted Low-Energy Arsenic Implantation Technology for N-Channel Metal Oxide Semiconductor
Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +,
Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +, 2+ or 3+ ionization) Use analyzer to selection charge/mass
A Novel Low Temperature Self-Aligned Field Induced Drain Polycrystalline Silicon Thin Film Transistor by Using Selective Side-Etching Process
Chapter 3 A Novel Low Temperature Self-Aligned Field Induced Drain Polycrystalline Silicon Thin Film Transistor by Using Selective Side-Etching Process 3.1 Introduction Low-temperature poly-si (LTPS) TFTs
Czochralski Crystal Growth
Czochralski Crystal Growth Crystal Pulling Crystal Ingots Shaping and Polishing 300 mm wafer 1 2 Advantage of larger diameter wafers Wafer area larger Chip area larger 3 4 Large-Diameter Wafer Handling
Process Integration. NMOS Generic NMOS Process Flow. CMOS - The MOSIS Process Flow
Process Integration Self-aligned Techniques LOCOS- self-aligned channel stop Self-aligned Source/Drain Lightly Doped Drain (LDD) Self-aligned silicide (SALICIDE) Self-aligned oxide gap MEMS Release Techniques
行政院國家科學委員會補助專題研究計畫成果報告
NSC89-2215-E-009-104 89 08 01 90 07 31 Fabrication and Characterization of Low-Temperature Polysilicon Thin Film Transistors with Novel Self-Aligned Sub-Gate Structures NSC89-2215-E009-104 (FID) self-aligned
Problem 1 Lab Questions ( 20 points total)
Problem 1 Lab Questions ( 20 points total) (a) (3 points ) In our EE143 lab, we use Phosphorus for the source and drain diffusion. However, most advanced processes use Arsenic. What is the advantage of
I. INTRODUCTION. Horyeong Lee 1, Meng Li 1, Jungwoo Oh 2, and Hi-Deok Lee 1,* Schottky diode, effective Schottky barrier height, n- channel MOSFETs
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.1, FEBRUARY, 2015 http://dx.doi.org/10.5573/jsts.2015.15.1.041 A Study of the Dependence of Effective Schottky Barrier Height in Ni Silicide/n-Si
Review of CMOS Processing Technology
- Scaling and Integration Moore s Law Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from
HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:
HOMEWORK 4 and 5 March 15, 2009 Homework is due on Monday March 30, 2009 in Class. Chapter 7 Answer the following questions from the Course Textbook: 7.2, 7.3, 7.4, 7.5, 7.6*, 7.7, 7.9*, 7.10*, 7.16, 7.17*,
CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook
CMOS Fabrication Dr. Bassam Jamil Adopted from slides of the textbook CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different
Lecture 22: Integrated circuit fabrication
Lecture 22: Integrated circuit fabrication Contents 1 Introduction 1 2 Layering 4 3 Patterning 7 4 Doping 8 4.1 Thermal diffusion......................... 10 4.2 Ion implantation.........................
Chapter 3 CMOS processing technology
Chapter 3 CMOS processing technology (How to make a CMOS?) Si + impurity acceptors(p-type) donors (n-type) p-type + n-type => pn junction (I-V) 3.1.1 (Wafer) Wafer = A disk of silicon (0.25 mm - 1 mm thick),
Integrated Circuit Engineering Corporation EPROM
EPROM There was lots of discussion and many technical papers covering the promises of EPROM (typically Flash) at the IEDM conference last December, but here as in the other memory areas, not much in the
SEMATECH Symposium Korea 2012 Practical Analysis Techniques of Nanostructured Semiconductors by Electron Microscopy
SEMATECH Symposium Korea 2012 Practical Analysis Techniques of Nanostructured Semiconductors by Electron Microscopy Jun-Mo Yang, Ph.D. Measurement & Analysis Team National NanoFab Center, Korea Introduction
EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #9
Issued: Tuesday, Nov. 11, 2014 PROLEM SET #9 Due: Wednesday, Nov. 19, 2010, 8:00 a.m. in the EE 143 homework box near 140 Cory 1. The following pages comprise an actual pwell CMOS process flow with poly-to-poly
Chapter 2 Manufacturing Process
Digital Integrated Circuits A Design Perspective Chapter 2 Manufacturing Process 1 CMOS Process 2 CMOS Process (n-well) Both NMOS and PMOS must be built in the same silicon material. PMOS in n-well NMOS
VLSI. Lecture 1. Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University. Based on slides of David Money Harris
VLSI Lecture 1 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University Based on slides of David Money Harris Goals of This Course Learn the principles of VLSI design Learn to design
Semiconductor Device Fabrication
5 May 2003 Review Homework 6 Semiconductor Device Fabrication William Shockley, 1945 The network before the internet Bell Labs established a group to develop a semiconductor replacement for the vacuum
Performance Predictions for Scaled Process-induced Strained-Si CMOS
Performance Predictions for Scaled Process-induced Strained-Si CMOS G Ranganayakulu and C K Maiti Department of Electronics and ECE, IIT Kharagpur, Kharagpur 721302, India Abstract: Device and circuit
CMOS VLSI Design. Introduction. All materials are from the textbook Weste and Harris, 3 rd Edition CMOS VLSI DESIGN. Introduction
CMOS VLSI Design Introduction ll materials are from the textbook Weste and Harris, 3 rd Edition CMOS VLSI DESIGN Introduction Chapter previews the entire field, subsequent chapters elaborate on specific
ECSE 6300 IC Fabrication Laboratory Lecture 8 Metallization. Die Image
ECSE 6300 IC Fabrication Laboratory Lecture 8 Metallization Prof. Rensselaer Polytechnic Institute Troy, NY 12180 Office: CII-6229 Tel.: (518) 276-2909 e-mails: luj@rpi.edu http://www.ecse.rpi.edu/courses/s18/ecse
Schottky-Barrier-Height Modulation of Ni Silicide/Si Contacts by Insertion of Thin Er or Pt Layers
Schottky-Barrier-Height Modulation of Ni Silicide/Si Contacts by Insertion of Thin Er or Pt Layers Yoshihisa Ohishi 1, Kohei Noguchi 1, Kuniyuki Kakushima 2, Parhat Ahmet 1, Kazuo Tsutsui 2, Nobuyuki Sugii
Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design
Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each
Interconnects. Outline. Interconnect scaling issues Aluminum technology Copper technology. Properties of Interconnect Materials
Interconnects Outline Interconnect scaling issues Aluminum technology Copper technology 1 Properties of Interconnect Materials Metals Silicides Barriers Material Thin film Melting resistivity point ( C)
Impacts of Back Grind Damage on Si Wafer Thinning for 3D Integration
Impacts of Back Grind Damage on Si Wafer Thinning for 3D Integration Tomoji Nakamura, Yoriko Mizushima, Young-suk Kim, Akira Uedono, and Takayuki Ohba Fujitsu Laboratories Ltd., University of Tsukuba Tokyo
Optical pumping and final metal investigation
Optical pumping and final metal investigation FLOORS Optical pumping of unstressed device Optical pumping of stressed device Stressing points Trap analysis t=0, As Built t>0, Degradation Final Metal Study
ECE520 VLSI Design. Lecture 7: CMOS Manufacturing Process. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 7: CMOS Manufacturing Process Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last
Rapid Thermal Processing (RTP) Dr. Lynn Fuller
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Rapid Thermal Processing (RTP) Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585)
EE 143 CMOS Process Flow
EE 143 CMOS rocess Flow CT 84 D D G Sub G Sub S S G D S G D S + + + + - MOS Substrate Well - MOS Substrate EE 143 CMOS rocess Flow CT 85 hotoresist Si 3 4 SiO 2 Substrate selection: moderately high resistivity,
Resistivity of Ni silicide nanowires and its dependence on Ni film thickness used for the formation
ECS 224 th MEETING. 2013 o Resistivity of Ni silicide nanowires and its dependence on Ni film thickness used for the formation J. Song 1, K. Matsumoto 1, K. Kakushima 2, Y. Kataoka 2, A. Nishiyama 2, N.Sugii
More on oxidation. Oxidation systems Measuring oxide thickness Substrate orientation Thin oxides Oxide quality Si/SiO2 interface Hafnium oxide
More on oxidation Oxidation systems Measuring oxide thickness Substrate orientation Thin oxides Oxide quality Si/SiO2 interface Hafnium oxide EE 432/532 oxide measurements, etc 1 Oxidation systems silicon
Mark T. Bohr Intel Senior Fellow, Technology and Manufacturing Group Director, Process Architecture and Integration INTEL CORPORATION
Mark T. Bohr Intel Senior Fellow, Technology and Manufacturing Group Director, Process Architecture and Integration INTEL CORPORATION Patents» 6762464, N-P butting connections on SOI substrates, 7/13/2004.»
MOLYBDENUM AS A GATE ELECTRODE FOR DEEP SUB-MICRON CMOS TECHNOLOGY
Mat. Res. Soc. Symp. Vol. 611 2000 Materials Research Society MOLYBDENUM AS A GATE ELECTRODE FOR DEEP SUB-MICRON CMOS TECHNOLOGY Pushkar Ranade, Yee-Chia Yeo, Qiang Lu, Hideki Takeuchi, Tsu-Jae King, Chenming
Lecture 1A: Manufacturing& Layout
Introduction to CMOS VLSI Design Lecture 1A: Manufacturing& Layout David Harris Harvey Mudd College Spring 2004 Steven Levitan Fall 2008 1 The Manufacturing Process For a great tour through the IC manufacturing
Abstract --- We investigated phosphorus and boon implanted emitter and selective emitter junction formation
Selective and Homo Emitter Junction Formation Using Precise Dopant Concentration Control by Ion Implantation and Microwave, Laser or Furnace Annealing Techniques John Borland 1, Victor Moroz 2, Joanne
9/4/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter II CMOS Manufacturing Process 1 Dual-Well Trench-Isolated CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 p-well poly n-well SiO 2 n+ p-epi p+ p+ 2 Schematic Layout
Epi Replacement and up to 30% Process Simplification in a CMOS Foundry Environment Using the BILLI Structure
Epi Replacement and up to 30% Process Simplification in a CMOS Foundry Environment Using the BILLI Structure Martin Teague, Susan Johns, Rob Haase, Paul Jones & Peter Lister Newport Waferfab Limited, Cardiff
EE-612: Lecture 28: Overview of SOI Technology
EE-612: Lecture 28: Overview of SOI Technology Mark Lundstrom Electrical and Computer Engineering Purdue University West Lafayette, IN USA Fall 2006 NCN www.nanohub.org Lundstrom EE-612 F06 1 outline 1)
Thin metal film 4H-SiC vertical Schottky photodiodes for UV Index monitoring
Thin metal film 4H-SiC vertical Schottky photodiodes for UV Index monitoring Massimo Mazzillo 1, Antonella Sciuto 2, Paolo Badalà 1, Beatrice Carbone 1, Alfio Russo 1 and Salvatore Coffa 1 1 STMicroelectronics,
Microfabrication of Integrated Circuits
Microfabrication of Integrated Circuits OUTLINE History Basic Processes Implant; Oxidation; Photolithography; Masks Layout and Process Flow Device Cross Section Evolution Lecture 38, 12/05/05 Reading This
A LOW SERIES RESISTANCE, HIGH DENSITY, TRENCH CAPACITOR FOR HIGH-FREQUENCY APPLICATIONS
A LOW SERIES RESISTANCE, HIGH DENSITY, TRENCH CAPACITOR FOR HIGH-FREQUENCY APPLICATIONS Gordon Grivna, Sudhama Shastri, Yujing Wu, & Will Cai Sept, 2008 www.onsemi.com Presentation Outline 1. Introduction
Chapter 2 Problems. The CMOS technology we need to realize is shown below, from Figure 1-34 in the text. S P + N P + N WELL P +
Chapter 2 roblems 2.1 Sketch a process flow that would result in the structure shown in Figure 1-34 by drawing a series of drawings similar to those in this chapter. You only need to describe the flow
Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther
EECS 40 Spring 2003 Lecture 19 Microfabrication 4/1/03 Prof. ndy Neureuther How are Integrated Circuits made? Silicon wafers Oxide formation by growth or deposition Other films Pattern transfer by lithography
Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +,
Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +, 2+ or 3+ ionization) Use analyzer to selection charge/mass
Doping and Oxidation
Technische Universität Graz Institute of Solid State Physics Doping and Oxidation Franssila: Chapters 13,14, 15 Peter Hadley Technische Universität Graz Institute of Solid State Physics Doping Add donors
Lect. 2: Basics of Si Technology
Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from fractions of nanometer to several micro-meters
Making III-V contact with silicon substrates
106Technology focus: III-Vs on silicon Making III-V contact with silicon substrates High-speed logic, high-frequency/high-power transistors and photonics systems could benefit from marrying with silicon
Silicon Wafer Processing PAKAGING AND TEST
Silicon Wafer Processing PAKAGING AND TEST Parametrical test using test structures regularly distributed in the wafer Wafer die test marking defective dies dies separation die fixing (not marked as defective)
45nm Node p+ USJ Formation With High Dopant Activation And Low Damage
45nm Node p+ USJ Formation With High Dopant Activation And Low Damage John Borland 1, Seiichi Shishiguchi 2, Akira Mineji 2, Wade Krull 3, Dale Jacobson 3, Masayasu Tanjyo 4, Wilfried Lerch 5, Silke Paul
Semiconductor Technology
Semiconductor Technology from A to Z Oxidation www.halbleiter.org Contents Contents List of Figures List of Tables II III 1 Oxidation 1 1.1 Overview..................................... 1 1.1.1 Application...............................
Complementary Metal Oxide Semiconductor (CMOS)
Technische Universität Graz Institute of Solid State Physics Complementary Metal Oxide Semiconductor (CMOS) Franssila: Chapters 26,28 Technische Universität Graz Institute of Solid State Physics Complementary
EE 330 Lecture 9. IC Fabrication Technology Part 2
EE 330 Lecture 9 IC Fabrication Technology Part 2 Quiz 8 A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this
New approaches to classical Silicon Solar Cells
New approaches to classical Silicon Solar Cells The SSTEP Project Solar-grade Silicon by Transfer and EPitaxy G.Amato - INRIM, Torino G. Borionetti- MEMC, Novara Contents 1. What s the porous Si? 2. Epitaxy
4 Concept of Ripple Pyrometry during Flash Lamp Annealing
4 Concept of Ripple Pyrometry during Flash Lamp Annealing 4.1 Review on Temperature Measurement for Flash Lamp Annealing Several different efforts have been undertaken to measure temperature by contactless
Development of High Voltage Silicon Carbide MOSFET Devices in KERI
Development of High Voltage Silicon Carbide MOSFET Devices in KERI 2014. 06. Kim, Sang Cheol (sckim@keri.re.kr) Power Semiconductor Device Research Center Korea Electrotechnology Research Institute Contents
Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica
Microelettronica Planar Technology for Silicon Integrated Circuits Fabrication 26/02/2017 A. Neviani - Microelettronica Introduction Simplified crosssection of an nmosfet and a pmosfet Simplified crosssection
Lecture 200 BiCMOS Technology (12/12/01) Page 200-1
Lecture 200 BiCMOS Technology (12/12/01) Page 200-1 LECTURE 200 BICMOS TECHNOLOGY (READING: Text-Sec. 2.11) INTRODUCTION Objective Illustrate BiCMOS technology Outline Introduction Physical process illustration
Resistive switching of CeO x /SiO 2 stacked film based on anodic oxidation and breakdown
Feb. 19 th, 2015 WIMNACT-45 Resistive switching of /SiO 2 stacked film based on anodic oxidation and breakdown K. Kakushima Tokyo Institute of Technology 1 Introduction to resistive RAM (RRAM) Reset OFF
Complexity of IC Metallization. Early 21 st Century IC Technology
EECS 42 Introduction to Digital Electronics Lecture # 25 Microfabrication Handout of This Lecture. Today: how are Integrated Circuits made? Silicon wafers Oxide formation by growth or deposition Other