3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan
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1 3D Package Technologies Review with Gap Analysis for Mobile Application Requirements Apr 22, 2014 STATS ChipPAC Japan T.Nishio
2 Contents Package trends and roadmap update Advanced technology update Fine pitch & low cost flip chip (fccube ) Wafer level package (ewlb) Silicon level integration (TSV) Summary
3 Contents Package trends and roadmap update Advanced technology update Fine pitch & low cost flip chip (fccube ) Wafer level package (ewlb) Silicon level integration (TSV) Summary
4 Applications Driving Growth Through Semi TAM Growth Differences Source: Gartner, June 13 Wireless $15.0 Compute Industrial Storage Auto Wired Consumer Mili/Aero $10.3 $7.4 $4.8 $6.9 $2.6 $1.5 $0.3 $0.0 $5.0 $10.0 $15.0 $20.0 Mobile PC Gartner Webinar Semiconductor Forecast: Jun 13 Update
5 Package Roadmap Update to Fill the Gaps Application processor, Base band Delayed one generation of Wide IO GAP; Power consumption vs Performance fcfbga PoP fccube PoP GAP; Flip Chip Cost Cu-Column Bump on Lead MUF /MR -> CUF / MR -> NPI / TCB 3D TSV GAP; Cost vs Density GAP; Low profile to reserve more space RF, PM, WiFI, BT, GPS, etc chip ewlb PoP (1.5S) GAP; Low profile GAP Space/Performance ewlb-3d F-t-F WLCSP Network, PC, Game, DTV ewlb GAP; Ball counts vs Size GAP; Dependency of Wide IO infrastructure ewlb-3d IPD/ Passive in ewlb FCBGA - LF Solder GAP; Cost reduction/ EM performance fccube 2.5D/3D TSV Hybrid Memory Cube
6 Contents Package trends and roadmap update Advanced technology update Fine pitch & low cost flip chip (fccube ) Wafer level package (ewlb) Silicon level integration (TSV) Summary
7 -A Key Elements fccube Technology Gap; Substrate cost, Under fill cost Cu column bump & BOL Interconnection Dense routing w/ relaxed substrate design rules Dramatic reduction of ELK stress & elimination of ELK damage in Si Enhanced Assembly Hi throughput jet underfill for fcbga & Mold Underfill (MUF) for fcfbga Wide boat format for fcbga & 1-up high density matrix strip for fcfbga fcfbga Reduced Substrate Complexity Majority of devices routable in 2-lyr laminate using no-sop/ BOL/open SRO design Relaxed substrate des rules (SRO registration and L/S) by virtue of Open SR design
8 Further Enhancements of Cu pillar - Oblong Bump Gap; Bump pitch 40um Bump Diameter 33 25x50um Oblong Bump 25 13um Larger bump to trace spacing at a given pitch Larger Process window w/ respect to bump bridge 17um Benefits Larger bump-to-trace spacing More relaxed line width/spacing Applicable to Mass Reflow (MR) & TC Bonding (TCB) Larger solder cap volume Enhanced CA yield (non-wets) Possibly improved EM performance Possibly better ILD crack protection w/ increased UBM area
9 Coreless Embedded Trace Substrate (ETS) Gap; Bump pitch, Chip Height4 2L Conventional Coreless 2L ETS 4L 1/2/1 Coreless 3L ETS Cost reduction compared to normal pattern substrate Mainly by elimination of PCF needed for SAP Normal BOL Lower cost for conventional SAP design rules ( < 25/25um L/S) BOL in ETS Flatter surface provides a better path for CUF or EMC flow under the die Thinner substrate Higher process margin with respect to bump-to-trace short Leads to wider process window for fccube & enables tighter bump pitch Currently in HVM fcfbga MUF
10 fccube: Preventing ELK Damage Stress Simulation Bump Type & Design 9.0 Gap; Ultra Low K damage Volume cross-section Max Principle Stress(10^2 Mpa) Die thickness: 150um Low CTE Core S/M Core AL Pad Cu column Bump BOL Die ELK Passivation Cu + Solder cap on BOC Cu + Solder cap on BOL Solder Bump on BOC Solder Bump on BOL UBM Cu column The thermal loading is from solder melting temp to room temp, then checked the maximum principle stress of the silicon Higher stress in Cu Column, but it can be reduced by BOL pad structure
11 Contents Package trends and Road map update Advanced Technology update Fine pitch & Low cost flip chip (fccube ) Wafer level package (ewlb) Silicon level integration (TSV) Summary
12 What is ewlb? Gap; Die Size vs Bump Counts Wafer Level Packaging technology that utilizes a well developed wafer bumping infrastructure with an innovative wafer reconstitution process to package Known Good Dice Uses mold compound to support the fan-out I/Os Fan-In WLP PKG size = Chip size ewlb/fan-out WLP PKG size > Chip size chip chip Fan-In Interconnects only - Number and pitch of Interconnects must be adapted to the chip size Only Single chip packaging solution ewlb expands the application space for Wafer Level Packaging! Fan-out Interconnects - #, Pitch of Interconnect is INDEPENDENT of chip size Single/Multi/3D chip packaging solution Improved Yield with KGD
13 ewlb Positioning Gap; Cost Performance Over FBGA (*1): Slightly smaller footprint (clearance distances to the edges are smaller) Better signal integrity and power integrity Thinner package Lower thermal resistance Simplified supply chain infrastructure Lower cost until 5 mm size Pkg Cost FCCSP FBGA ewlb Over fan-in WLCSP (*1): Higher board-level reliability Fan-out area to counter the pad limitation issue, adaptable to customer needs Only confirmed good dice are packaged Built-in back-side protection No restriction in bump pitch chip Pkg Size Over flip chip BGA (*1): Slightly smaller footprint (clearance distances to the edges are smaller) Thinner package Substrate-less package (shorter interconnections meaning higher electrical performance and cheaper in the long run) Future potential for SiP and 3D integration Lower thermal resistance Simplified supply chain infrastructure Signal Integrity comparison for 10x9 mm ewlb vs 11x11 mm fccsp Lower cost until 12 mm size *1; Yole presented advantages of SEMI Networking Day: Packaging - Key for System Integration, Jun 13
14 Double-sided ewlb for 3D Packaging Gap; vs Embedded Substrate Top View ewlb PoP (ewlb + ewlb) Total PKG height ~ 1.3mm Bottom View Courtesy of 3D ewlb JDA
15 Advanced FO-WLP Technology Ultra fine pad pitch (<50um) Gap; vs Embedded Substrate 28nm ELK Device Plated Cu RDL 35 m pad pitch IPD, SMD/discrete embedding HVM from Q for 40nm Qualified 28nm devices EMC IPD embedding 0201 MLCC
16 ewlb : Themo-Moire, High Temperature Warpage Measurement Gap; vs Flip Chip fcvfbga,7x7mm, 191LD NSP PKG height 0.95 mm Die 4.46 x 5.65 x 0.19 mm ewlb 8x8mm, 182I/O PKG height 0.7 mm Die 5 x 5 x 0.45 mm
17 ewlb-pop Packages Gap; vs Flip Chip 30% height reduction with ewlb in % height reduction in 2013 Total PoP Height 0.8mm 12x12 mm ewlb-pop 14 x 14 mm ewlb-pop Presented in imaps Europe (MINAPAD) April 2012
18 Large Panel Carrier Manufacturing Technology Gap; vs Embedded Substrate Dramatic cost & throughput improvement with expanded carrier size 2010 Near Future Starting (2009) Panel 200 mm 1x 300 mm 2.2 x 4 10 x
19 Contents Package trends and roadmap update Advanced technology update Fine pitch & low cost flip chip (fccube ) Wafer level package (ewlb) Silicon level integration (TSV) Summary
20 TSV Ecosystem with Foundry & OSAT partnership Gap; Quality Owner TSV BEOL Packaging Assembly Test TSV MEOL OSAT TSV Fab. Foundry IDM & Foundry Full-Turnkey Virtual TSV-ecosystem Open ecosystem collaborative approach drives proven and reliable 3D IC solutions for the semiconductor market by combining the foundry partner s robust, leading-edge TSV FEOL with OSAT s TSV MEOL & BEOL assembly technology. 20
21 TSV Assembly Process Flow Example (3D IC TSV) Gap; TCB cost MEOL TSV wafer Dicing WideIO Memory Wafer 3D TSV IC Underfill - NCP CtS Bonding Grinding Dicing Substrate Chip-to-Substrate bonding Thermocompression Bonding Underfill - NCP CtC Bonding Molding Ball Mount Marking/Singulation Testing Wide IO Memory 3D TSV IC Chip-to-Chip bonding Thermocompression Bonding
22 40/50um bump pitch Chip-to-Chip Bonding Gap; TCB cost Wide IO Memory 3D TSV IC Device Wide IO memory (40/50um pitch) bonding on TSV 3D IC
23 3D IC TSV Stacked Packaging Gap; TCB cost Chip-to-Substrate & Chip-to-Chip Thermo-compression Bonding (TCB) for 3D TSV IC packaging 40 m
24 Contents Package trends and roadmap update Advanced technology update Fine pitch & Low cost flip chip (fccube ) Wafer level package (ewlb) Silicon level integration (TSV) Summary
25 Summary 2D, 2.5D and 3D structures with Flip Chip, Fan-out Wafer level and TSV structures fill the gaps from requirements for high performance and compact form factor mobile applications such as Smartphones and Tablets Flip Chip with fccube Cu colum bump with BOL, OSR Mold underfill flip chip is a lower cost, finer pitch flip chip solution Oblong bump and ETS achieve narrower bump pitch, applicable to Mass Reflow and TCB TCB for narrower bump pitch and thiner die thickness still has a process time gap with a cost impact ewlb-pop realizes lower package height and less warpage than flip chip ewlb technology is evolving toward embedded component substrates with 2D, 2.5D and 3D level heterogeneous integration ewlb technology is used in a variety of 2D, 2.5D and 3D structures Provides better electrical performance and less thermal warpage Embedded passive function with IDC and passive components 3D ewlb-pop provides higher I/O in an ultra thin profile As panel size increases, the cost of manufacturing drops significantly with increased throughput TSV Wide I/O memory offers improved mobile computing performance with minimized power consumption Delay of Wide I/O applications caused slow down of the development activities and manufacturing tool investments for TSV Mid-end and Back-end processes TSV ecosystem with Foundry & OSAT partnership offers proven 3D IC solution
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