New Applications for CMP: Solving the Technical and Business Challenges. Robert L. Rhoades, Ph.D. NSTI Conference (Houston, TX) May 5, 2009
|
|
- Dwayne Jackson
- 6 years ago
- Views:
Transcription
1 New Applications for CMP: Solving the Technical and Business Challenges Robert L. Rhoades, Ph.D. NSTI Conference (Houston, TX) May 5, 2009
2 Outline Background and Business Climate for CMP Technical Approach STORM Development CMP Applications and Examples Conclusions 2
3 What is CMP? CMP = Chemical Mechanical Polishing (Planarization) Developed by IBM in late 1980 s. Licensed to and quickly adopted by both Intel and Micron in the early 1990 s Key manufacturing process required to improve device performance and achieve yield advancements No CMP Traditional Device (a) Side View (b) Top View Carrier (head) Slurry Feed Pad Conditioner Carrier (head) 4 Basic CMP Steps Newer Device Platen Wafer W Via Polishing Pad ILD Slurry Feed PMD W Plug Pictures courtesy of Medtronic, Inc. 3
4 CMOS Life Before CMP Topography at ILD levels (some severe) Sloped wall vias generally limited designers to only 2 or 3 levels of metal Even for fabs that adopted tungsten plugs and SOG, stacked plugs were generally not allowed 4
5 CMOS Life After CMP Topography under control CMP enabled multiple levels of metal Stacked plugs no longer an issue Shallow trench isolation widely adopted Drove several generations of shrinks and more complicated stacks However this technology also started to run out of steam for the most advanced CMOS devices AMD K6 microprocessor (circa 1996) 5
6 CMOS Life with Cu CMP IBM PC603 microprocessor (circa 1998) Dual damascene process integration for patterning Cu lines and vias Primary process issues: Robust clear, defect density, dishing, erosion Fastest growing CMP application for past few years, but still smaller than oxide and tungsten overall 6
7 Interconnects at Intel Interconnect Technology CMP Evolution 1000 nm Two Our Al Expertise, Metal layers, BPSG 350 nm Four Al metal layers, W polish, PSG 500 nm ILD planarization, W plugs w etch back 180 nm STI, 6 Al Metal layers 250 nm STI, Five Al metal layers, SiOF Process, Application, Equipment, & Slurry Evolve, but not as much on Pads Source: Courtesy of Ken Cadien Former Intel fellow 130 nm 3-6 Cu Layers, PMD, W, STI 65 nm 4-11 Cu Layers PMD, W, STI, OSG 90 nm 3-9 Cu Layers, PMD, W, STI OrganoSilicate Glass (OSG) CMP Applications Oxide Polish Pre-Metal Dielectric Interlevel Dielectric STI Polish Poly Polish Tungsten Polish Copper Polish Barrier Polish High k Gate 7
8 Driving Forces Today Since 2005, consumer products have become primary industry driver. Source: 2007 Industry Strategy Symposium Hans Stork, CTO, Texas Instruments Short product life cycles. Consumers demand More for Less. Consumers demand More in Less Space. Source: 2007 Industry Strategy Symposium Steve Newberry, CEO, Lam Research Corporation Contributing factors for Moore s Law device shrinks, multi-level stacks & larger wafers. Result = Fierce Competition + Control Unit Costs + Develop Technology Fast + Ramp Volume Quickly 8
9 Competitive Advantage Revenue Loss from Being Late to Market Acceleration with CMP Outsourcing: Scenario 1: First time CMP implementation Customer Internal Technology Integration Project: Equipment Purchase & Delivery Design, Integrate, Optimize & Quality CMP Implementation with Entrepix: Optimize & Qualify Ramp Customer Generating Revenue Ramp Strategic Factors in the IC Industry, FSA Forum, June 05 Dr. Handel Jones, Chairman & CEO IBS, Inc. Project Phases Scenario 2: CMP capacity expansion Customer Internal Capacity Expansion Project: Equipment Purchase & Delivery Qualify Ramp Customer Gen. Rev. CMP Capacity Expansion with Entrepix: Qualify Ramp Customer Generating Revenue Scenario 3: CMP burst or flex capacity absorption Customer Internal Capacity Expansion Project: Equipment Purchase & Delivery Qualify Ramp Customer Gen. Rev. CMP Capacity Expansion by IDM already qualified at Entrepix: Ramp Customer Generating Revenue Scenario 4: CMP technology improvement or cost reduction Customer Internal Capacity Expansion Project: Develop, Optimize & Qualify Ramp Customer Generating Revenue CMP Capacity Expansion with Entrepix: Qualify Ramp Customer Generating Revenue TIME 9
10 Business Realities Time IS Money Labor cost + cycles of learning + opportunity cost Competition in most markets is fierce Quality & reliability can not be compromised Each process module must be efficient 10
11 Business Response Minimize Manufacturing Costs Benchmarking Yield Enhancement Optimize Unit Processes Focus on Efficiencies Preserve Capital Extend Equipment Life Keep Depreciated Fabs R&D Consortia Install Less Overcapacity Delay Capital Expenditures Accelerate Development While Reducing Costs Reduce Cycles of Learning Extend Proven Technologies Lower % of Engineering Wafer Starts Leverage Outside Expertise 11
12 Comprehensive CMP Solution #1 Accelerate Time to Revenue #2 Reduce Cost and Risk 12
13 Applications for CMP Continue to Expand Numerous complex puzzles Qty Qty Qty 5 CMOS CMOS CMOS New Apps Substrate/Epi Glass (oxide) Glass (oxide) Glass (oxide) Doped Oxides GaAs Tungsten Tungsten Tungsten Nitrides GaN Copper Copper NiFe & NiFeCo InP Shallow Trench Shallow Trench Noble Metals CdTe & HgCdTe Polysilicon Polysilicon Al & Stainless Ge and SiGe Low k Polymers SiC Cap Ultra Low k Ultra Thin Wafers Diamond & DLC Metal Gates Direct Wafer Bond Si & Reclaim Gate Insulators Through Si Vias SOI High k Dielectrics 3-D Packaging Quartz Ir & Pt Electrodes MEMS Titanium Magnetics Nanodevices Integrated Optics Each application of CMP requires an optimized process that meets both performance and cost targets 13
14 CMP Metrics Five key metrics for a CMP process Removal Rate and Uniformity Defectivity Planarization (step height, dishing/erosion, surface roughness, etc.) Process Stability (consistent performance from wafer-to-wafer) Cost per Wafer 14
15 CMP Development CMP Development Sequence Generate Test Wafers Consumables Screening Process DOE's Optimize Uniformity Optimize Planarity Optimize Defectivity Repeatability (multiple runs) Stability (marathon) Release for Device Qualification Zoom in on CMP process development Screening Tests Assumes fundamentals of pad/slurry research are already done by suppliers Test wafer availability and quality often impact timeline, validity of results, etc. Optimization Initial process DOE s generally focus on removal rate and gross surface quality Optimization stages can be interchanged or executed in parallel Repeatability Planarity can mean step height, dishing, erosion, roughness, etc. depending on the material and intended application Marathon Failure at any stage usually means backing up at least one stage to try again 15
16 STORM STORM Screening Tests Optimization Repeatability A proven approach to successfully developing new CMP processes Marathon 16
17 Intro to CMOS Example Project launched to develop a planarized integration for an existing facility running mostly 0.5um and larger devices which did not require CMP. Integration included 2 levels of oxide CMP (PMD and ILD) and 2 levels of tungsten CMP (contact and via1). Initial estimate was roughly 24 months to purchase, install, and qualify CMP equipment plus develop the integration and be ready for production ramp. By leveraging an outsource CMP provider, integration work was started almost immediately and executed in parallel with the equipment lead time. 17
18 Timeline Comparison Key aspects of predicted time savings: Development could begin as soon as test wafers were ready. Equipment purchase, lead time, and installation in parallel. Faster cycles of learning, fewer wafers, lower cost compared to internal. Project Phases Initial Project Timeline for Tool Purchase and Internal Development Production Ramp Qualification Development Install Equip. Purchase Timeframe Acceleration = 12+ months Adjusted Project Timeline with CMP Outsource through Entrepix: Production Ramp Volume Production Revenue Enabled Qualification Development Install Equip. Purchase 3 mos 6 mos 9 mos 12 mos 15 mos 18 mos 21 mos 24 mos 27 mos 30 mos Time 18
19 Timeline Detail Detailed Timeline for CMP Process Module Development Patt. Wafers Blanket Wfrs CMP Lab Days Week #1 Week #2 Week #3 Week #4 Week #5 Week #6 Week #7 Week #8 Week #9 Week #10 Week #11 Week #12 Week #13 Week #14 Task or Milestone Details Phase 1: PMD Planarization Duration ~6-8 wks X Generate test wafers BPSG X CMP process - Initial characterization X Polar evaluation of results X PMD 2nd round optimization X Week #15 Week #16 Week #17 Week #18 Week #19 Week #20 Week #21 Week #22 Week #23 Week #24 Week #25 Week #26 Week #27 Week #28 Week #29 Week #30 Week #31 Week #32 Week #33 Week #34 Week #35 Week #36 Week #37 Week #38 Week #39 Week #40 Week #41 Week #42 Phase 2: Tungsten Contacts Duration ~8 wks X Mask layout and photo optimization X Generate test wafers 3rd party tungsten CVD X CMP process - Initial characterization Incl. SEM X-sections X Polar evaluation of results X Contact 2nd round optimization X Phase 3: ILD1 Planarization Duration ~6 wks X Generate test wafers X CMP process - Initial characterization X Polar evaluation of results X ILD 2nd round optimization X Phase 4: Tungsten Vias Duration ~6 wks X Mask layout and photo optimization X Generate test wafers 3rd party tungsten CVD X CMP process - Initial characterization X Polar evaluation of results X Via 2nd round optimization X Prototype Run (Begin Qual Lots) Duration 4-6 wks X Mask layout and photo optimization X Verification of entire process flow X Evaluation of prototype devices In-line and EOL (ongoing) Polish processes developed: 4 (PMD, W Contact, ILD, W Via1) Total patterned wafers: < 125 Total blanket test wafers: < 200 Total CMP lab shifts: < 12 19
20 Issues Resolved As might be expected, a few issues were encountered during the project. Examples are given below and further detail is provided in a few cases. Issue Composition and thickness of ILD dielectric layer Alignment marks (inconsistent contrast on wafers with CMP) Pattern density effects Ti/TiN liner and CVD W deposition thicknesses Poor contact fill (seen on first contact lot) High NMOS leakage and poor p- field inversion How Resolved Technical inputs from Entrepix with confirmation on 1 st engineering lot Technical dialogue between Entrepix and customer engineering team Verbal description of effects confirmed with data from test structures adjustments made in design rules Starting point suggestions followed by optimization on 1 st and 2 nd engineering lots Suggestions from Entrepix and Novellus helped solve issue in one cycle of learning (Traced to insufficient strip after contact etch) Changed PMD dielectric composition from TEOS to PSG or BPSG 20
21 Issue #1 High Rc Hollow contact Improved contact Hollow contacts with high resistance on first lot. Initial brainstorming between customer and outsource provider led to short list of likely causes. 4485A W-PLUG 3.JPG 4485A NOTCH A1.JPG Resolved with one round of optimization. Resolution involved optimizing post etch strip and was confirmed on next product lot. 21
22 Issue #2 - Leakage The first integration lot showed unexpectedly high NMOS leakage and p-field inversion issues. Technical brainstorming identified trapped charge in TEOS layer as a possible cause of the observed issue. NMOS leakage by PMD oxide Result BPSG PSG TEOS PMD glass composition P-field inversion by PMD oxide TEOS BPSG Normal Quantile BPSG 40 Split lot data confirms that changing to either BPSG or PSG for pre-metal dielectric resolves both issues. Result BPSG PSG TEOS TEOS PMD glass composition Normal Quantile 22
23 CMOS Summary By leveraging the capabilities of an outsource CMP provider, the project timeline for developing a 0.35 um integration in a fab was accelerated by roughly one year. Acceleration was driven by two primary factors. First, the team did not have to wait on internal CMP equipment to be purchased and installed, thus avoiding 6-9 months of delay. Second, several key cycles of learning were assisted by insights and guidance from the external technical staff. Substantial benefits and time savings realized through effective utilization of CMP outsourcing. 23
24 MEMS over CMOS Key Process Metrics & Constraints Metric Incoming Value Post-CMP Target Actual Oxide film thickness 6.5 um 3.0 um 3.02 um Step Height 2.8 um < 0.4 um 0.2 um Removal Rate (um/min) n/a Critical Concerns: Thick oxide layer over CMOS Final topography must be < 0.4um Smooth No sharp corners anywhere Batch to batch consistency Removal Rate (Ang/min) Run # Photos downloaded from web sites, including Sandia National Lab 24
25 Direct Wafer Bonding Example #1: TEOS on X Oxide surfaces tend to bond well when polished to sufficiently low Ra Incoming roughness driven by surface prep of underlying material Sufficient oxide thickness must be deposited to remove at least 2x initial peak-to-valley roughness Material Stack Incoming Ra (A) Post-CMP Ra (A) TEOS on Silicon 7 3 TEOS on SiC 72 7 TEOS on Polysilicon 87 7 TEOS on AlN TEOS on Metal Example #2: Inlaid Cu in TEOS Incoming topography >2.5 ka Goal of <200 A total topography Flat across Feature POST-CMP TOPOGRAPHY ACHIEVED Angstroms 25
26 Conclusions Efficient development of new products is required for any device manufacturer to remain competitive CMP process development involves a sequence of stages (STORM) to efficiently hit technical goals Screening Tests Optimization Repeatability Marathon Proper utilization of CMP outsourcing enables Accelerate timelines Preserve capital Reduce cost and risk 26
27 Contact info Anyone desiring copies of this presentation or any other information please contact: Rob Rhoades Chief Technology Officer Tel: Fax:
28 Appendix Slides providing additional details on STORM 28
29 Screening Tests Early stage development efforts often involve: Immature deposition or growth processes Poorly characterized materials or integrations Technologists who may not be familiar with CMP and how it interacts with other process modules Wide variation in pattern density/feature sizes Wafer sizes smaller than 200 mm Limited availability of test wafer These factors can create huge challenges for CMP 29
30 Rate Screening Removal Rate Metal CMP application Removal Rate (Ang/min) Slurry #1 Slurry #2 Slurry #3 Slurry #4 Slurry #5 Slurry #6 Slurry #7 Slurry #8 Slurry #9 Slurry #10 Pad selection frozen Goal of 4 ka/min Multiple slurry candidates Slurry #8 was chosen for further optimization 30
31 Process DOE s Resources Consumables (Pad and slurry) Blanket film test wafers (all mtrls) Defect monitor wafers (if available) Desired Outputs Rate and uniformity responses to changes in major process variables Identify a process to start further optimization Experimental Plan Inputs Goal is to get preliminary process responses to major variables Preston s Equation (RR=k*P*V) is only an approximation Keep % changes below 25% to keep DOE s as linear as possible Responses to slurry flow and back pressure are not usually linear Successive 2x2 or 3x3 DOE s are generally preferable to massive designs Include defectivity as an output metric if wafers are available 31
32 Optimization Resources Consumables (Pad and slurry) Blanket film wafers (selected mtrls) Defect monitor wafers Patterned wafers for planarization Desired Outputs Single process recipe that meets all required process metrics Data supporting chosen recipe and responses in nearby process space Experimental Plan Inputs Be careful using DOE s single-variable curves often more helpful at this stage Focus on variables with strongest link to parameter being optimized Uniformity: Carrier-to-table speed ratio, back pressure or carrier zones Planarization: Downforce, table speed (keep in mind rate tradeoffs) Defectivity: Downforce, slurry flow, final recipe steps (remember tradeoffs) Number of wafers can quickly get large 32
33 Repeatability Resources Consumables (multiple batches) Blanket film wafers Defect monitor wafers Patterned wafers (optional) Desired Outputs Consistent process performance data using same process settings across multiple consumable sets Experimental Plan Inputs Keep process recipe consistent throughout trials Measure all relevant metrics, not just removal rate Planarization monitor can be low sampling frequency Defect monitor can likewise be low frequency if confident in process 33
34 Marathon Run Resources Consumables Blanket film wafers (selected mtrls) Defect monitor wafers Patterned wafers Desired Outputs Data showing process consistency through pad life (or at least a reasonably large number of wafers) Experimental Plan Inputs Generally want to prove stability for duration of pad life, or at least 250 wafers Different than repeatability focus is on process stability of a single pad set Can be a continuation of the last pad set of the repeatability trial Liberal use of filler wafers can save cost Sample at some low frequency for defects and planarization 34
35 Blanket wafer marathon Oxide CMP Qualification Run Polisher: AMAT Mirra Mesa Pad: IC1010 Slurry: Klebosol Conditioning: In-situ Metrology: 49-point diameter scan, 3mm EE Removal Rate % NU Removal Rate (Ang/min) Uniformity (% 1-sigma) 1000 Start Wafer Number
Balancing Technical and Business Challenges in CMP R&D. Robert L. Rhoades, Ph.D. CAMP Conference (Lake Placid, NY) August 10-12, 2009
Balancing Technical and Business Challenges in CMP R&D Robert L. Rhoades, Ph.D. CAMP Conference (Lake Placid, NY) August 10-12, 2009 Outline Background and Business Climate for CMP STORM Development CMP
More informationCMP Process Development Techniques for New Materials. Robert L. Rhoades, Ph.D. ECS 213 th Meeting (Phoenix, AZ) May 19-21, 2008
CMP Process Development Techniques for New Materials Robert L. Rhoades, Ph.D. ECS 213 th Meeting (Phoenix, AZ) May 19-21, 2008 Outline Background and Industry Drivers Generalized Development Sequence CMP
More informationNew Applications of CMP for Non-Traditional Semiconductor Manufacturing. Robert L. Rhoades, Ph.D. Entrepix, Inc.
New Applications of CMP for Non-Traditional Semiconductor Manufacturing Robert L. Rhoades, Ph.D. Entrepix, Inc. Outline Introduction New Applications of CMP MEMS Non-CMOS Devices New Materials Epitaxial
More informationCMP for Thru-Silicon Vias TSV Overview & Examples March 2009
CMP for Thru-Silicon Vias TSV Overview & Examples March 2009 Packaging Evolution Source: Yole Dev 2007 2 3D Integration Source: Yole Dev 2007 Growth rates for 3D integration Flash continues to drive the
More informationNew CMP Applications And Opportunities for Improvement. Robert L. Rhoades, Ph.D. Presentation for Levitronix Conference May 2011
New CMP Applications And Opportunities for Improvement Robert L. Rhoades, Ph.D. Presentation for Levitronix Conference May 2011 Outline Background TSV s Diamond CMP Opportunities for Improvement Summary
More informationOverview of CMP for TSV Applications. Robert L. Rhoades, Ph.D. Presentation for AVS Joint Meeting June 2013 San Jose, CA
Overview of CMP for TSV Applications Robert L. Rhoades, Ph.D. Presentation for AVS Joint Meeting June 2013 San Jose, CA Outline TSV s and the Role of CMP TSV Pattern and Fill TSV Reveal (non-selective)
More informationNew Applications of Chemical Mechanical Planarization
New Applications of Chemical Mechanical Planarization Robert L. Rhoades, Ph.D. Semiconductor Equipment Spare Parts and Service CMP Foundry AVS Joint Meeting San Jose, CA Feb 19, 2015 Welcome to Entrepix
More informationThe History & Future of
The History & Future of CMP CMPUG July 2008 Karey Holland, Ph.D. kholland@nexplanar.com Ken Cadien, Ph.D. University of Alberta kcadien@ualberta.ca http://www.nexplanar.com http://www.ualberta.ca/ Outline
More informationHardware and Process Solutions to Evolving CMP Needs. - or - CMP Challenges How Can We Polish THAT?
Hardware and Process Solutions to Evolving CMP Needs - or - CMP Challenges How Can We Polish THAT? Robert L. Rhoades (Entrepix) and Paul M. Feeney (Axus Technology) Presented at TechXPOT North - Semicon
More informationNotable Trends in CMP: Past, Present and Future
Notable Trends in CMP: Past, Present and Future Semiconductor International February 15 th, 2007 Pete Singer Editor-in-Chief Levitronix CMP Users Conference 2007 April 1988: Etchback, SOG November 1990:
More informationNonplanar Metallization. Planar Metallization. Professor N Cheung, U.C. Berkeley
Nonplanar Metallization Planar Metallization Passivation Metal 5 (copper) Metal 3 (copper) Interlevel dielectric (ILD) Via (tungsten) Metal 1 (copper) Tungsten Plug to Si Silicon Caps and Plugs oxide oxide
More informationThe ABC s of CMP for DWB and SOI. Robert L. Rhoades, Ph.D. CAMP Conference Presentation August 9, 2010
The ABC s of CMP for DWB and SOI Robert L. Rhoades, Ph.D. CAMP Conference Presentation August 9, 2010 Outline Introduction Direct Wafer Bonding (DWB) Background CMP for DWB Silicon-On-Insulator (SOI) Background
More informationChapter 4 : ULSI Process Integration (0.18 m CMOS Process)
Chapter : ULSI Process Integration (0.8 m CMOS Process) Reference. Semiconductor Manufacturing Technology : Michael Quirk and Julian Serda (00). - (00). Semiconductor Physics and Devices- Basic Principles(/e)
More informationTest Patterns for Chemical Mechanical Polish Characterization
Dobek S: CMP Characterization 15th Annual Microelectronic Engineering Conference, 1997 Test Patterns for Chemical Mechanical Polish Characterization Stanley 3. Dobek Senior Microelectronic Engineering
More informationSemiconductor Manufacturing Technology. IC Fabrication Process Overview
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 00 by Prentice Hall Chapter 9 IC Fabrication Process Overview /4 Objectives After studying the material in this chapter, you
More informationECE321 Electronics I
ECE321 Electronics I Lecture 19: CMOS Fabrication Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 Miller Effect Interconnect
More information200mm Next Generation MEMS Technology update. Florent Ducrot
200mm Next Generation MEMS Technology update Florent Ducrot The Most Exciting Industries on Earth Semiconductor Display Solar 20,000,000x reduction in COST PER TRANSISTOR in 30 years 1 20x reduction in
More informationEE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009
Suggested Reading EE40 Lec 22 IC Fabrication Technology Prof. Nathan Cheung 11/19/2009 300mm Fab Tour http://www-03.ibm.com/technology/manufacturing/technology_tour_300mm_foundry.html Overview of IC Technology
More informationIntegration Issues with Cu CMP
Integration Issues with Cu CMP Copper CMP Integrated Solutions Michael R. Oliver Rodel, Inc. December 3, 2003 Outline Dual Damascene Approach Requirements Impact of Cu Deposition Topography Issues Sensitivity
More informationCMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI
CMOS Technology Flow varies with process types & company N-Well CMOS Twin-Well CMOS STI Start with substrate selection Type: n or p Doping level, resistivity Orientation, 100, or 101, etc Other parameters
More informationA Production-Proven Shallow Trench Isolation (STI) Solution Using Novel CMP Concepts*
A Production-Proven Shallow Trench Isolation (STI) Solution Using Novel CMP Concepts* Raymond R. Jin, Jeffrey David, Bob Abbassi, Tom Osterheld, Fritz Redeker Applied Materials, 3111 Coronado Drive, M/S
More informationLecture #18 Fabrication OUTLINE
Transistors on a Chip Lecture #18 Fabrication OUTLINE IC Fabrication Technology Introduction the task at hand Doping Oxidation Thin-film deposition Lithography Etch Lithography trends Plasma processing
More informationCzochralski Crystal Growth
Czochralski Crystal Growth Crystal Pulling Crystal Ingots Shaping and Polishing 300 mm wafer 1 2 Advantage of larger diameter wafers Wafer area larger Chip area larger 3 4 Large-Diameter Wafer Handling
More informationDevelopment of a New Tungsten Pad Utilizing Outsource CMP Capabilities
Development of a New Tungsten Pad Utilizing Outsource CMP Capabilities by Robert L. Rhoades; Entrepix, Inc., John Bare, Anthony J. Clark, and Ed Atkinson; psiloquest, Inc. Presented to CMP-MIC 2005 Summary
More informationEE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects
EE 330 Lecture 9 IC Fabrication Technology Part II -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects Review from Last Time Etching Dry etch (anisotropic) SiO
More informationIMPACT Seminar. Title: Past, present, and future of CMP Faculty: David Dornfeld Department: Mechanical Engineering University: Berkeley IMPACT
1 Seminar Title: Past, present, and future of Faculty: David Dornfeld Department: Mechanical Engineering University: Berkeley 2 Overview Outline History and Future Development (courtesy of Ken Cadien,
More informationChapter 3 Silicon Device Fabrication Technology
Chapter 3 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world) are manufactured every year. VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale
More informationEvaluation of Copper CMP Process Characterization Wafers
SKW Associates, Inc. Evaluation of Copper CMP Process Characterization Wafers SKW6-3 & SKW6-5 SooKap Hahn Jan 15, 2005 Polish Proposal 1 Planned Polishing: Week of Dec 20 th Customer: SKW Associates Inc.
More informationSlurry Design Evolution. Robert L. Rhoades, Ph.D. CAMP Conference Presentation August 14, 2012
Slurry Design Evolution Robert L. Rhoades, Ph.D. CAMP Conference Presentation August 14, 2012 Outline Introduction to Slurry Design Birth of a Sub-Industry (Early Years) Slurry Evolution and Revolution
More informationEngineered Substrates
Engineered Substrates Engineered Substrates Using the NanoCleave TM Process Francois J. Henley President and CEO Silicon Genesis Corporation San Jose, California SiGen Presentation Outline Engineered Substrates
More informationMotorola PC603R Microprocessor
Construction Analysis Motorola PC603R Microprocessor Report Number: SCA 9709-551 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:
More informationSKW Wafer Product List
SKW Wafer Product List Regularly updated (2.13.2018) SKW Associates, INC. 2920 Scott Blvd, Santa Clara, CA 95054 Tel: 408-919-0094, Fax: 408-919-0097 I. Available Wafers in 200mm and 300mm - Please refer
More informationIC Fabrication Technology Part III Devices in Semiconductor Processes
EE 330 Lecture 10 IC Fabrication Technology Part III Metalization and Interconnects Parasitic Capacitances Back-end Processes Devices in Semiconductor Processes Resistors Diodes Review from Last Lecture
More informationKeeping Your CMP Slurry From Being A Pain in the As-Probed Die Yield. Robert L. Rhoades (Entrepix) Brian Orzechowski and Jeff Wilmer (DivInd, LLC)
Keeping Your CMP Slurry From Being A Pain in the As-Probed Die Yield Robert L. Rhoades (Entrepix) Brian Orzechowski and Jeff Wilmer (DivInd, LLC) Presentation for the Levitronix Conference February 1,
More informationAdvanced STI CMP Solutions for New Device Technologies
Advanced STI CMP Solutions for New Device Technologies Jeffrey David, Benjamin A. Bonner, Thomas H. Osterheld, Raymond R. Jin Applied Materials, 3111 Coronado Drive, M/S 1510, Santa Clara, CA 95054 (408)986-3277
More informationMicrofabrication of Integrated Circuits
Microfabrication of Integrated Circuits OUTLINE History Basic Processes Implant; Oxidation; Photolithography; Masks Layout and Process Flow Device Cross Section Evolution Lecture 38, 12/05/05 Reading This
More informationIntegrated Circuit Engineering Corporation. DRAMs
DRAMs As generally known, the focus of technology in this product category continues to be complex vertical polysilicon structures to reduce cell area. This not only pushes the limits of deposition and
More informationComplementary Metal Oxide Semiconductor (CMOS)
Technische Universität Graz Institute of Solid State Physics Complementary Metal Oxide Semiconductor (CMOS) Franssila: Chapters 26,28 Technische Universität Graz Institute of Solid State Physics Complementary
More information2009 Market Slurries and Particles in CMP & a Bit Beyond
2009 Market Slurries and Particles in CMP & a Bit Beyond NCCAVS CMPUG Semicon W Meeting Karey Holland, Ph.D. July 14, 2009 Techcet Group, LLC. KHolland@Techcet.com www.techcet.com Slurries & Particles
More informationPROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS
Contents: VI Sem ECE 06EC63: Analog and Mixed Mode VLSI Design PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS 1. Introduction 2. CMOS Fabrication 3. Simplified View of Fabrication Process 3.1 Alternative
More informationEE BACKEND TECHNOLOGY - Chapter 11. Introduction
1 EE 212 FALL 1999-00 BACKEND TECHNOLOGY - Chapter 11 Introduction Backend technology: fabrication of interconnects and the dielectrics that electrically and physically separate them. Aluminum N+ Early
More informationLecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther
EECS 40 Spring 2003 Lecture 19 Microfabrication 4/1/03 Prof. ndy Neureuther How are Integrated Circuits made? Silicon wafers Oxide formation by growth or deposition Other films Pattern transfer by lithography
More informationLect. 2: Basics of Si Technology
Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from fractions of nanometer to several micro-meters
More informationPolishing of Bulk Micro-Machined Substrates by Fixed Abrasive Pads for Smoothing and Planarization of MEMS Structures
PAPER D Polishing of Bulk Micro-Machined Substrates by Fixed Abrasive Pads for Smoothing and Planarization of MEMS Structures In: Proceedings of IEEE/SEMI Advanced Semiconductors Manufacturing Conference
More informationOverview of Dual Damascene Cu/Low-k Interconnect
ERC Retreat Stanford: New Chemistries & Tools for scco 2 Processing of Thin Films Overview of Dual Damascene Cu/Low-k Interconnect P. Josh Wolf 1,4 - Program Manager, Interconnect Div. josh.wolf@sematech.org
More informationComplexity of IC Metallization. Early 21 st Century IC Technology
EECS 42 Introduction to Digital Electronics Lecture # 25 Microfabrication Handout of This Lecture. Today: how are Integrated Circuits made? Silicon wafers Oxide formation by growth or deposition Other
More informationEECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 9/13/2007 Fabrication Technology Lecture 1 Silicon Device Fabrication Technology Over 10 15 transistors (or 100,000 for every person in the world)
More informationReduced Cost of Ownership Oxide CMP Process using 300mm Consumables for 200mm processing
Reduced Cost of Ownership Oxide CMP Process using 300mm Consumables for 200mm processing Christopher Eric Brannon, Jimmy Carter (TI DMOS5 CMP Manufacturing Engineering) Texas Instruments, Semiconductor
More informationChapter 5 Thermal Processes
Chapter 5 Thermal Processes 1 Topics Introduction Hardware Oxidation Diffusion Annealing Post-Implantation Alloying Reflow High Temp CVD Epi Poly Silicon Nitride RTP RTA RTP Future Trends 2 Definition
More informationMark T. Bohr Intel Senior Fellow, Technology and Manufacturing Group Director, Process Architecture and Integration INTEL CORPORATION
Mark T. Bohr Intel Senior Fellow, Technology and Manufacturing Group Director, Process Architecture and Integration INTEL CORPORATION Patents» 6762464, N-P butting connections on SOI substrates, 7/13/2004.»
More informationECE520 VLSI Design. Lecture 7: CMOS Manufacturing Process. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 7: CMOS Manufacturing Process Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last
More informationRockwell R RF to IF Down Converter
Construction Analysis Rockwell R6732-13 RF to IF Down Converter Report Number: SCA 9709-552 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780
More informationXilinx XC4036EX FPGA
Construction Analysis Xilinx XC4036EX FPGA Report Number: SCA 9706-544 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax: 602-948-1925
More informationReview of CMOS Processing Technology
- Scaling and Integration Moore s Law Unit processes Thin Film Deposition Etching Ion Implantation Photolithography Chemical Mechanical Polishing 1. Thin Film Deposition Layer of materials ranging from
More informationEE 330 Lecture 9. IC Fabrication Technology Part 2
EE 330 Lecture 9 IC Fabrication Technology Part 2 Quiz 8 A 2m silicon crystal is cut into wafers using a wire saw. If the wire diameter is 220um and the wafer thickness is 350um, how many wafers will this
More informationMicrostructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley
Microstructure of Electronic Materials Amorphous materials Single-Crystal Material 1 The Si Atom The Si Crystal diamond structure High-performance semiconductor devices require defect-free crystals 2 Crystallographic
More informationCu/low κ. Voids, Pits, and Copper
Cu/low κ S P E C I A L s, Pits, and Copper Judy B Shaw, Richard L. Guldi, Jeffrey Ritchison, Texas Instruments Incorporated Steve Oestreich, Kara Davis, Robert Fiordalice, KLA-Tencor Corporation As circuit
More informationDepartment of Electrical Engineering. Jungli, Taiwan
Chapter 3 Fabrication of CMOS Integrated Circuits Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Background Outline The CMOS Process Flow Design Rules Latchup
More informationEE 434 Lecture 9. IC Fabrication Technology
EE 434 Lecture 9 IC Fabrication Technology Quiz 7 The layout of a film resistor with electrodes A and B is shown. If the sheet resistance of the film is 40 /, determine the resistance between nodes A and
More informationCleaning Trends for Advanced Nodes. April 9, 2018 Scotten W. Jones President IC Knowledge LLC
Cleaning Trends for Advanced Nodes April 9, 2018 Scotten W. Jones President IC Knowledge LLC sjones@icknowledge.com Outline DRAM Logic NAND Conclusion 2 DRAM Nodes 2011 2012 2013 2014 2015 2016 2017 2018
More information4th Annual SFR Workshop, Nov. 14, 2001
4th Annual SFR Workshop, Nov. 14, 2001 8:30 9:00 Research and Educational Objectives / Spanos 9:00 9:45 CMP / Doyle, Dornfeld, Talbot, Spanos 9:45 10:30 Plasma & Diffusion / Graves, Lieberman, Cheung,
More informationChapter 2 Manufacturing Process
Digital Integrated Circuits A Design Perspective Chapter 2 Manufacturing Process 1 CMOS Process 2 CMOS Process (n-well) Both NMOS and PMOS must be built in the same silicon material. PMOS in n-well NMOS
More informationLecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1
Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1 LECTURE 030 INTEGRATED CIRCUIT TECHNOLOGY - I (References [7,8]) Objective The objective of this presentation is: 1.) Illustrate integrated
More informationCopper Interconnect Technology
Tapan Gupta Copper Interconnect Technology i Springer Contents 1 Introduction 1 1.1 Trends and Challenges 2 1.2 Physical Limits and Search for New Materials 5 1.3 Challenges 6 1.4 Choice of Materials 7
More informationExam 1 Friday Sept 22
Exam 1 Friday Sept 22 Students may bring 1 page of notes Next weeks HW assignment due on Wed Sept 20 at beginning of class No 5:00 p.m extension so solutions can be posted Those with special accommodation
More informationCMOS Processing Technology
CHAPTER 2 CMOS Processing Technology Outline 2 1. CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues CMOS Technologies 3 n-well
More informationA Novel Retaining Ring in Advanced Polishing Head Design for Significantly Improved CMP Performance
A Novel Retaining Ring in Advanced Polishing Head Design for Significantly Improved CMP Performance Thomas H. Osterheld, Steve Zuniga, Sidney Huey, Peter McKeever, Chad Garretson, Ben Bonner, Doyle Bennett,
More informationCMP challenges in sub-14nm FinFET and RMG technologies
CMP challenges in sub-14nm FinFET and RMG technologies Tae Hoon Lee*, Hong Jin Kim, Venugopal Govindarajulu, Gerett Yocum & Jason Mazzotti Advanced Module Engineering NCCAVS CMPUG Spring Meeting 2016 Contents
More informationAltera EPM7128SQC EPLD
Construction Analysis Altera EPM7128SQC160-15 EPLD Report Number: SCA 9712-569 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:
More informationThin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high
Thin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high vacuum ~10-7 torr Removes residual gases eg oxygen from
More informationEE C245 ME C218 Introduction to MEMS Design
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 10: Surface
More informationMEMS Devices. Fraunhofer Institute for Silicon Technology ISIT. Itzehoe, Germa. any
Examples of CMP Processess for the Manufacturing of MEMS Devices Gerfried Zwicke er Fraunhofer Institute for Silicon Technology ISIT Itzehoe, Germa any gerfried.zwicker@isit.fraunhofer.de Contents MEMS
More informationFeature-level Compensation & Control. CMP September 15, 2005 A UC Discovery Project
Feature-level Compensation & Control CMP September 15, 2005 A UC Discovery Project Chemical Mechanical Planarization - Faculty Team Mechanical Phenomena David A. Dornfeld Mechanical Engineering UCB Fiona
More informationTSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development
TSV Processing and Wafer Stacking Kathy Cook and Maggie Zoberbier, 3D Business Development Outline Why 3D Integration? TSV Process Variations Lithography Process Results Stacking Technology Wafer Bonding
More informationVLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents UNIT I INTRODUCTION: Introduction to IC Technology MOS, PMOS, NMOS, CMOS & BiCMOS technologies. BASIC ELECTRICAL PROPERTIES : Basic Electrical
More informationCMOS Processing Technology
CHAPTER 2 CMOS Processing Technology Outline 2 1. CMOS Technologies 2. Layout Design Rules 3. CMOS Process Enhancements 4. Technology-related CAD Issues 5. Manufacturing Issues CMOS Technologies 3 n-well
More informationSUMMiT V Five Level Surface Micromachining Technology Design Manual
SUMMiT V Five Level Surface Micromachining Technology Design Manual Version 1.3 09/22/2005 MEMS Devices and Reliability Physics Department Microelectronics Development Laboratory Sandia National Laboratories
More informationManufacturing Process
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Manufacturing Process July 30, 2002 1 CMOS Process 2 A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten
More information9/4/2008 GMU, ECE 680 Physical VLSI Design
ECE680: Physical VLSI Design Chapter II CMOS Manufacturing Process 1 Dual-Well Trench-Isolated CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 p-well poly n-well SiO 2 n+ p-epi p+ p+ 2 Schematic Layout
More informationRegents of the University of California
Topography Issues Degradation of lithographic resolution PR step coverage, streaking Thickness differences pose problems for reduction steppers Direction of Spin PR PR PR Stringers Problematic when using
More informationMotorola MC68360EM25VC Communication Controller
Construction Analysis EM25VC Communication Controller Report Number: SCA 9711-562 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax:
More informationXilinx XC4036XL-1C FPGA
Construction Analysis Xilinx XC4036XL-1C FPGA Report Number: SCA 9709-553 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9780 Fax: 602-515-9781
More informationCMP Scratches; Their Detection and Analysis on Root Causes
6 th LEVITRONIX CMP and Ultrapure Conference The Westin Park Central, Dallas, Texas May 11-12, 2011 CMP Scratches; Their Detection and Analysis on Root Causes Jin-Goo Park May 11, 2011 Department of Materials
More informationNKK NR4645LQF Bit RISC Microprocessor
Construction Analysis NKK NR4645LQF-133 64-Bit RISC Microprocessor Report Number: SCA 9707-547 Global Semiconductor Industry the Serving Since 1964 17350 N. Hartford Drive Scottsdale, AZ 85255 Phone: 602-515-9870
More informationCMP Process Development for the Via- Middle 3D TSV Applications at 28nm Technology Node
CMP Process Development for the Via- Middle 3D TSV Applications at 28nm Technology Node UMC/ ATD_AM / CMP Department T. C. Tsai, W. C. Tsao, Welch Lin, C. L. Hsu, C. L. Lin, C. M. Hsu, J. F. Lin, C. C.
More informationEEC 118 Lecture #5: MOS Fabrication. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #5: MOS Fabrication Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 3 this week, report due next week HW 3 due this Friday at 4
More informationIntegrated Circuit Engineering Corporation EPROM
EPROM There was lots of discussion and many technical papers covering the promises of EPROM (typically Flash) at the IEDM conference last December, but here as in the other memory areas, not much in the
More informationNANOMANUFACTURING TECHNOLOGY
NANOMANUFACTURING TECHNOLOGY NAS/SSSC Spring Meeting April 2, 2009 Moore's Law and Transistor Scaling Bits/Chip 1T 45nm 90nm 1G 0.25um 1um 1M 1K 1975 1985 1995 2005 2015 DSP AA Battery Hours 100 50 0 0
More informationINTEGRATED-CIRCUIT TECHNOLOGY
INTEGRATED-CIRCUIT TECHNOLOGY 0. Silicon crystal growth and wafer preparation 1. Processing Steps 1.1. Photolitography 1.2. Oxidation 1.3. Layer Deposition 1.4. Etching 1.5. Diffusion 1.6 Backend: assembly,
More informationNew Materials as an enabler for Advanced Chip Manufacturing
New Materials as an enabler for Advanced Chip Manufacturing Drive Innovation, Deliver Excellence ASM International Analyst and Investor Technology Seminar Semicon West July 10 2013 Outline New Materials:
More informationRegents of the University of California 1
Electroplating: Metal MEMS Nickel Surface-Micromachining Process Flow Photoresist Wafer Release Etchant Use electroplating to obtain metal μstructures When thick: call it LIGA Pros: fast low temp deposition,
More informationLinx Consulting Inc. CMP TECHNOLOGIES and MARKETS to the 5 nm NODE. See Beyond the Horizon. Eighth Edition
See Beyond the Horizon Linx Consulting Inc. Pu b l i s h e d 3 Q 2 0 1 8 CMP TECHNOLOGIES and MARKETS to the 5 nm NODE Eighth Edition Uncertainty around true materials requirements is a huge risk for leading
More informationPROVIDER OF BREAKTHROUGH TECHNOLOGY, PROCESSES AND EQUIPMENT FOR ENGINEERED SUBSTRATE SOLUTIONS. ...
SEMICONDUCTOR SOLAR DISPLAY OPTOELECTRONIC PROVIDER OF BREAKTHROUGH TECHNOLOGY, PROCESSES AND EQUIPMENT FOR ENGINEERED SUBSTRATE SOLUTIONS........... A Look at Silicon Genesis 1997 Founded as a fabless
More informationn region. But, it is a bit difficult
VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 31 Problems in Aluminium Metal Contacts So, we have been discussing about the
More informationIntel Pentium Processor W/MMX
Construction Analysis Intel Pentium Processor W/MMX Report Number: SCA 9706-540 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax:
More informationLattice isplsi1032e CPLD
Construction Analysis Lattice isplsi1032e CPLD Report Number: SCA 9612-522 Global Semiconductor Industry the Serving Since 1964 15022 N. 75th Street Scottsdale, AZ 85260-2476 Phone: 602-998-9780 Fax: 602-948-1925
More informationAdvances in Process Overlay - ATHENA Alignment System Performance on Critical Process Layers
Advances in Process Overlay - ATHENA Alignment System Performance on Critical Process Layers David Laidler 1, Henry Megens 2, Sanjay Lalbahadoersing 2, Richard van Haren 2, Frank Bornebroek 2 1 IMEC, Kapeldreef
More informationResearch Activities on Defect Improvement of CMP Process in 1x nm Foundry Device
Research Activities on Defect Improvement of CMP Process in 1x nm Foundry Device 1JI CHUL YANG, 2Hong Jin Kim, 2Venu. Govindarajulu,1Dinesh Koli and 2Jason Mazzotti Jichul.yang@globalfoundries.com 1 CMP,
More informationInterconnects OUTLINE
Interconnects 1 Interconnects OUTLINE 1. Overview of Metallization 2. Introduction to Deposition Methods 3. Interconnect Technology 4. Contact Technology 5. Refractory Metals and their Silicides Reading:
More information2006 UPDATE METROLOGY
INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS METROLOGY THE ITRS DEVED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS
More information