Basic Opamp Design and Compensation. Transistor Model Summary

Transcription

1 Basic Opamp Design and Compensation David Johns and Ken Martin slide of 37 General Constants Transistor charge Boltzman constant Transistor Model Summary Intrinsic silicon carrier concentration ( K) Relative permittivity of oxide Relative permittivity of silicon MOS Transistor Parameters Electron mobility (typical) Hole mobility (typical) Oxide thickness (typical) q C k JK n i. 0 6 carriers/m 3 K ox 3.9 K s.8 µ n 0.05 m V s µ p 0.0 m V s t ox 0.0 µm slide of 37

2 Transistor Model Summary Gate capacitance per unit area C ox Device parameters (typ), Threshold voltages (typical) V tn 0.8 V, Threshold voltage adjustment Body effect parameter (typical) Fermi potential difference (typical) φ F Effective Gate-Source Voltage, V eff Effective gate-source voltage K ox ε o pf/ ( µm) t ox µ n C ox 90 µa/v µ p C ox 30 µa/v V tp 0.9 V V tn V tn-0 + γ( V SB + φ F φ F ) γ 0.5 V 0.35 V V eff V GS V tn slide 3 of 37 I D Triode and Active Regions W V µ n C ox ---- ( V L GS V tn )V DS DS I D I D V GS constant µ n C ox W ---- ( L V GS V tn ) I D W µ n C ox ---- ( V L GS V tn )V DS Triode Region Active Region Cutoff Region: V GS V GS Cutoff Region V tn V DS,sat V DS,sat Triode Region: > V tn, V DS V eff Active Region: V GS > V tn, V DS V eff < V DS V eff slide 4 of 37

3 MOS Triode Equations Region of operation V GS > V tn, V DS V eff Drain current I D µ n C W ox ---- ( V L GS V tn )V DS.7 V DS typical term is due to body effect along channel Small-Signal Model in Triode Region ( for V DS << V eff ) Vg Vs Cgs Csb rds Cgd Cdb Vd r ds W µ n C ox ---- Veff L slide 5 of 37 MOS Active (or Pinch-Off) Equations Region of operation V GS > V tn, V DS V eff Drain current I µ n C ox D W ---- ( VGS V L tn ) [ + λ( V DS V eff )] Output impedance constant λ L V DG + V tn term is due to built-in junction potential Effective gate-source voltage (ignoring output impedance) V eff V GS V tn I D µ n C ox ( W L) slide 6 of 37

4 MOS Active Equations Small-Signal Model (Active Region) C gd v g v d C gs v gs g m v gs g s v s r ds C db C sb v s slide 7 of 37 Transconductance Transconductance MOS Active Equations g m g m W µ n C ox ---- Veff L µ n C ox ( W L)I D Transconductance g m I D V eff Body effect transconductance g s Body effect transconductance (typical) g s Output impedance Output impedance r ds λi D α L γg m V SB + φ F 0.g m r ds ---- V where I DG + V tn α D V m slide 8 of 37

5 Two-Stage CMOS Opamp Useful for describing many opamp design concepts Still used for low voltage applications C cmp V in A A V out Differential input stage Second gain stage Output buffer slide 9 of 37 Two-Stage CMOS Opamp 5 Q0 Q 5 Q5 I bias V DD Q6 500 Q4 Q 5 5 Q8 Q Q V in V in+ V out 00 5 Q6 Q5 Q3 R b Q3 Q4 V SS Q7 Q9 Bias circuitry Differential-input Common-source Output first stage second stage buffer all transistor lengths.6 um slide 0 of 37

6 Opamp Gain 3rd stage NOT included if driving capacitive loads Typical gains of for each of stage and First Stage Differential to single-ended g m Second Stage Common-source gain A v g m ( r ds r ds4 ) W µ p C ox ---- I L D A v g m7 ( r ds6 r ds7 ) µ p C W ox ---- L I bias () () (3) slide of 37 Opamp Gain Third Stage Source follower Typical gain slightly less than (say 0.9) Note g ds r ds and G L R L A v G L + g m8 + g s8 + g ds8 + g ds9 g s is body-effect conductance and equals zero if source tied to substrate is the load conductance at output G L g m8 (4) slide of 37

7 V bias Q5 Frequency Response v in+ v in Q Q v v A 3 50 Q3 50 Q4 i g m v in A A3 v out C eq ( + A ) slide 3 of 37 Frequency Response dominates at all freq except unity-gain freq Ignore Q6 for now (used for lead compensation) Miller effect results in ( C eq ( + A )) A At midband freq A g m Z out g m ( s A ) Overall gain (assuming A 3 ) A v () s A A g m ( s ) resulting in a unity-gain frequency of a g m (5) (6) (7) (8) slide 4 of 37

8 First-order model 0log( A A ) Gain (db) Freq Response -0 db/decade a g m 0 Freq a (log) ω p Phase (degrees) 0 ω Freq ta (log) ω p slide 5 of 37 Slew Rate Max rate output changes when input signal large All Q5 bias current goes into Q or Q I D SR dv out dt max I CC max I D5 I D is nominal bias current of input transistors (9) Using W g m a and g m µ p C ox ---- L I D slide 6 of 37

9 SR Slew Rate I D a V eff a µ p C ox ( W L) I D (0) where V eff I D µ p C ox ( W L) Normally, little control over a for a given power diss Increase slew-rate by increasing Veff This is one of main reasons for using p-channel input stage higher slew-rate slide 7 of 37 Systematic Offset Voltage To ensure inherent offset voltage does not exist, design should satisfy ( W L) 7 ( W L) ( W L) ( W L) 5 Ensures nominal current through Q7 equals Q6 Found by noting I D5 I D3 I D4 () () and V GS7 V DS3 V GS4 (3) then setting I D7 I D6 slide 8 of 37

10 N-Channel or P-Channel Input Stage Can also build complement opamp with an n-channel input diff pair and second-stage p-channel stage P-channel Advantages V eff Higher slew-rate For fixed bias current, is larger (assuming similar widths used for max gain) Higher unity-gain freq higher transconductance of second stage which is proportional to unity-gain freq Lower /f noise holes less likely to be trapped p-channel transistors have lower /f noise N-channel Advantage Lower thermal noise thermal noise is lowered by high transconductance of first stage slide 9 of 37 Opamp Compensation β V in ( s) As ( ) V out ( s) Feedback circuit β assumed to be freq independent R β R R + R β C C C + C R As ( ) V out C As () V out slide 0 of 37

11 Model ω p General Opamp Compensation As ( ) by As ( ) first dominant-pole frequency pole frequency modelling higher-freq poles. found from simulation frequency with 35 phase shift ( 90 due to ω p and another 45 due to higher-frequency poles and zeros) Closed loop gain given by A ( + s ω p )( + s ) A CL ( s) As ( ) βa( s) (4) (5) slide of 37 General Opamp Compensation A CL ( s) A CL s( ω p + ) s βa 0 ( + βa 0 )( ω p ) (6) wherea CL0 A 0 ( + βa 0 ) β Compare to a general second-order equation H ( s) Kω s ω s + ω0 Q % overshoot 00e K s s ω 0 Q π Q ω 0 (7) (8) slide of 37

12 General Opamp Compensation Equating equations above results in ω 0 ( + βa 0 )( ω p ) βa 0 ω p (9) ( + βa 0 ) ω p βa 0 ω p Q ω p + To find relationship between Q and phase-margin we look at the loop gain, LG() s βa 0 LG( s) βas ( ) ( + s ω p )( + s ) To find a relationship for the loop-gain unity-gain freq LG( j ) (0) () () slide 3 of 37 General Opamp Compensation And rearrange and use approx that» ω p βa 0 ω p (3) so that Q (4) Would also like to relate phase-margin with and Q factor slide 4 of 37

13 Phase-Margin Loop Gain (db) 0log( LG( jω) ) 0 Phase Loop Gain (degrees) 90-0 db/decade a a Freq 0 (log) 80 ω p ω p PM (phase margin) Freq (log) GM (gain margin) slide 5 of 37 PM General Opamp Compensation LGjω ( t ) ( 80 ) 90 tan ( ) (5) where ω p adds 90 phase shift If non-dominant poles remains unchanged, independent of β for optimally compensated circuit! PM (Phase margin) tan( 90 PM) Percentage overshoot for a step input Q factor % % % % % (6) slide 6 of 37

14 Compensating the -Stage Opamp V bias Q5 V DD Q6 Vin- Q Q V in+ V out V bias Q6 Cc Q3 Q4 Q7 slide 7 of 37 Compensating the -Stage Opamp v R C v out g m v R g v in C m7 R C Q 6 has V DS6 0 and is hard in the triode region. R C r ds W µ n C ox ---- L V eff6 6 R C Small signal analysis without present, right-half plane zero occurs and worsens phase-margin (7) slide 8 of 37

15 Including Compensating the -Stage Opamp R C (through Q6) places zero at ω z ( g m7 R C ) Zero moved to left-half plane to aid compensation Good practical choice is ω z. (8) (9) satisfied by letting R C g m (30) since g m and ω z ( R C ) if R C» g m7 slide 9 of 37 Design Procedure ) Find with R c 0 for a 55 o phase margin Arbitrarily choose C C 5 pf and set R C 0 Using SPICE, find frequency where a 5 phase shift exists, define gain as A Choose new so becomes unity-gain frequency of the loop gain results in a 55 phase margin. Achieved by setting C C A Might need to iterate on a couple of times using SPICE slide 30 of 37

16 Design Procedure ) Choose R C according to R C (3) Increases by about 0 percent, leaving zero near final Check that gain continues to decrease at frequencies above the new 3) If phase margin not adequate, increase while leaving R C constant slide 3 of 37 Design Procedure 4) Replace R C by a transistor R C r ds W µ n C ox ---- L V eff6 6 SPICE can be used again to fine-tune the device dimensions to optimize phase margin (3) slide 3 of 37

17 Process and Temperature Independence Can show non-dominant pole roughly given by ω p Recall zero given by g m C + C ω z ( g m7 R C ) If R C tracks inverse of g m7 then zero will track ω p R C r ds µ n C ox ( W L) 6 V eff6 g m7 µ n C ox ( W L) 7 V eff7 (33) (34) (35) (36) slide 33 of 37 Process and Temperature Independence Need to ensure V eff6 and temperature variations V bias V eff7 independent of process Q Q6 5 Q 5 First set V eff3 V a 5 Q6 Q3 Q7 V b V eff7 which makes V a V b slide 34 of 37

18 Process and Temperature Independence Since V a I D µ n C ox ( W L) 7 V b I D I D3 ( W L) ( W L) 3 I D µ n C ox ( W L) 3 and gates of Q and Q6 same V eff V eff6 (37) (38) (39) V eff V eff V eff3 µ n C ox ( W L) V eff I D3 I D µ n C ox ( W L) ( W L) ( W L) 3 (40) slide 35 of 37 5 Q0 Stable Transconductance Biasing Q 5 Can bias on-chip g m to a resistor V GS3 V GS5 + I D5 R B (4) I D µ n C ox ( W L) 3 I D5 µ n C ox ( W L) I R D5 B 5 (4) Q4 Q 5 5 But I D3 I D5 and rearrange W L R µ n C ox ( W L) 3 I W L B 5 D3 (43) 00 R B Q5 Q3 5 Recall g m3 µ n C ox ( W L) 3 I D3 ( W L) g m R ( W L) B 5 (44) slide 36 of 37

19 Stable Transconductance Biasing Transconductance of Q 3 determined by geometric ratios only Independent of power-supply voltages, process parameters, temperature, etc. For special case ( W L) 5 4( W L) 3 g m Note that high-temp will decrease mobility and hence increase effective gate-source voltages Roughly 5% increase for 00 degree increase Requires a start-up circuit (might have all 0 currents) R B (45) slide 37 of 37