TechARENA Packaging Exhibitor Session OCT/08, 2014 New WLP-Technology-Fusion Concept Steffen Kröhnert, Director of Technology, NANIUM S.A. V1.

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1 TechARENA Packaging Exhibitor Session OCT/08, 2014 New WLP-Technology-Fusion Concept Steffen Kröhnert, Director of Technology, NANIUM S.A. V1.0 EXT

2 Notification NANIUM is highly committed to IP protection. Therefore, this hand-out of the presentation has been modified from the original presented. Some sections have been covered with blue boxes and Proprietary Information. Not to be disclosed. remark, as it is shown in the examples below. In case of questions, please contact the author and/ or speaker directly. We appologize for any inconvenience caused by that and thank you for your kind understanding. PI NTBD Proprietary Information. Not to be disclosed. Proprietary Information. - Not to be disclosed. Page 2

3 Content Short Company Introduction Fan-Out Wafer-Level Packaging Technology ewlb WLP-Technology-Fusion Concept FIMP Performance Data and Reliability Results Summary & Conclusion Page 3

4 Content Short Company Introduction Fan-Out Wafer-Level Packaging Technology ewlb WLP-Technology-Fusion Concept FIMP Performance Data and Reliability Results Summary & Conclusion Page 4

5 Largest Packaging Foundry in Europe Wafer-Level Packaging Solutions Provider A state-of-the-art facility located in Vila do Conde, Porto, Portugal. 570 employees, thereof 150 Engineers 222,000 ft² clean room ( m²) Current Capacity: - 4,200 wafer/ week 300mm FI & FO WLP - 1,000 kpcs/ Proprietary week BGA Information. Components - 2,700 pcs/ week Not to be SMT disclosed. Modules 24/7 Operation Page 5

6 NANIUM Business Offers Page 6

7 Content Short Company Introduction Fan-Out Wafer-Level Packaging Technology ewlb WLP-Technology-Fusion Concept FIMP Performance Data and Reliability Results Summary & Conclusion Page 7

8 Fan-Out WLP Technology ewlb *) 1) Wafer Reconstitution with Spaces (Pick & Place KGD s on Mold Carrier); 2) Wafer Level Compression Molding; 3) RDL using Thin Film Technology; 4) Wafer Level Pre-formed Bump Drop Process (Solder Ball Attach); 5) Wafer Level Component Thinning, Marking and Singulation Process. *) ewlb is patented by Infineon Technologies AG/ Intel Mobile Communications GmbH Proprietary Information. Not to be disclosed. Page 8

9 Fan-Out WLP Technology ewlb ewlb Component without die (left) and with die (right) 1L-RDL, x 9.25mm² package size Proprietary Information. Not to be disclosed. Fan-In Zone Fan-Out Zone Page 9

10 Content Short Company Introduction Fan-Out Wafer-Level Packaging Technology ewlb WLP-Technology-Fusion Concept FIMP Performance Data and Reliability Results Summary & Conclusion Page 10

11 New WLP-Technology-Fusion Concept Applying Fan-Out WLP/ ewlb Technology to realize Fan-In WLP/ WLCSP Distance between chip edge and package edge is as little as 30-50µm; All solder balls will be placed in the fan-in zone, means on the die only; Fan-out zone is not used for electrical purpose, just mechanical protection. Page 11

12 Fan-In WLP/ WLCSP with Mold Protection FIMP A A Logo Marking Lot Number Logo Marking Lot Number A A a) Overmold 200mm Wafer Fan-In WLP FIMP/eWLCSP Realized in 300mm Fan-Out WLP Logo Marking Lot Number Moldcompound Dies Thermal Release Tape Metal Mold Carrier b) Exposed Die, Very Thin Package Marking, Singulation Solder Ball Drop Thin Film Processing c) BSP-Tape, Thin Package Page 12

13 FIMP/ ewlcsp Cross-Sections 30um sidewall, Backside overmolded 30um sidewall, Backside exposed Si (Pictures taken from recently released publications) Source: ewlcsp Datasheet STATSChipPAC, August 2014 Source: ewlcsp: a new path for WLCSP packaging STATSChipPAC, Chip Scale Review, 09-10/2014 Page 13

14 Independence from Incomming Wafer Technology Scalability to FO-WLP industry standard format (today 300mm round panel); Depending on die size and incomming wafer yield, this can offer significant cost advantage for WLCSP. 9.00X 4.00X 2.25X 1.78X 2.25X mm² mm² 200mm mm² 300mm mm² Page 14

15 Advantages of FIMP - Process Known-Good-Die (KGD) of probed wafer only; - Assembly in highly efficient 300mm recon wafer; - Several wafers with smaller diamater processed at same time in 300mm round recon panel batch processing; - Low temperature processing to avoid performance loss; - Die sidewall protection and optional backside protection by moldcompound (polymer epoxy material); - Improved reliability, higher WLCSP fan-in ballout, slighly larger footprint (min +60um in x and y); - Component test on wafer level without bare die handling; - Safe component handling test (socket insertion), during handling, packing (T&R, Tray) and in SMT-Line; - Optical advantages, better marking (contrast, area gain). Page 15

16 Content Short Company Introduction Fan-Out Wafer-Level Packaging Technology ewlb WLP-Technology-Fusion Concept FIMP Performance Data and Reliability Results Summary & Conclusion Page 16

17 FIMP Performance Data ELECTRICAL Low parasitics due to short connections (Fan-In WLP/ WLCSP), thick Cu-RDL and choice of dielectric material (LTC-PI); Dependent on design and application suitable for 10GHz and beyond. THERMAL Depending on die size and if overmolded die backside or exposed die; Example 5x5mm² die overmolded die backside: around Rth = 30 K/W; Slightly larger package than die Increased area compared to WLCSP. APPLICATION Amplifiers, MCU, PMIC, RFIC; Suitable for automotive and wearable applications. Page 17

18 FIMP Quality Aspects Moldcompound backside and sidewall coverage offers mechanical protection of the die, even when as thin as 30-50um only No bare die handling in component test and SMT line No die chipping or cracking; Compared to standard WLCSP packaging concept, more than 50% increase in die strength; Using of advanced low-temperature cure dielectric materials from Fan-Out WLP/ ewlb process results in improved reliability and performance; Proven reliability level same or better compared to standard Fan-In WLP/ WLCSP. Source: ewlcsp: a new path for WLCSP packaging STATSChipPAC, Chip Scale Review, 09-10/2014 Page 18

19 FIMP Reliability Data COMPONENT LEVEL (FIMP w/ 30um sidewall + BS Overmold) Passed following tests: JEDEC Moisture Sensitivity Level MSL1 (3x 260 degc) Precon + TCT (-55 degc/125 degc) > cycles Precon + uhast (130 degc/85%rh) 192h HTS (150 degc) 1000h THB (85 degc/85%rh/5v) 1000 h BOARD LEVEL (FIMP w/ 30um sidewall + BS Overmold) Passed following tests: TCoB (ICP-9701, -40 degc/125 degc, 1 cy/h) > 500 cycles JEDEC and Customer Specific Drop Test Page 19

20 Content Short Company Introduction Fan-Out Wafer-Level Packaging Technology ewlb WLP-Technology-Fusion Concept FIMP Performance Data and Reliability Results Summary & Conclusion Page 20

21 Summary & Conclusion Advanced packaging solution for classical Fan-In WLP/ WLCSP, applying Fan-Out WLP/ ewlb technology was presented; WLP-Technology-Fusion concept FIMP (Fan-In with Mold Protection) offers significant advantages; Independent of the incoming wafer diameter, 300mm reconstituted mold wafer is built with the Known-Good Dies only; Dies are placed with very small distance (two 200mm wafer or even four 150mm wafer can be WLP processed on one 300mm recon mold wafer) Cost advantage, depending on incoming wafer and die size; Fan-In/ WLCSP dies will have molded backside- and sidewall protection around the die More robust for handling and in operation; FIMP used for advanced CMOS technology nodes w/ Low-k and ULK materials Wafer probe applied to already singulated Si dies, now embedded in the recon wafer, instead of bare die testing. Page 21