IC PACKAGING: APE & APD

Transcription

1 DATASHEET IC PACKAGING: APE & APD HIGH-DENSITY IC PACKAGE DESIGN AND ANALYSIS The rapid emergence and widespread adoption of deep-submicron (DSM) and system-on-a-chip (SoC) integrated circuits are placing a host of new demands on the packaging industry. Increased functionality, faster performance, lower operating voltages, reduced size, and increased siliconization have driven increases in die density and input/outputs boosting package pin count and complexity. This in turn, has created the need for a new breed of high-density, multi-layer, customdesigned packages, such as flip chip, ball-grid-array (BGA) and pin-grid-array (PGA). Figure 1 Increasing Density and Complexity. Today s designs have high pin-count die and package substrates that require any angle routing, arc-radial wirebonding, and complex power and ground structures. These increasing densities also have a significant impact on the overall electrical performance of the package. Today s advanced IC package engineers are constantly pushing the boundaries of substrate technologies, assembly yields, and thermal performance. Consequently, they must now have a clear understanding of signal integrity issues, substrate materials and processes (ceramic, organic, polyimide tape), metalization technologies (thick and thin film, sputtering, conductive foil), and effects on assembly yield (wire bond, wire length and angles, die clearance). At the same time, they re required to design packages that are as inexpensive as possible. Compounding these challenges is the fact that current package-design methodologies are disjointed. At each stage from silicon to package design and analysis, on through manufacturing designers and engineers try to optimize their own segment of the process, oblivious to the impacts their decisions have on other stages. But in leading-edge, high-density designs, this isolationist approach breaks down, retarding cycle time due to missed design specifications. CADENCE IC PACKAGING EXPERT SYSTEMS THE NEXT GENERATION IN DESIGN AUTOMATION This is where Cadence Design Systems steps in. Our new IC packaging expert systems: Advanced Package Engineer (APE) and Advanced Package Designer(APD), are the first products to attack this higher order problem head on. These complementary tool suites institute groundbreaking techniques for integrating electrical analysis and physical design through all phases of development, bridging the gaps between IC design, package design, and package analysis. APD addresses the needs of package designers who lay out high-density, high-performance substrates for IC packages and MCMs. APD provides the designer with a complete end-toend solution that includes data input capability supporting multiple formats, an extensive suite of physical layout tools, and full documentation capability. All tied together by a Constraint Manager that utilizes

2 built-in simulation capability providing dynamic feedback for both electrical and physical DRCs. APE addresses the needs of engineers responsible for package level tradeoff, characterization, analysis, and model extraction. It enables users to make judicious decisions regarding physical interconnect and substrate technology early in the design cycle. The results are improved overall performance of the I/O buffer, reduced signal corruption from crosstalk, delay, simultaneous switching of noise, and other effects and equally vital, less rework caused by errors surfacing downstream in the development flow. Figure 2 High-level Design Flow. The key change from old methodologies and critical to implementing an effective design environment is integration of electrical analysis from the chip through to board design, indicated by the green area of the diagram. ADVANCED PACKAGE DESIGNER COMPREHENSIVE, CONSTRAINT- DRIVEN PHYSICAL LAYOUT A core component of the suite (and already the leading physical design product on the market today) is the Advanced Package Designer application. APD is an environment for rules-based physical design of complex, high-density single- and multi-chip packages and modules. APD includes all the functionality and features you need to design advanced single- and multi-chip packages as well as system-in-package (SiP). It supports all packaging methods, including PGA, BGA, micro-bga, chip scale, as well as both flip chip, wire bond, and stackeddie attach methods. Full online design rule checking supports the complex, unique requirements of all combinations of laminate, ceramic, and deposited substrate technologies. Multiple cavities, complex shapes, and interactive and automatic wire bonding are all supported. The easy-to-use Design Wizards within APD take you through each task, smoothing the transition from mechanical methodologies and first-generation EDA tools to this more comprehensive, interdisciplinary approach. Design Wizards advance early development phases by automating the creation of die, package, and plating-bar footprints. The die and substrate wizards automate definition of these library elements using your choice of text file standard formats (such as D.I.E. and AIF2), or a form-driven user interface, such as the BGA Wizard. SOPHISTICATED SUBSTRATE MODELING AND RULE CHECKING A key advantage of APD is its ability to accurately verify design accuracy against a complete set of physical and electrical design rules (constraints). Physical constraints are mechanical design guidelines to ensure manufacturability. Electrical constraints are delay and distortion specifications for critical nets. APD automatically checks the design against these constraints throughout the design process to ensure the design is meeting manufacturing and electrical specifications and provides immediate feedback to the designer by way of DRC markers. REUSE/REPURPOSING OF DESIGN DATA FOR INCREASED EFFICIENCIES APD can capture both substrate stackup and constraint information in a technology file, which can then be reused for other designs of similar structure, further reducing cycle time on future designs. Technology files can be provided by the substrate suppliers. These techfiles will typically contain 2 critical design rules that help drive a correct design methodology. Multiple techfiles can be used from different suppliers to assure manufacturability at secondary suppliers. WIRE BOND FINGER PATTERNS FOR ALL TYPES OF PACKAGES AND CONSTRAINTS If the design uses wire bond interconnects, the bond finger patterns will vary from in-line or in-line radial to multi-tiered, arc-based patterns, depending on package technology and density of chip I/Os. APD can automatically create the appropriate pattern based on specific, user-defined constraints. These include: Bond finger dimension Bond finger and wire spacing Minimum and maximum wire length Maximum bond wire angle (only for radial) Number of rows in stagger or shelves, if applicable Alternatively, APD can automatically calculate the best pattern based on more general design criteria. APD TECHNOLOGICAL ADVANCES AUTO AND MANUAL OPTIMIZATION OF CHIP-TO-PACKAGE INTERCONNECTS The netlist-less design philosophy available in APD lets you optimize the chip to package interconnect without a predefined netlist. If routability and delay drive chip-to-package connectivity, use automatic and interactive assignment utilities to achieve optimal results. The interactive assignment utility allows you to create new nets, assign specific pins, delete pins, or delete nets. If a plating bar exists, you can also build the package I/O to plating bar connectivity. If a net list does exist, you don t have to worry about its format. The netlist Text Wizard reads virtually any ASCII file. Define any power/ground shapes for generating power and ground distribution, APD provides interactive tools capable of creating the most complex shapes. If you need to distribute power and ground through rings, use the

3 Power/Ground Ring Wizard to generate the conductor shape automatically. SPECCTRA EXPERT AUTOROUTER AND SPIDERROUTE FOR INTERACTIVE OR AUTOMATIC RULES-BASED ROUTING At the end of the day, the most important and time consuming step in any design is routing. By their very nature, complex IC packages are a routing challenge. Whether it s an all-angle, single-layer, wire bonded design with a plating bar, or a flip chip on a multi-layer build-up substrate, each technology presents its own unique set of challenges. Advanced Package Designer has surmounted this problem by providing the designer with a toolbox of routing functionality from interactive to automatic. For dynamic interactive routing, APD has the most powerful set of interactive routing tools available today. This suite of routing functionality provides the capability to easily route any type of IC package design from all angle wire bonded to orthogonal flip chip, these tools are fast and accurate. Any electrical constrained nets, such as those with controlled impedance, matched delay, or differential requirements, are easily routed to those constraints with dynamic feedback when rule violations occur. In addition to the interactive tools, APD also provides automatic routing capability. Two routers are included in APD: SPECCTRA Expert autorouter and SpiderRoute. So depending on the interconnect technology of your design, wire bond or flip chip, you can choose which router is more appropriate. For multi-layer flip chip designs, which typically have a large amount of electrically constrained nets, SPECCTRA Expert is a powerful shapebased router that can manager these complex design challenges. For all-angle wire bonded designs, which can be extremely dense and require a different set of routing algorithms, SpiderRoute is the right choice. SpiderRoute is a schedule-based router that evaluates the routing channels available and optimizes the routing based on spacing rules. SpiderRoute also automatically creates and routes orthogonal routes out to the plating bar. REAL-TIME ANALYSIS ENSURES ELECTRICAL INTEGRITY Beyond innovative packaging and routing facilities, what really marks APD as a next generation tool is its ability to ensure electrical integrity by performing real-time analysis. You can do this in two different ways: Dynamic RLC displays line parasitic data in real-time as you enter traces, reflecting resistance, inductance, and capacitance Check the design against electrical design constraints for crosstalk thresholds, delay, and line impedance ANSOFT INTERFACE ALLOWS 3-D EXTRACTION Over and above APD s intrinsic strengths, it also has a built-in interface to Ansoft s TPA. The interface automatically extracts the geometry that can be read directly into TPA to create 3-D models. These models can be read into SPECCTRAQUEST signal integrity solutions (part of Advanced Package Engineer) for simulation. EXTENSIVE MANUFACTURING OUTPUT CAPABILITIES The total solution philosophy demands as much attention to outputs as to internal capabilities. APD can generate all the types of manufacturing data likely to be required from documentation to tooling. You can easily create bond diagrams, dimension documents, format drawings, and various output files containing critical package data. Manufacturing output supports Gerber 4X00 & 6X00 series, 274X, Barco, DXF, AIF2, and GDSII. Many of today s foundries already use APD. This means you can send an APD design database to the foundry directly as manufacturing input, greatly compressing throughput times and pre-empting potential inaccuracies. The foundry can use the database to enhance manufacturing yields and implement any last minute changes to the package without inadvertently compromising the original 3 specifications. (Contact your foundry to confirm their specific capabilities.) PCB SYSTEM LEVEL HAND-OFF You ve seen now how Advanced Package Designer bridges the gap between silicon and package design. But it also bridges the gap between package and circuit board design, automatically generating all data required for PCB-level floor planning and layout: Physical footprint Schematic footprint Device models in SPICE, IBIS, or SPECCTRAQuest format This compresses setup time and raises data accuracy for systems designers. Additional Features: Advanced Package Designer truly is a total packaging solution, addressing the full design flow from end to end. Building upon the major capabilities already described, additional features include: Integration with silicon design Full UNIX/NT interoperability Free web downloadable viewer Special routing for dog-bone fanout vias, with or without tangent fillets, for both chip and package Auto smoothing of traces to any angle, diagonal, or arc Dynamic pad filleting Online, dynamic RLC parasitic calculation Design reuse features for utilizing prior designs with new ICs GDSII, DXF, Gerber, IDF bi-directional data transfer Full database compatibility with Allegro and SPECCTRAQuest These features are just a sampling of the productivity-boosting capabilities available in this powerful tool suite, Advanced Package Designer.

4 ADVANCED PACKAGE ENGINEER THE COMPLETE SHOP FOR INTELLIGENT DESIGN The more in-depth analysis you can perform early in the design cycle, the fewer tortured workarounds and design turns downstream. That s why Cadence created Advanced Package Engineer, the perfect complement of substrate design, routing, and analysis tools. PIECEMEAL ANALYSIS: BETTER THAN NOTHING BUT NOT BY MUCH Maintaining signal integrity in today s dense, high-speed IC packages is a mounting challenge, with the packaging s physical characteristics and geometries playing an increasingly critical role in signal behavior. Consequently, every packaging engineer needs the means to analyze signal behavior accounting for all the factors introduced by the package as an integral part of the normal design process. Until now though, such means simply did not exist. While there are some tools that can be used for 3-D analysis earlier in the design process, they are typically difficult to use, have no intelligent integration with the design tools, no interactive capabilities, and take a long time to solve problems. So this critical aspect of analysis has largely been the province of experts who do it after the package design is complete. The specialist selects some characteristics of the package and some critical net information, then attempts to recreate that data within his or her standalone modeling software. This process alone can take over two weeks. And when problems are identified, the remedies are all lesserevils either modify the package and delay the project, or try to work around the problem at the board level. But with increasingly stringent system constraints, the possibilities for such workarounds are extremely limited, so this tactic can end up creating worse problems downstream. Figure 3 Ansoft Tools Enable 3-D Analysis. Integration of Ansoft s Turbo Package Analyzer allows the design database to be automatically transferred. Turbo Package Analyzer produces 3-D resistance, inductance, capacitance, and conductance (RLCG) values and can be used for more accurate 3-D signal integrity analysis within SPECCTRAQuest for IC Packaging. INTEGRATED ANALYSIS THE WAY IT S SUPPOSED TO BE SPECCTRAQuest for IC packaging, the heart of Advanced Package Engineer finally closes the chapter on this old, inefficient workflow by putting total, integrated analysis capability into the hands of every packaging engineer early in the design cycle where it s really needed. It merges electrical and physical design into one easy-to-use environment, along with features designed specifically to support IC package exploration, definition, and implementation. Now you can explore pre-layout options, design signal and power/ ground plane distribution requirements, implement them in physical design, and then perform concurrent validation with layout. This methodology compresses design cycles up to 75 percent for high-speed devices, bestowing cost and performance improvements on downstream system designs as well. SPECCTRAQuest for IC Packaging tightly integrates SPECCTRAQuest simulation technology with Ansoft s extraction engine. The result is a unified design-and-analysis flow that enables you to make critical design decisions much earlier in the process (see Figure 3). With SPECCTRAQuest for IC Packaging, you don t get bogged down with 4 excessive detail about the physical layout. Design Wizards guide you through the entire process of building up design data for the substrate, wire bonds, interconnect and IC to help you get to simulation quickly, without being a physical CAD engineer. With limited design information, you can model topologies of critical net interconnect and simulate them against your desired results. Solution-sweep analysis lets you sweep various aspects of the design, such as I/O driver strengths, interconnect lengths, and loading conditions, then simulate against these parameter ranges. These results are used to determine optimized constraints that will govern the physical layout of critical paths and the power/ground distribution of the package. You can define constraints for interconnect routing in terms of delay, crosstalk, impedance, and/or inductance. The Advanced Package Designer tool reads these constraints directly from SPECCTRAQuest and automatically implements them through physical interconnect to ensure electrical requirements are met. With the combination of SPECCTRAQuest and Ansoft s TPA, accurate final verification of the package can be completed. Since rules have been defined, checked, and validated throughout the entire process, any remaining issues uncovered should be minimal and easily resolved before releasing the design to manufacturing. Direct database compatibility with the APD means package design data can be read in directly and used for analysis with no intermediate conversion. Conversely, you can make design changes directly within SPECCTRAQuest and pass them back into APD. INTEGRATED ANALYSIS FRONT TO BACK, TOP TO BOTTOM SPECCTRAQuest for IC Packaging not only provides for package-level analysis, but also provides for accurate PCB system level analysis. Final parasitic models for the package can be automatically generated and used

5 within the PC board analysis environment. These models significantly boost simulation accuracy of PCB-level interconnect by enhancing the standard I/O models supplied by the silicon house. SPECCTRAQuest for IC Packaging also lets you verify signal integrity through all levels of a system through its unique design link technology. You can actually link the package, or multiple packages, to the final PCB and perform true silicon-to-board simulation. For the first time in the industry, silicon and system can now be truly integrated in one environment, thanks to this revolutionary capability. Figure 4 Multi-level Analysis. Advanced Package Engineer lets you create a dynamic link between the package and board. This allows analysis from the on-chip driver through the wire bond, package interconnect, I/O pin onto the PCB, through the board route, and onto the destination load. Extract topologies and make analysis trade-offs with a button click. OUTPUT CAPABILITIES All the output features that distinguish Advanced Package Designer are present in Advanced Package Engineer, as well, providing a seamless flow into PCB design and manufacturing. KEEP PACE WITH TECHNOLOGY. KEEP AHEAD OF YOUR COMPETITORS With technological breakthroughs and fierce market pressures placing greater and greater demands on package designers and engineers, you need commensurately sophisticated and powerful tools tools that reflect the complex interplay between silicon, packaging, and PCB phases of the design process, which help you design accordingly. Cadence is the first to provide such comprehensive solutions. With our expert series of products, Cadence initiates a unique approach that breaks out of the myopic perspectives inherent in first-generation EDA tools. With Advanced Package Designer and Advanced Package Engineer, you ll be able to keep pace with the accelerating changes in IC design and meet the challenges they pose successfully. METHODOLOGY SERVICES Cadence provides a complete offering of customer services called methodology services. From individual product solutions to team-based environments, methodology services help customers achieve maximum productivity in a minimum amount of time. Our methodology experts can deploy a PCB development process that delivers repeatable design successes while reducing your time to market. CADENCE METHODOLOGY SERVICES INCLUDE: QuickStart Services - A QuickStart service is a pre-packaged, pre-defined, and pre-priced service that includes installation and verification of a Cadence product. It helps accelerate the implementation and use of a Cadence solution within a specific engineering environment. CIS Implementation and Database Creation Services Using your internal resources to install new systems and software can disrupt your workflow. Methodology services can take the burden off your IS and engineering staff with CIS Implementation and Database Creation services. A team of CIS professionals can deliver a completed CIS implementation service or prepare and populate your existing library. Our involvement ensures that you ll have an optimal configuration from the start. Conversion Services Cadence methodology services offers several migration services. If you have designs or libraries that need to be migrated, we can perform the conversions for 5 you. These services are especially useful when you have large numbers of files to convert, or if you have designs that require hand conversion beyond the capabilities of commercial translators. Onsite Consulting Please contact your Cadence account manager for detailed information on how a Cadence application engineer can assist you. EDUCATION SERVICES From basic product training to advanced high-speed PCB and IC packaging design techniques, Cadence training and education services accelerate your learning curve and put your company on a direct path to increased competitiveness. A variety of public, private, and Internet-based courses are available. For detailed information on training schedules and locations, please visit: FOR MORE INFORMATION us at pcbsalesinfo@cadence.com. Or log on to To locate a Cadence PCB sales office or Value-added Reseller in your area, visit globalnetwork.

6 CADENCE DESIGN SYSTEMS, INC. PCB Systems Division SW 68th Parkway, Ste. 200 Portland, OR USA phone: fax: website: EUROPE Cadence Design Systems Limited European Headquarters Bagshot Road Bracknell, Berkshire RG12 OPH United Kingdom phone: fax: website: JAPAN Cadence Design Systems, Japan PCB Systems Division Shin-Yokohama Kohoku-ku, Yokohama JAPAN phone: fax: website: Cadence Design Systems, Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All others are properties of their holders. Product # /02 WGD/15K