Conceptual V IN 3 VIN. C1 1uF/300mA 2.2uF/500mA. Enable EN 3. Disable

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1 Conceptual The is a compa ct fast response low dropout regulator specifically designed to continuously deliver up to 600mA output current. Designed with a P-cha nnel MSFET serie s pass transistor, the up0 yields extremely low dropout voltage (e.g. 300mVat 600mA) and maintains very low ground current (70uA). The does not require a bypass capacitor, hence achieving the smallest PCB area. The is designed and optimized to work with low-value, low-cost cera mic capacitors. nly a uf ceramic output capacitor is required for stable operation for any load conditions. ther features include f oldback overcurrent prote ction, quick soft start, a nd overte mperature prote ction. The is available in fixed output voltage from 0.8V to 3.3V with 0.V per step or as an adjustable device with a 0.8V reference voltage. The device comes in various packages. Cellular and Cordless Phones Bluetooth Portable Radios and Accessaries Battery-Powered Equipment Laptop, Palmtops, Notebook Computers Hand-Held nstruments PCMCA Cards Portable nformation Appliances General Description 600mA Low Dropout Linear Regulator Applications Wide nput Voltage Range from 2.5V to 5.5V Ultra Low Dropout Voltage: 600mA Ultra Fast Response in Line/Load Transient Stable with uf Ceramic utput Capacitor Low Ground Current: 70uA Typical Low Shutdown Current: < ua Foldback utput Current Limit High utput Accuracy.5% nitial Accuracy Fixed utput Voltages: 0.8V to 3.3V Adjustable utput Voltage from 0.8V to 4.5V ver-temperature Protection RoHS Compliant and Halogen Free V V ST23-3L (AMA3) VN Features Pin Configuration VN VN ST23-5L (AMA5) VN V FB rdering nformation VN 3 ST223-3L (AJA3) V 3 ST223-3L (BJA3) e rder Number Pkacka g ul P0AMA3-XX ST23-3 ul P0AMA5-XX ST23-5 ul P0AJA3-XX ST223-3 ul P0BJA3-XX ST223-3 ul P0AKA3-XX ST89-3 ul P0BKA3-XX ST89-3 ul P0ADD8-XX DFN3x3-8 ul P0ADC8-XX DFN6x5-8 ul P0PSU8-XX PSP-8 ul P0QSU8-XX PSP-8 Remar XX: Voltage ptions 00: Adjustable utput Voltage 08: 0.8V; 0:.0V; 2:.2V 5:.5V; 8:.8V; etc... D:.35V; L:.34V (00 version is not available for 3-lead packages ) Note: up products are compatible with the current PC/ JEDEC J-STD-020 requirement. They are halogen-free, RoHS compliant and 00% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes. V 2 VN 3 VN 2 V 3 ST89-3L (AKA3) ST89-3L (BKA3) VN 8 NC 8 VN 2 7 NC 2 7 V 3 6 VN 3 6 V 4 5 FB VN 4 5 PSP-8L (PSU8) PSP-8L (QSU8) VN 8 VN 8 VN 2 7 NC VN 2 7 V 3 6 V 3 6 V 4 5 FB V 4 5 DFN 3x3 (ADD8) DFN 6x5 (ADC8) Note: The figures are not to scale VN FB V NC NC FB Rev. C0, File Name: -DS-C00

2 Typical Application Circuit VN V V N 3 2.2V C uf/300ma 2.2uF/500mA AMA3-2 C2 uf/300ma 2.2uF/500mA V N VN V V =.2V 5 C uf/300ma 2.2uF/500mA Enable Disable 3 AMA FB R 00K R2 00K C3 22pF C2 uf/300ma 2.2uF/500mA Pin No. Pin Name VN Pin Function 2 G ND Ground. 3 4B 5T F VU Functional Pin Description nput Voltage. This pin connects to the source of the internal pass transistor that supplies current to the output pin. Bypass VN to with a minimum uf ceramic capacitor. Place the decoupling capacitor physically as close as possible to the device. Enable nput. Pulling this pin below 0.35V turns the regulator off, reducing the quiescent current to a fraction of its operating value. This pin is not available for 3-pin packages. Feedback Pin (Adjustable Version). This pin is the non-inverting input of the error amplifier. The FB pin voltage is regulated to 0.8V reference voltage. Set the output voltage according to V = 0.8 x (R + R2)/ R (V). This pin is not internally connected for the fixed output version. utput Voltage. This pin is power output of the device. A pull low resistance exists when the device is disabled by pulling low the pin. To maintain adequate transient response to large load change, a minimum uf ceramic capacitor is required to reduce the effects of current transients on V. Rev. C0, File Name: -DS-C00 2

3 Functional Block Diagram Power n Reset Current Sense VN Band Gap Thermal Shutdown V REF Error Amp. Fixed MSFET Driver V Adjustable FB Definitions Some important terminologies for LD are spe cified below. Dropout Voltage The input/output Voltage differential at which the regulator output no longer maintain s regulation again st further reductions in in put voltage. Mea sured when the output drops 2% below its nomin al value, dropout voltage is affected by junction te mperature, load current a nd minimum input supply requirements. Line Regulation The change in output voltage for a change in input voltage. The measurement is ma de under conditions of low dissipation or by using pulse techniques such that average chip temperature is not significantly affected. Load Regulation The change in output voltage for a change in load current at constant chip temperature. The measurement is made under condition s of low dissi pation or by using pulse techniques such that average chi p te mperature is not significantly affected. Maximum Power Dissipation The maximum total device dissipation for which the regulator will operate within specifications. Quiescent Bias Current Functional Description Current which is used to operate the regulator chi p and is not delivered to the loa d. The quiescent current Q is defined as the supply current used by the regulator itself that does not pass into the load. t typically include s all bias currents required by the LD a nd any drive current for the pass transistor. The up0 is a compa ct fa st tra nsient re sponse low dropout regulator specif ically designed to continuously deliver up to 600mA output current f or spa ce-limited applications. Designed with a P-channel MSFET series pass transistor, the yields extremely low dropout voltage (e.g. 300mV at 600mA) a nd maintain very low ground current (70uA). The does not require a bypass capacitor, hence achieving the smallest PCB area. The is designed and optimized to work with lowvalue, low-cost cera mic capacitors. nly a uf cera mic output capacitor is required f or stable operation f or any loa d condition s. ther fe ature s include f oldba ck overcurrent protection, quick soft start, a nd overtemperature prote ction. The is availa ble in fixed output voltage s from 0.8V to 3.3V with 0.V increments. As shown in the Functional Block Diagram, the consists of a bandgap for reference voltage, error amplifier, P-channel MSFET pass transistor and internal feedback Rev. C0, File Name: -DS-C00 3

4 connected to the inverting input of error amplifier. The error amplif ier compare s this reference voltage with the feedback voltage a nd a mplifies the dif ference. f the feedback voltage is lower than the reference voltage, the pass-transistor gate is pulled low. This allows more current to pass to the output and increases the output voltage. f the feedback voltage is too high, the pass transistor gate is pulled high, allowing less current to pass to the output. The output voltage is fed ba ck through a n intern al or external resistor voltage-divider connected to the V pin. Additional block s include a current li miter, thermal sensor, and shutdown logic. Supply nput Power n Reset The input voltage supplies current to the output voltage and supplies current for control circuit. The input voltage is monitored f or power on re set (PR) to en sure the regulator is not en abled until the in put voltage is high enough for normal operation. The PR threshold level is typical 2.V at V N rising. Enable/Shutdown The features an active-high enable pin that allows the regulator to be disabled. Forcing the enable pin lower than 0.35V shuts down the regulator a nd reduce s its quiescent current less tha n ua. The voltage reference, error amplifier, gate-driver circuit and pass transistor are disabled in the shutdown state. When the regulator is in shutdown mode, a n internal 600Ω resistor is conne cted between V and. This is intended to discharge C when the LD regulator is disa bled. The intern al 600Ω has no adverse effect on device turn-on time. Forcing the enable pin higher than.2v enables the output voltage (once the in put voltage is higher tha n its PR threshold level). f the enable function is not needed in a specific application, it may be tied to VN to kee p the regulator in a n always on state. The en able pin use s CMS technology and cannot be left floating, as this may cause an indeterminate state on the output. Current Limit and Short-Circuit Protection The includes a current li miter that monitors a nd controls the gate voltage of pa ss transistor to li mit the output current to 500mAtypically. A short circuit protector monitors the output voltage and asserts output short circuit if V is lower than 40% of V NM. The current limiting level is reduced to 800mA. The output voltage is rebuilt after short circuit is removed. vertemperature Protection Functional Description The overte mperature protection li mits total power dissipation in the. When the junction temperature exceeds T J = 70 C, the thermal sen sor sign al the shutdowns logic, turning of the pass transistor and allows the device to cool down. The thermal sensor turns on the pass transistor again after the device junction temperature drops by 40 C, re sulting in a pulsed output during continuous during continuous thermal-overload conditions. The over te mperature prote ction is de signed to prote ct the device in the event of a fault condition. For continual operation, do not exceed the recommended temperature of T J = 25 C for maximum reliability. Rev. C0, File Name: -DS-C00 4

5 Absolute Maximum Rating Supply nput Voltage V N (Note ) V to +6V ther Pins V to (V N + 0.3V) Storage Temperature Range C to +50 C Junction Temperature C Lead Temperature (Soldering, 0 sec) C ESD Rating (Note 2) HBM (Human Body Mode) kV MM (Machine Mode) V Thermal nformation Package Thermal Resistance (Note 3) ST23-3L θ JA C/W ST23-5L θ JA C/W ST89-3L θ JA C/W ST223-3L θ JA C/W DFN3x3-8L θ JA C/W DFN6x5-8L θ JA C/W PSP-8L θ JA C/W ST23-3L θ JC C/W ST23-5L θ JC C/W ST89-3L θ JC C/W ST223-3L θ JC C/W DFN3x3-8L θ JC C/W DFN6x5-8L θ JC C/W PSP-8L θ JC C/W Power Dissipation, P T A = 25 C ST23-3L W ST23-5L W ST89-3L W ST223-3L W DFN3x3-8L W DFN6x5-8L W PSP-8L W Recommended peration Conditions perating Junction Temperature Range (Note 4) C to +25 C perating Ambient Temperature Range C to +85 C Supply nput Voltage, V N Vto +5.5V Rev. C0, File Name: -DS-C00 5

6 Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Unit Supply nput Voltage SVupply nput PVR Threshold PVR Hysteresis Voltage Q uiescent Current V Q Shutdown Current utput Voltage. 5 N V V PRTH V PRHYS SHDN V = 5V, =00m A A =-0V - 0. ua u V utput Voltage Accuracy V N = V +.0V; =, ma NM fixed output voltage version V. % NM Reference Accuracy Voltage V FB V N = 3.3V, = ma, V = FB adjustable output voltage version, V.8 utput Line Regulation ΔV REF(LNE ) utput Load Regulation ΔV REF(LAD) 2.5V < V N = ma ma < < 5.5V, and V N < 500mA, V N > V +.0V = VN M, V. %/ +-.0V A. %/ DVropout Voltage DRP = 300mA, 2.5V < V N = 600mA, 2.7V < V N <-2.7V <-5.5V mv Frequency = 0Hz, =-0mA Freequency = khz, =-0mA Power Ratio Supply Rejection PSRR Frequency = 00kHz, Frequency = 0Hz, =-0mA =-300mA db Freequency = khz, =-300mA Frequency = 00kHz, =-300mA Enable EVnable DVisable EN nput ETnable High Level Low Level Current Delay Time. 2 - SD DELAY V N V V. 3 = 5.5V, V =5.5V or 0V -- - ua form V design >.2V to V > 0% V NM, by s u T utput Ramp Up Time SS from V design = 0% to 90% of V, NM by s u Rev. C0, File Name: -DS-C00 6

7 Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Unit Protection Current Limit Threshold. 9 LM A Short Circuit Current A Thermal Shutdown Temperature Thermal Shutdown Hysteresis T SD = 0mA, V N T SDHYS = 0mA, V N = V = V = 5.5V C, =-5.5V C Note. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. θ JA is measured in the natural convection at T A = 25 C on a low effective thermal conductivity test board of JEDEC 5-3 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions. Rev. C0, File Name: -DS-C00 7

8 Typical peration Characteristics This page is intentionally left blank and will be updated later. Rev. C0, File Name: -DS-C00 8

9 The is specially designed to provide low-noise, high PSRR output voltage without a bypa ssing capacitor on its reference voltage. However, in put a nd output ca pacitor should be well con sidered for optimal performance. nput Capacitors The requires well-decoupled supply input for optimal performance. A mini mum uf ca pacitor is required frominput-to-ground to provide stability. nput capacitors greater than uf of fer superior in put line tra nsient re sponse and will assist in maximizing the highest possible power supply ripple re jection ratio (PSRR). Cera mic, ta ntalum, or aluminum electrolytic capacitors may be selected for CN. There is no spe cific capacitor ESR requirement f or CN. However, l ow-esr cera mic ca pacitors provide opti mal perf orma nce at a mini mum of spa ce a nd are highly recommended due to their inherent capability over tantalum capacitors to withsta nd in put current surge s from low impedance sources such as batteries in portable devices. Additional high frequency capacitors, such as small-valued NP dielectric type capacitors, help filter out high-frequency noise and are good design practice in any RF-based circuit. Place the capacitors physically a s close as possible to the device with wide and direct PCB traces. utput Capacitors and Stability For proper load voltage regulation and operational stability, a capacitor is required between V and pins. The is designed and optimized to work with low-value, low-cost cera mic ca pacitors in spa ce saving a nd performance consideration. Typical output capacitor values for maximum output current conditions range from uf to 0uF. Larger capacitors are recommended for applications expecting low output noise a nd optimum power supply ripple reje ction chara cteristics. Place the ca pacitors physically as close as possible to the device with wide a nd direct PCB traces. X7R/X5R dielectric-type cera mic ca pacitors are recommended because of their temperature performance. X7R type capacitors loss capacitance by 5% over the ir operating temperature rand and are the most stable type of ceramic capacitors. Z5U or Y5V dielectric ca pacitors loss their capacitance by 50% and 60% respectively over their operating temperature ra nge s. f Y5V or Z5U capacitors are used as output capacitors, the capacitance must be much higher than that of X7R capacitors to ensure the sa me mini mum ca pacitance over the operating temperature range. ESR of output ca pacitors should be well con sidered to ensure stable operation of the device. High ESR ca pacitors may cause high frequency oscillation. Figure shows the acceptable ESR range of output capacitor for stability. No Load Stability Application nformation The up0 is de signed to maintain output voltage regulation a nd sta bility under operation al no loa d conditions. This is important characteristic for CMS RAM keep-alive applications where the output current may drop to zero. Rev. C0, File Name: -DS-C00 9

10 ST23-3L Package nformation 0.60 MAX 2.90 BSC.00 REF REF 2.60 REF.90 REF.60 REF 2.80 BSC.60 BSC.90 BSC Recommended Solder Pad Layout MAX BSC ST23-5L 0.60 MAX.00 REF 2.90 BSC 3.60 REF 2.60 REF 0.95 REF.60 REF 2.80 BSC.60 BSC 0.95 BSC Recommended Solder Pad Layout MAX BSC Rev. C0, File Name: -DS-C00 0

11 ST223-3L Package nformation 3.3 MAX 6.50 BSC 3.00 BSC.50 MAX 7.00 BSC MN 6.30 REF 7.80 MAX.50 MAX 2.30 BSC.00 MAX 2.30 BSC Recommended Solder Pad Layout MAX MN 4.60 BSC ST89-3L 2.00 MAX REF 3.00 MAX 0.70 MN MAX.50 BSC.00 MAX Recommended Solder Pad Layout MAX BSC Rev. C0, File Name: -DS-C00

12 0.76 REF.27 REF.85 REF Conceptual PSP - 8L BSC Package nformation 2.29 BSC MN 2.39 REF 6.5 REF 8.00 MN.27 BSC Recommended Solder Pad Layout BSC MAX BSC Note.Package utline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.5mm. Rev. C0, File Name: -DS-C00 2

13 Package nformation DFN3x3-8L BSC REF MAX BSC Recommended Solder Pitch and Dimensions Note.Package utline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.5mm. Rev. C0, File Name: -DS-C00 3

14 DFN6x5-8L Package nformation BSC REF MAX BSC Recommended Solder Pitch and Dimensions Note.Package utline Unit Description: BSC: Basic. Represents theoretical exact dimension or dimension target MN: Minimum dimension specified. MAX: Maximum dimension specified. REF: Reference. Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2.Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.5mm. Rev. C0, File Name: -DS-C00 4