[] Specification of Automotive Version of Optical 3D Input Device E909.06A. [JTAG]

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1 1 Purpose This document shows the way an EL16-based microcontroller device has to flashed via JTAG and supports the user how to implement flashing operations of E via JTAG. 2 Abbreviations EL16 E909.06A TEST_MODE JTAG ID CALC_CRC data U_SLEEP n M_SLEEP n IR_SHIFT cmd DR_SHIFT(n) data 16bit microcontroller family designed by Elmos Semiconductor AG to allow reliable application development. It offers extended fail-safe features e.g. parity protection for ram cells and mcu registers and also crc-protected flash. Automotive Version of Optical 3D Input Device IC containing an EL16 microcontroller. a special pin that enables JTAG access through the GPIO pins. It must be set to 1 (high level) for JTAG operation. For E909.06A this is a constant value of 0x91 Function to calculate the CRC bits for a Flash data word Macro to delay execution for n * 1/ seconds Macro to delay execution for n * 1/1.000 seconds Macro to shift 8 bits into JTAG Instruction Register Macro to shift n bits of data into JTAG Data Register 3 References [] Specification of Automotive Version of Optical 3D Input Device E909.06A. [JTAG] IEEE Std (IEEE Standard Test Access Port and Boundary-Scan Architecture) The E909.06A JTAG is created according to this Standard. 4 Basic Flash Information The Flash contains 30K words by 22 bit including 6 bit CRC protected memory. As a automotive qualified module it guarantees 10 years data retention at 85 C and a minimum of erase cycles. Parameter Value Remarks Main Block Size 30K words by 22 bit 16 bit data + 6 bit CRC Address Range 0x1000 0xFFFF (TMODE=1) Page Size 256 words by 22 bits / page 16 pages Row Size 32 words by 22 bits / row 8 rows/page CRC polynomial x^6 + x^4 + x^3 + x^2 + x^1 + 1 (see example code) Hamming distance 4 1 bit error correctable, 2 bit errors detectable 4.1 Flash Organization Flash is organized by 30K words by 22 bit. A page is composed of eight adjacent rows. The Flash can only be accessed word-wise, byte access is not possible. A page has 256 words by 22 bits. A word contents 16 bit data + 6 bit CRC. So 60 Kbytes of data is available for the application. 1/8

2 5 JTAG Interface To access the FLASH structures of E909.06A a 4 -wire JTAG interface is used. The JTAG interface can be accessed via GPIO pins 4 to 7 when TMODE=1. TMODE=0 resets all test and debug structures and the IC operates in normal mode. The Flash access mode is enabled when the appropriate JTAG instruction is loaded into the JTAG instruction register (see examples later on). To minimize side effects in Flash Test Mode, the analog part of the IC is forced to power-down and the digital part is hold to reset state. 5.1 JTAG overview In test mode, the JTAG TAP controller can be accessed via the GPIO port according the following table: Table 1. Signal Mapping Normal Mode JTAG Mode TMODE=0 TMODE =1 GPIO4 TDO GPIO5 TDI GPIO6 TMS GPIO7 TCK The used JTAG signals are described here: Table 2. JTAG Signals Pin Dir. Usage TMS IN Signal to control the JTAG state machine TCK IN JTAG clock input TDI IN JTAG data input TDO OUT JTAG data output TMODE IN JTAG enable when '1', Reset of JTAG TAP Controller and Test Registers when '0' For an overview the TAP controller flow is described in the following figure: Figure 1. TAP Controller States 2/8

3 5.2 JTAG Sequences Macros To simplify this documentation some high-level macros are used to describe JTAG access. This macro notation will be used in the code examples. 5.3 U_SLEEP n MACRO The macro U_SLEEP has to guaranty a delay of n µs (1/ seconds) between JTAG operations. 5.4 M_SLEEP n MACRO The macro M_SLEEP has to guaranty a delay of n ms (1/1.000 seconds) between JTAG operations. 5.5 IR_SHIFT cmd MACRO This macro loads a desired JTAG instruction into the JTAG instruction register (IR) of the target device. This register is 8 bits wide with the least-significant bit (LSB) shifted in first. The data output from TDO during a write to the JTAG instruction register contains the version identifier of the JTAG interface (or JTAG ID) implemented on the target device. Regardless of the 8-bit instruction sent out on TDI, the return value on TDO is always the JTAG ID. Each instruction bit is captured from TDI by the target on the rising edge of TCK. Figure IR_SHIFT Macro shows how to load a instruction into the JTAG IR register: LSB MSB TCK TMS TDI IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 TDO ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Figure 2. IR_SHIFT Macro 5.6 DR_SHIFT(n) data MACRO This macro loads n-bit data into a JTAG data register (DR). The data is shifted, most-significant bit (MSB) first, into the target s TDI input. Each bit is captured from TDI on a rising edge of TCK. At the same time, TDO shifts out the last captured/stored value in the addressed data register. A new bit is present at TDO with a falling edge of TCK. The next figure shows how to load a 16-bit word into the JTAG DR and read out a stored value via TDO. DR_ SHIFT(16) is used to access an 16 bit wide test register. Use DR_SHIFT(n) for accessing n-bit wide registers respectively (e.g. DR_SHIFT(20)). The figure below shows the behavior of the JTAG DR_SHIFT(16) macro: MSB LSB TCK TMS TDI DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 TDO DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Figure 3. DR_SHIFT(16) Macro 3/8

4 5.7 CALC_CRC data MACRO To write a data word to the Flash, you have to supply a CRC value according to the data. A simple code example in C will calculate these required CRC bits and can be used to implement this macro: // data : std _ logic _ vector[15:0] // crc : std _ logic _ vector [5:0] // crc _ data : std _ logic _ vector[21:0] long CALC _ CRC ( long data ) { int i; long orig = data << 6; /* store data to left */ long polynom = 0x2f8000; /* magic */ data = data << 6; for ( i = 0; i <= 15; i++ ) { if ( data > 0x1fffff ) /* */ { data = data ^ polynom; } } data = data << 1; data = data >> 16; } return ( data orig ); /* CRC and Data */ 4/8

5 6 Flash Operations This section demonstrates the typical operations by providing example code sequences using the defined macros. 6.1 MASS ERASE Mass Erase will erase the complete flash area of 30K words to Mass Erase Sequence Mass Erase Flash INPUT.: none OUTPUT: none start mass erase sequence DR _ SHIFT(0x0A) 0x28a erase/mass on U _ SLEEP 5 wait min. 5 us DR _ SHIFT(0x0A) 0x28b do it... M _ SLEEP 20 takes 20 ms DR _ SHIFT(0x0A) 0x283 erase off U _ SLEEP 100 wait min. 100 us DR _ SHIFT(0x0A) 0x200 all off U _ SLEEP 1 wait min. 1 us Mass Erase Done 5/8

6 6.3 WRITE WORD Write Word(s) write 16 bit data + 6 bit CRC at a given address into the Flash (see CRC example code above for setting up the CRC bits). From one to Row Size data may be written, then an ending sequence is necessary. 6.4 Write Word Sequence Write Data Word(s) to Flash (max. Row Size data per call) INPUT.: [address], [data0], [data1],, [data31] OUTPUT: none IR _ SHIFT 0xA0 select data in register DR _ SHIFT(0x16) CALC _ CRC([data0]) calculate crc bits and shift data + crc IR _ SHIFT 0xA4 select address register DR _ SHIFT(0x10) [address] data address start writing sequence DR _ SHIFT(0x0A) 0x284 X addr, prog U _ SLEEP 5 wait min. 5 us DR _ SHIFT(0x0A) 0x285 + NV store U _ SLEEP 10 wait min. 10 us DR _ SHIFT(0x0A) 0x2c5 + Y addr U _ SLEEP 20 wait min. 20 to 40 us DR _ SHIFT(0x0A) 0x285 - Y addr delay min. 20 nano sec. prior to next write or end IR _ SHIFT 0xA0 select data in register DR _ SHIFT(0x16) CALC _ CRC([data1]) calculate crc bits and shift data + crc IR _ SHIFT 0xA4 select address register DR _ SHIFT(0x10) [address+2] data address start writing sequence DR _ SHIFT(0x0A) 0x284 X addr, prog U _ SLEEP 5 wait min. 5 us DR _ SHIFT(0x0A) 0x285 + NV store U _ SLEEP 10 wait min. 10 us DR _ SHIFT(0x0A) 0x2c5 + Y addr U _ SLEEP 20 wait min. 20 to 40 us DR _ SHIFT(0x0A) 0x285 - Y addr delay min. 20 nano sec. prior to next write or end repeat as needed up to row size words ending sequence for flash row DR _ SHIFT(0x0A) 0x281 prog at row end U _ SLEEP 5 wait min. 5 us DR _ SHIFT(0x0A) 0x200 all off U _ SLEEP 1 wait min. 1 us Write Word(s) Done 6/8

7 6.5 READ WORD Read Word will read a 16bit and its CRC value from the Flash. 6.6 Read Word Sequence Read Data Word from Flash INPUT.: [address] OUTPUT: [data] IR _ SHIFT 0xA4 select address register DR _ SHIFT(0x10) [address] for data word to read reading sequence starts... DR _ SHIFT(0x0A) 0x280 X addr LABEL OnceAgain DR _ SHIFT(0x0A) 0x2D0 + Y addr, + Out delay 15 nano sec. DR _ SHIFT(0x0A) 0x2F0 + SE IR _ SHIFT 0xA9 DR _ SHIFT(0x16) 0x0000 read data and inc address shift result will provide [data + crc] end reading sequence DR _ SHIFT(0x0A) 0x280 X addr to read the next data word goto LABEL OnceAgain keep in mind in this mode the order is crc / data stop reading DR _ SHIFT(0x0A) 0x200 all off Read Word Done 7/8

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