Modeling and Design Challenges for Multi-Core Power Supply Noise Analysis 2009 DAC User Track

Transcription

1 Systems & Technology Group Modeling and Design Challenges for Multi-Core Power Supply Noise Analysis 2009 DAC User Track Ben Mashak, Howard Chen and Bill Hovis {mashak, haowei,

2 Outline Introduction Context and Motivation Details of Innovation Explanation of Results Future Tool Enhancements Summary 2

3 Introduction 3 Multi-core system-on-chip (SoC) design increases challenge to power distribution AC noise analysis. More asynchronous frequency domains stress wider bands of frequency on the supply impedance. Power reduction techniques like clock gating, power gating, frequency scaling, etc. can create maximum functional, supply noise. In addition POR and BIST procedures can be many times more disruptive to supplies than any functional mode and may need to be analyzed. Magnitude of timing impacting (not absolute) supply noise transfer between IP blocks and from IO to core logic supplies needs to be budgeted and analyzed.

4 Context and Motivation Focus of presentation Creation of worst case, unit current demand and alignment in this SoC design. Post-design extraction of package and PWB power supply distribution. Simulation and analysis of resultant AC supply noise to the circuit. 4

5 Context and Motivation (2) EDA vendor tools enable extraction of complete package and PWB supply distribution shapes and decoupling which enables a broad, system view of supply impedance and noise. Power distribution networks have a different modeling challenges than signals for which EDA tools default. Characteristic supply impedances are very low and typically in the mohm range. Accuracy of a supply model at DC is key due to large currents involved. 5

6 Details of Innovation Worst case di/dt current demand per unit and worst case asynchronous unit alignment proposed. Script developed to grid port definition for supply and return at chip pins in combined package and PWB extraction. Complete power distribution simulation of supply noise at chip circuit over 1000-cycles in about 1 CPU hour. FFT of supply noise to quantify portion of asynchronous noise impact from other units. Frequency domain alignment of the current demanded, the supply impedance and the resultant supply noise at a handful of chip circuit locations. 6

7 Example Power Distribution Topology 7 Large amount of data required for complete post design extraction. Chip detail not shown, but included like On chip decoupling from BEOL image, placed decoupling and non-switching, idle-high logic decoupling.

8 Post Design VDD Analysis Flow Package Design PWB Design Report Merge Pins Combined Design S-parameter Extraction Perl Package Port Def. Chip Grid Definition Chip Floorplan Legend In-house EDA Vendor Touchstone Unit Current Waveforms Perl Chip Placed Decoupling Create Regulator Impedance Touchstone w/ DC point Chip Power Grid Design Chip Unit Locations, Current Signatures And Decoupling C4 Currents Macromodel Generator No Yes Package and OK? PWB model NOVA (Howard Chen) Transient Supply Noise At Circuit Macromodel C4 map 8

9 Current Demand 9 For each unit Leakage, idle AC and maximum AC powers were calculated. Minimum transition time from idle to max active was set based on depth of logic pipe, actual current demand based on workload, etc. Intra-cycle AC demand was modeled with a triangular saw tooth waveform. Trapezoidal current demand envelope results when cycling from idle to max active state. Ramp up and ramp down times were assumed the same with approximately 50/50 duty cycle. Least common multiple of cycle times for asynchronous units was found to create worst case alignment.

10 Example Intra-cycle Current Demand Idle to max active ramp in 3 cycles shown. 10

11 Example Alignment of Asynchronous Units 11 Least common multiple of cycle times

12 Example Package Port Definition Package mounted to PWB during extraction. Best resolution is achieved when the port impedance is in the ballpark of the supply/return impedance which is typically in the mohm range. Ports were defined in the chip pin field on a grid with a custom script. <1mm grid is desirable if total number of ports is manageable. Example IO and core supply port bounding boxes are shown on the next slide. 12

13 Example Package Port Definition (2) Top side package view Chip outline and port grid 13

14 Simulation and Analysis of Results Example chip simulation input plots and results in the following slides. Matlab was used to compute FFT on input current demand and resultant output noise. In-house tools typically provide 1000-cycle circuit simulation results in one CPU hour. 14

15 Example Chip Placed Decoupling Map 15

16 Example Average Power 16

17 Example min(vdd) Distribution 17

18 Example Average C4 Current 18

19 Example Current Demand at Circuit 19

20 Example Noise at Circuit 20

21 Example V(t) with I(f) and Z self (f) 21

22 Example V(f) with I(f) and Z self (f) 22

23 Supply Noise Propagation Example shows intra-cycle noise created in the mid-frequency unit of the SoC propagates deep into high-frequency unit where it can impact timing. An appreciable amount of this noise was noticed >5mm from the closest circuit that demanded it. On the other hand, high-frequency unit noise was localized and quickly attenuated by on chip decoupling. 23

24 Future Enhancements 24 Extraction of return and supply path performance separately is desired. For designs with a common return strategy, simulation of supply to supply noise through the return is important. IO interfaces can drive asymmetric current demand on the supply and return due to pullup or pulldown only termination. Macromodels of power supplies would place special focus on matching the DC value of input touchstone to minimize potential for inducing voltage offset error when large current is applied.

25 S-parameter Port Definition Current port definition required for supplies in package/pwb extraction tools. P3 P4 Supply2 Supply1 P1 + _ Return P2 + _ Alternative reference would enable supply and return performance to be detailed separately in touchstone output. P3 Pr3 P4 Pr4 Supply1 Return Supply2 Common Reference P2 + Pr2 + P1 + _ Pr1 + _ 25

26 Example for Supply and Return Separation for IO Idle Bus1 Bus2 Pkg/PWB with supply and return lumped together + - Idle Bus1 Bus2 Pkg/PWB with supply and return modeled as separate ports + - Return doesn t move on 1 -> 0 transition. Transition is modeled correctly. 26

27 Example of Supply and Return Separation for IO Idle Bus1 Bus2 Pkg/PWB with supply and return lumped together + - Idle Bus1 Bus2 Pkg/PWB with supply and return modeled as separate ports + - Supply compression is over predicted for 0 -> 1. Transition is modeled correctly. 27

28 Macro Models of Power Distribution Macromodels allow simulations with convergence issues to solve. Being another level of abstraction, there is always the risk of the macromodel over/under representing the supply noise. Our experience has shown 0.5X to 2X difference in peak-to-peak noise between the touchstone and macromodel depending on the supply and tool level. Special matching of supply macromodel to touchstone DC value is desirable. Large voltage offset (between touchstone and macromodel) under worst case current makes one question the validity of the macromodel. 28

29 Macro Models of Power Distribution - AC 29 Macro model converges and over predicts supply noise, but better to over predict than underestimate.

30 Macro Models of Power Distribution - DC + V 1 - I 1 I 2 [Z(f)] + V 2 - Assume I 1 = -I 2 = 50A and Z 12 =Z 21, Then V 2 -V 1 = Vdrop = 50A*[Z 11 +Z 22-2*Z 12 ]. Touchstone Macro model Z 11 at 0Hz (self) 4.5mOhm 6.3mOhm Z 12, Z 21 at 0Hz (trans) 1.5mOhm 1.5mOhm Z 22 at 0Hz (self) 1.5mOhm 1.5mOhm 50A Vdrop calculated 150mV 240mV SPICE Vdrop 152mV 237mV 30 85mV extra drop

31 Summary 31 EDA vendor package and PWB extraction tools lend more credibility to post design simulation results by enabling broad system extraction of power distribution networks. SoC and common return designs complicate simulation and analysis of supply noise. The following enhancement requests for package and PWB supply extraction and modeling were made. Extraction of return and supply path performance separately is desired. Macromodels of power distribution networks would ideally place special focus on matching the DC value of input touchstone to minimize potential for inducing voltage offset error when large current is applied.

32 Acknowledgements Ankur Patel Darryl Becker Mark Bailey Mark Maxson Mike Maurice Mike Rohn Tom Liang Trevor Timpane Wes Martin 32