INEMI Packaging Substrate Workshop, Toyama, Japan, 2014 Challenges of Organic Substrates from EMS Perspective Weifeng Liu, Ph. D.

Transcription

1 INEMI Packaging Substrate Workshop, Toyama, Japan, 2014 Challenges of Organic Substrates from EMS Perspective Weifeng Liu, Ph. D. Date (4/10/2014) AEG - WW Microelectronics and Packaging

2 OUTLINE Overview of Substrate Challenges Substrate Warpage and Assembly Failures PoP assembly failure Head in pillow (HiP) Solder joint failure at double reflow Related Industry Standards Current Issues Future Work and Collaboration 2

3 Overview of Substrate Challenges Electrical: large bandwidth Physical: high I/O, fine pitch, large body size, low thickness Thermal: high power density Materials: low loss tangent, low dielectric constant, low CTE Integration: embedding active and passives, 2.5D/3D package Fabrication: high AR via filling, fine line/spacing Assembly: Substrate warpage during reflow System: L1/L2 interconnect reliability 3

4 Challenges Identified by ITRS 4

5 Mechanisms of Substrate Warpage Substrate warpage during reflow is caused by the CTE mismatch between building elements, primarily: Substrate (for BT substrate, CTE 17ppm/ o C) Die (silicon, 4ppm/ o C) Molding compound Heat spreader With the transition to lead free, higher reflow temperature will result in higher substrate warpage 5

6 Substrate Warpage During Reflow Temperature: 20 o C, 11.2mil Temperature: 85 o C, 5.4mil Temperature: 185 o C, 1.4mil Temperature: 248 o C, 5.7mil Temperature: 158 o C, 2.9mil Temperature: 45 o C, 8.5mil 6

7 Assembly Issues due to Warpage Die Board Non Wet Open Head-in-Pillow Open Stretched joint Head in pillow shorting Various solder joint defects can occur during SMT reflow process due to excessive BGA component and/or board warpage Kirk Van Dreel, HDPUG Report,

8 PoP Package Package on package (PoP) is a structure where two electronic packages are placed directly on top of the other package with solder joints connecting the stacked packages. One pass assembly: the bottom package is firstly placed on board, then the top package is dipped in flux and then placed on the bottom one, both packages go through the reflow process at the same time Two pass assembly: the top package is at first assembled on the bottom package, then the whole stack up is assembled on board via a separate reflow process. 8

9 Challenges with POP Assembly Number one challenge in assembly is to control and match warpage of top and bottom packages More than 90% of the defects in PoP assembly are due to package warpage* *Greg Caswell, Challenges With Package on Package (PoP) Technology, CTEA meeting, February 21,

10 Excessive Warpage Causing Open Joints Greg Caswell, Challenges With Package on Package (PoP) Technology, CTEA meeting, February 21,

11 Package and Assembly Trends The ongoing trends in package and assembly will increase the extent and degree of warpage and assembly defects Larger substrate size for high performance application Thinner substrate Finer pitch and smaller solder balls Finer and halogen free solder paste Higher reflow temperature More stacked die and PoP applications 11

12 Head in Pillow (HiP) HIP defect ball Good ball A head-in-pillow (HiP) defect is a process anomaly during the SMT reflow process where the BGA balls do not coalesce with the solder paste. When looking at a cross section, it looks like a head resting on a soft pillow. Major manufacturing defects and yield issue Not be able to detect effectively May show up at customer sites 12

13 HiP Formation Mechanism BGA balls are in contact with solder paste During reflow, package warpage causes separation between ball and paste. Solder ball and paste surfaces melt and oxidized During cooling, solder ball in contact with paste again Oxidation on the ball surface prevents collapsing of ball and paste 13

14 Types of Head in Pillow Based on the x-ray detection capability, HiP is classified by Flextronics to three types: Type 1: can be detected with right algorithm settings of AXI. Angle images show clearer image. Type 2: can be easily detected by AXI through pad slicing Type 3: difficult to detect through AXI (but may be detectable by CT) Type 2 Type 3 Type 2 Type 1 14

15 Factors Contributing to HiP Design/material selection Incoming Material Quality Package design Package substrate warpage PCB design Solder ball alloy Solder paste alloy/flux/type Package size/pitch Stencil design Solder Ball/paste contamination Inaccurate paste printing Insufficient paste volume Non-optimized reflow profile Inaccurate component placement Assembly Process Control PCB flatness/warpage Contamination Stencil thickness variation Solder ball/paste oxidation Component storage Assembly conditions Environmental Conditions HiP 15

16 Solder Joint Failure at Double Reflow Failure location (BGA side) Solder joint crack Dewetting and crack This type of solder joint failures typically occurs at package side at the second reflow It looks that the failed solder joints, while in molten, are pulled away from the component pads Component/board warpage during the reflow is suspected to play a major role in the failures, combined with other contributing factors Limited literature and study on this failure mechanism Julie Silk, Double Reflow-Induced Brittle Interfacial Failures in Pb-free Ball Grid Array Solder Joints, IPC APEX

17 Standards to Measure and Specify Warpage JEITA ED-7306: Measurement Methods of Package Warpage at Elevated Temperature and the Maximum Permissible Warpage, March 2007 JEDEC Publication No. 95: Reflow Flatness Requirements for Ball Grid Array Packages, March 2009 JESD22-B112A: Package Warpage Measurement of Surface Mount Integrated Circuits at Elevated Temperature, October 2009 JESD22-B108B: Coplanarity Test for Surface-Mount Semiconductor Devices, September 2010 IPC 9641: High Temperature Printed Board Flatness Guidelines, 2013 IPC-TM-650: Test methods (PCB bow and Twist) IPC-A-600: Acceptability of Printed Boards 17

18 JEDEC Publication No 95 (2009) Ball Diameter (mm) for Components less than or equal to 15mm Ball Height (mm) Ball Pitch (mm) 0.40 ±0.10 ±0.10 ± ±0.10 ±0.10 ± ±0.10 ±0.10 ±0.10 ±0.11 ± ±0.10 ±0.10 ±0.10 ±0.11 ±0.12 ±0.13 ± ±0.11 ±0.12 ±0.13 ±0.14 ±0.17 ± ±0.17 ±0.17 ±0.21 ±0.23 ± ±0.17 ±0.17 ±0.21 ±0.23 ±0.25 Ball Diameter (mm) for Components greater than 15mm Ball Height (mm) Ball Pitch (mm)

19 JEITA ED-7306 (2007) Ball Diameter (mm) Ball Height (mm) Ball Pitch (mm)

20 ITRS Target for High Temperature Package Warpage Year in production Pitch (mm) Ball Dia (mm) , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

21 INEMI Target for High Temperature Package Warpage Year in production Pitch (mm) Ball Dia (mm) , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , ,

22 Gap Analysis Significant gaps exist between current standard specifications and goals from ITRS and INEMI roadmaps Discrepancies exist between goals from ITRS and INEMI and between JEITA and JEDEC 22

23 Warpage Reduction General industry approaches to reduce substrate warpage Structure design Reduction of in plane CTE of the substrate INEMI Technology Roadmap, 2013 Hitachi Chemical Technical Report, NO 55 23

24 Warpage Reduction and Solder Joint Reliability Lower substrate CTE will help reduce substrate warpage as well as improve L1 interconnect and low K dielectric reliability Reduction of substrate CTE (XY Plane) has an adverse effect on the second level solder joint reliability Balance needs to be reached to take into account warpage reduction, and L1 and L2 interconnect reliability 4ppm/ o C 13ppm/ o C 17ppm/ o C BT Substrate (CTE: 17ppm/ o C) LTCC Substrate (CTE: 12ppm/ o C) HTCC Substrate (CTE: 7ppm/ o C) 24

25 Summary of Current Major Issues There lacks a systematic study and correlation how different factors contribute to assembly failures like HiP Substrate warpage PCB warpage Assembly process There lacks industry consensus on warpage specifications Gaps between current specifications and ITRS/INEMI goals Discrepancies between JEDEC and JEITA standards Certain packages like PoP may require tighter specifications on substrate warpage Defects like double reflow failure may occur at lower warpage conditions. Limited study on how warpage affects the solder joint reliability (stretched solder joint, double reflow failure ) The industry approach to reduce warpage by using lower CTE core materials has an adverse effect on L2 interconnect long term reliability Balance needs to be reached There lack specifications on PCB warpage at reflow 25

26 Future Work and Collaboration Further collaboration is needed between substrate vendors, package suppliers, OEMs, equipment suppliers, PCB suppliers, and EMSs INEMI serves a good platform to coordinate the efforts (Package/substrate/PCB suppliers) Develop materials and structures to minimize warpage in balance with L2 solder joint reliability (OEMs) Establish target on substrate CTE reduction based on system reliability requirements to guide substrate supplier warpage reduction Optimize assembly process (reflow profile, stencil design, solder paste selection) to mitigate warpage risks Evaluate different factors causing assembly failures and establish correlation between warpage and failures under optimized assembly process Need to consider overlay of PCB and package warpages Update or tighten current warpage specifications with industry acceptance For boards, warpage specifications need to be developed Evaluate warpage impact on solder joint reliability 26

27 Flextronics Work: Optimize Assembly Process 27

28 Flextronics Work: Effective ATI Screening Automated x-ray inspection of HiP defects through collaborating with equipment makers X-ray CT Image 2D AXI Inspection False call pin Escaped pin Solder Area Threshold <0.142 mm 2 28

29 Acknowledgement The author would like to thank Murad Kurwa and Anwar Mohammed for management support, David Geiger, Dr. Zhen (Jane) Feng, George Liu and Alejandro Castellanos for internal assembly and x-ray inspection data and review, Tuyen Nguyen for shadow moiré data, Hank Saiki of NTK and Jeffrey Lee of IST for discussion and review. 29

30 We will continue to deliver! 30