10. Design Optimization Overview

Transcription

1 10. Design Optimization Overview November 2013 QII QII Tis capter introduces eatures in Altera s Quartus II sotware tat you can use to acieve te igest design perormance wen you design or programmable logic devices (PLDs), especially ig density FPGAs. Introduction Pysical implementation can be an intimidating and callenging pase o te design process. Te Quartus II sotware provides a compreensive environment or FPGA designs, delivering unmatced perormance, eiciency, and ease-o-use. In a typical design low, you must syntesize your design wit Quartus II integrated syntesis or a tird-party tool, place and route your design wit te Fitter, and use te TimeQuest timing analyzer to ensure your design meets te timing requirements. Wit te PowerPlay Power Analyzer, you ensure te design s power consumption is witin limits. Initial Compilation: Required Settings Device Settings Tis section describes te basic assignments and settings or your initial compilation. Ceck te ollowing settings beore compiling your design in te Quartus II sotware. Signiicantly varied compilation results can occur depending on te assignments tat you set. Device assignments determine te timing model tat te Quartus II sotware uses during compilation. Coose te correct speed grade to obtain accurate results and te best optimization. Te device size and te package determine te device pin-out and te available resources in te device. Device Migration Settings I you anticipate a cange to te target device later in te design cycle, eiter because o canges in your design or oter considerations, plan or te cange at te beginning o your design cycle. Wenever you select a target device, you can also list any oter compatible devices you can migrate by clicking on te Migration Devices button in te Device dialog box. Selecting te migration device and companion device early in te design cycle elps to minimize canges to your design at a later stage Altera Corporation. All rigts reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks o Altera Corporation and registered in te U.S. Patent and Trademark Oice and in oter countries. All oter words and logos identiied as trademarks or service marks are te property o teir respective olders as described at Altera warrants perormance o its semiconductor products to current speciications in accordance wit Altera's standard warranty, but reserves te rigt to make canges to any products and services at any time witout notice. Altera assumes no responsibility or liability arising out o te application or use o any inormation, product, or service described erein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain te latest version o device speciications beore relying on any publised inormation and beore placing orders or products or services. ISO 9001:2008 Registered Quartus II Handbook Version 13.1 November 2013 Twitter Feedback Subscribe

2 10 2 Capter 10: Design Optimization Overview Initial Compilation: Required Settings I/O Assignments Te I/O standards and drive strengts speciied or a design aect I/O timing. Speciy I/O assignments so tat te Quartus II sotware uses accurate I/O timing delays in timing analysis and Fitter optimizations. I tere is no PCB layout requirement, ten you do not need to speciy pin locations. I your pin locations are not ixed due to PCB layout requirements, ten leave te pin locations unconstrained. I your pin locations are already ixed, ten make pin assignments to constrain te compilation appropriately. For more inormation about recommendations or making pin assignments tat can ave a large eect on your results in smaller macrocell-based arcitectures, reer to Optimizing Resource Utilization (Macrocell-Based CPLDs) in te Timing Closure and Optimization capter in volume 2 o te Quartus II Handbook. Use te Assignment Editor and Pin Planner to assign I/O standards and pin locations. For more inormation about I/O standards and pin constraints, reer to te appropriate device andbook. For more inormation about planning and cecking I/O assignments, reer to te I/O Management capter in volume 2 o te Quartus II Handbook. For inormation about using te Assignment Editor, reer to About te Assignment Editor in Quartus II Help. Timing Requirement Settings You must use compreensive timing requirement settings to acieve te best results or te ollowing reasons: Correct timing assignments enable te sotware to work ardest to optimize te perormance o te timing-critical parts o your design and make trade-os or perormance. Tis optimization can also save area or power utilization in non-critical parts o your design. I enabled, te Quartus II sotware perorms pysical syntesis optimizations based on timing requirements. Depending on te Fitter Eort setting, te Fitter can reduce runtime i your design meets te timing requirements. For more inormation about optimization wit pysical syntesis, reer to Pysical Syntesis Optimization in te Timing Closure and Optimization capter in volume 2 o te Quartus II Handbook. For more inormation about reducing runtime by canging Fitter eort, reer to Fitter Settings Page in te Quartus II Help. Use your real requirements to get te best results. I you apply more demanding timing requirements tan you need, ten increased resource usage, iger power utilization, increased compilation time, or all o tese may result. Quartus II Handbook Version 13.1 November 2013 Altera Corporation

3 Capter 10: Design Optimization Overview 10 3 Initial Compilation: Required Settings Te Quartus II TimeQuest Timing Analyzer determines i te design implementation meets te timing requirement. Te Compilation Report sows weter your design meets te timing requirements, wile te timing analysis reporting commands provide detailed inormation about te timing pats. To create timing constraints or te TimeQuest analyzer, create a Synopsys Design Constraints File (.sdc). You can also enter constraints in te TimeQuest GUI. Use te write_sdc command, or te Constraints menu in te TimeQuest analyzer. Click Write SDC File to write your constraints to an.sdc. You can add an.sdc to your project on te Quartus II Settings page under Timing Analysis Settings. 1 I you already ave an.sdc in your project, using te write_sdc command rom te command line or using te Write SDC File option rom te TimeQuest GUI allows you to create a new.sdc tat combines te constraints rom your current.sdc and any new constraints added troug te GUI or command window, or overwrites te existing.sdc wit your newly applied constraints. Ensure tat every clock signal as an accurate clock setting constraint. I clocks arrive rom a common oscillator, ten tey are related. Ensure tat you set up all related or derived clocks in te constraints correctly. You must constrain all I/O pins tat require I/O timing optimization. Speciy bot minimum and maximum timing constraints as applicable. I your design contains more tan one clock or contains pins wit dierent I/O requirements, make multiple clock settings and individual I/O assignments instead o using a global constraint. 1 Make any complex timing assignments required in your design, including alse pat and multicycle pat assignments. Common situations or tese types o assignments include reset or static control signals (wen te time required or a signal to reac a destination is not important) or pats tat ave more tan one clock cycle available or operation in a design. Tese assignments enable te Quartus II sotware to make appropriate trade-os between timing pats and can enable te Compiler to improve timing perormance in oter parts o your design. For more inormation about timing assignments and timing analysis, reer to Te Quartus II TimeQuest Timing Analyzer capter in volume 3 o te Quartus II Handbook and te Quartus II TimeQuest Timing Analyzer Cookbook. 1 To ensure tat you apply constraints or assignments to all design nodes, you can report all unconstrained pats in your design wit te Report Unconstrained Pats command in te Task pane o te Quartus II TimeQuest Timing Analyzer or te report_ucp Tcl command. Partitions and Floorplan Assignments or Incremental Compilation Te Quartus II incremental compilation eature enables ierarcical and team-based design lows in wic you can compile parts o your design wile oter parts o your design remain uncanged and import parts o your design rom separate Quartus II projects. November 2013 Altera Corporation Quartus II Handbook Version 13.1

4 10 4 Capter 10: Design Optimization Overview Pysical Implementation Using incremental compilation or your design wit good design partitioning metodology elps to acieve timing closure. Creating design partitions on some o te major blocks in your design and assigning tem to LogicLock regions, reduces Fitter time and improves te quality and repeatability o te results. LogicLock regions are lexible, reusable loorplan location constraints tat elp you place logic on te target device. Wen you assign entity instances or nodes to a LogicLock region, you direct te Fitter to place tose entity instances or nodes inside te region during itting. For more inormation about LogicLock regions, reer to About LogicLock Regions in Quartus II Help. Using incremental compilation elps you acieve timing closure block by block and preserve te timing perormance between iterations, wic aid in acieving timing closure or te entire design. Incremental compilation may also elp reduce compilation times. For more inormation, reer to te Incremental Compilation section in te Reducing Compilation Time capter in volume 2 o te Quartus II Handbook. 1 I you plan to use incremental compilation, you must create a loorplan or your design. I you are not using incremental compilation, creating a loorplan is optional. For more inormation about guidelines to create partition and loorplan assignments or your design, reer to te Best Practices or Incremental Compilation Partitions and Floorplan Assignments capter in volume 1 o te Quartus II Handbook. Pysical Implementation Most optimization issues involve preserving previous results, reducing area, reducing critical pat delay, reducing power consumption, and reducing runtime. Te Quartus II sotware includes advisors to address eac o tese issues and elps you optimize your design. Run tese advisors during pysical implementation or advice about your speciic design. You can reduce te time spent on design iterations by ollowing te recommended design practices or designing wit Altera devices. Design planning is critical or successul design timing implementation and closure. For more inormation, reer to te Design Planning wit te Quartus II Sotware capter in volume 1 o te Quartus II Handbook. Trade-Os and Limitations Many optimization goals can conlict wit one anoter, so you migt need to resolve conlicting goals. For example, one major trade-o during pysical implementation is between resource usage and critical pat timing, because certain tecniques (suc as logic duplication) can improve timing perormance at te cost o increased area. Similarly, a cange in power requirements can result in area and timing trade-os, suc as i you reduce te number o available ig-speed tiles, or i you attempt to sorten ig-power nets at te expense o critical pat nets. Quartus II Handbook Version 13.1 November 2013 Altera Corporation

5 Capter 10: Design Optimization Overview 10 5 Pysical Implementation In addition, system cost and time-to-market considerations can aect te coice o device. For example, a device wit a iger speed grade or more clock networks can acilitate timing closure at te expense o iger power consumption and system cost. Finally, not all designs can be realized in a ardware circuit wit limited resources and given constraints. I you encounter resource limitations, timing constraints, or power constraints tat cannot be resolved by te Fitter, consider rewriting parts o te HDL code. For more inormation, reer to te Timing Closure and Optimization and Area Optimization capters in volume 2 o te Quartus II Handbook. Preserving Results and Enabling Teamwork For some Quartus II Fitter algoritms, small canges to te design can ave a large impact on te inal result. For example, a critical pat delay can cange by 10% or more because o seemingly insigniicant canges. I you are close to meeting your timing objectives, you can use te Fitter algoritm to your advantage by canging te itter seed, wic canges te pseudo-random result o te Fitter. Conversely, i you cannot meet timing on a portion o your design, you can partition tat portion and prevent it rom recompiling i an unrelated part o te design is canged. Tis eature, known as incremental compilation, can reduce te Fitter runtimes by up to 70% i te design is partitioned, suc tat only small portions require recompilation at any one time. Wen you use incremental compilation, you can apply design optimization options to individual design partitions and preserve perormance in oter partitions by leaving tem untouced. Many optimization tecniques oten result in longer compilation times, but by applying tem only on speciic partitions, you can reduce tis impact and complete iterations more quickly. In addition, by pysically loorplanning your partitions wit LogicLock regions, you can enable team-based lows and allow multiple people to work on dierent portions o te design. For more inormation, reer to Quartus II Incremental Compilation or Hierarcical and Team-Based Designs in volume 1 o te Quartus II Handbook and About Incremental Compilation in Quartus II Help. Reducing Area By deault, te Quartus II Fitter migt pysically spread a design over te entire device to meet te set timing constraints. I you preer to optimize your design to use te smallest area, you can cange tis beavior. I you require reduced area, you can enable certain pysical syntesis options to modiy your netlist to create a more area-eicient implementation, but at te cost o increased runtime and decreased perormance. For more inormation, reer to te Netlist Optimizations and Pysical Syntesis, Timing Closure and Optimization, and Area Optimization capters in volume 2 and te Recommended HDL Coding Styles capter in volume 1 o te Quartus II Handbook. November 2013 Altera Corporation Quartus II Handbook Version 13.1

6 10 6 Capter 10: Design Optimization Overview Pysical Implementation Reducing Critical Pat Delay To meet complex timing requirements involving multiple clocks, routing resources, and area constraints, te Quartus II sotware oers a close interaction between syntesis, timing analysis, loorplan editing, and place-and-route processes. By deault, te Quartus II Fitter tries to meet te speciied timing requirements and stops trying wen te requirements are met. Tereore, using realistic constraints is important to successully close timing. I you under-constrain your design, you may get sub-optimal results. By contrast, i you over-constrain your design, te Fitter migt over-optimize non-critical pats at te expense o true critical pats. In addition, you migt incur an increased area penalty. Compilation time may also increase because o excessively tigt constraints. I your resource usage is very ig, te Quartus II Fitter migt ave trouble inding a legal placement. In suc circumstances, te Fitter automatically modiies some o its settings to try to trade o perormance or area. Te Quartus II Fitter oers a number o advanced options tat can elp you improve te perormance o your design wen you properly set constraints. Use te Timing Optimization Advisor to determine wic options are best suited or your design. I you use incremental compilation, you can elp resolve inter-partition timing requirements by locking down results, one partition at a time, or by guiding te placement o te partitions wit LogicLock regions. You migt be able to improve te timing on suc pats by placing te partitions optimally to reduce te lengt o critical pats. Once your inter-partition timing requirements are met, use incremental compilation to preserve te results and work on partitions tat ave not met timing requirements. In ig-density FPGAs, routing accounts or a major part o critical pat timing. Because o tis, duplicating or retiming logic can allow te Fitter to reduce delay on critical pats. Te Quartus II sotware oers pus-button netlist optimizations and pysical syntesis options tat can improve design perormance at te expense o considerable increases o compilation time and area. Turn on only tose options tat elp you keep reasonable compilation times and resource usage. Alternately, you can modiy your HDL to manually duplicate or adjust te timing logic. Reducing Power Consumption Te Quartus II sotware as eatures tat elp reduce design power consumption. Te PowerPlay power optimization options control te power-driven compilation settings or Syntesis and te Fitter. For more inormation, reer to te Power Optimization capter in volume 2 o te Quartus II Handbook. Reducing Runtime Many Fitter settings inluence compilation time. Most o te deault settings in te Quartus II sotware are set or reduced compilation time. You can modiy tese settings based on your project requirements. Quartus II Handbook Version 13.1 November 2013 Altera Corporation

7 Capter 10: Design Optimization Overview 10 7 Using Quartus II Tools Te Quartus II sotware supports parallel compilation in computers wit multiple processors. Tis can reduce compilation times by up to 15% wile giving te identical result as serial compilation. You can also reduce compilation time wit your iterations by using incremental compilation. Use incremental compilation wen you want to cange parts o your design, wile keeping most o te remaining logic uncanged. Using Quartus II Tools Design Analysis Te ollowing sections describe several Quartus II tools tat you can use to elp optimize your design. Te Quartus II sotware provides tools tat elp wit a visual representation o your design. You can use te RTL Viewer to see a scematic representation o your design beore syntesis and place-and-route. Te Tecnology Map Viewer provides a scematic representation o te design implementation in te selected device arcitecture ater syntesis and place-and-route. It can also include timing inormation. Wit incremental compilation, te Design Partition Planner and te Cip Planner allow you to partition and layout your design at a iger level. In addition, you can perorm many dierent tasks wit te Cip Planner, including: making loorplan assignments, implementing engineering cange orders (ECOs), and perorming power analysis. Also, you can analyze your design and acieve a aster timing closure wit te Cip Planner. Te Cip Planner provides pysical timing estimates, critical pat display, and a routing congestion view to elp guide placement or optimal perormance. For more inormation, reer to te Quartus II Incremental Compilation or Hierarcical and Team-Based Designs and Best Practices or Incremental Compilation Partitions and Floorplan Assignments capters in volume 1 and te Engineering Cange Management wit te Cip Planner capter in volume 2 o te Quartus II Handbook. Advisors Te Quartus II sotware includes several advisors to elp you optimize your design and reduce compilation time. You can complete your design aster by ollowing te recommendations in te Compilation Time Advisor, Incremental Compilation Advisor, Timing Optimization Advisor, Area Optimization Advisor, Resource Optimization Advisor, and Power Optimization Advisor. Tese advisors give recommendations based on your project settings and your design constraints. For more inormation about advisors, reer to Running Advisors in te Quartus II Sotware in Quartus II Help. November 2013 Altera Corporation Quartus II Handbook Version 13.1

8 10 8 Capter 10: Design Optimization Overview Conclusion Design Space Explorer Use te Design Space Explorer (DSE) to ind optimal settings in te Quartus II sotware. DSE automatically tries dierent combinations o netlist optimizations and advanced Quartus II sotware compiler settings, and reports te best settings or your design, based on your cosen primary optimization goal. You can try dierent seeds wit te DSE i you are airly close to meeting your timing or area requirements and ind one seed tat meets timing or area requirements. Finally, te DSE can run te dierent compilations on multiple computers in parallel, wic sortens te timing closure process. Conclusion For more inormation, reer to About Design Space Explorer in Quartus II Help. Te Quartus II sotware includes a number o eatures and tools tat you can use to optimize area, timing, power, and compilation time wen you design or programmable logic devices (PLDs). Document Revision History Table Document Revision History Table 10 1 sows te revision istory or tis capter. Date Version Canges November o Minor canges or HardCopy. May Added te inormation about initial compilation requirements. Tis section was moved rom te Area Optimization capter o te Quartus II Handbook. Minor updates to delineate division o Timing and Area optimization capters. June Removed survey link. November Template update. December Canged to new document template. No cange to content. August Corrected link July Initial release. Capter based on topics and text in Section III o volume 2. For previous versions o te Quartus II Handbook, reer to te Quartus II Handbook Arcive. Quartus II Handbook Version 13.1 November 2013 Altera Corporation