A Proposal of DEVS Model for Simulation Based Acquisition in FAB Process of Semiconductor Manufacturing

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1 Vol.133 (Information Technology and Computer Science 2016), pp A Proposal of DEVS Model for Simulation Based Acquisition in FAB Process of Semiconductor Manufacturing Sunghwan Moon 1, Youngshin Han 2 * and Jongsik Lee 1* 1 Dept. of Computer and Information Engineering, Inha University, Incheon, Republic of Korea shmoon@inhaian.net, jslee@inha.ac.kr 2 Dept. of Computer Engineering, Sungkyul University, Anyang, Republic of Korea hanys@sungkyul.ac.kr Abstract. An advanced equipment process is an important technological assets to companies. Development of the IT industry has led to an increase in demand for the semiconductor productivity of the high efficiency, steadily. But it is not easy to test using actual process because TAT (as known turnaround time of job) is so long. the test cost is also expensive. This paper proposes a DEVS model for simulation based acquisition in FAB process of semiconductor manufacturing. This model shows FAB process based on DEVS formalism. it will be enable us to reduce the cost of FAB process testing. Keywords: TAT, DEVS Model, Simulation Based Acquisition, FAB Process, Semiconductor Manufacturing 1 Introduction There are companies that manufacture products based on advanced equipment like factory automation. Their profits are directly related to the completion of manufacturing process. A low degree of completion causes problems such as increasing failure rate and reducing productivity, they result in the company's economic crisis. Therefore, it is important for companies to manage the manufacturing process methodically [1]. Development of the IT industry has led to an increase in demand for the semiconductor industry. The semiconductor industry, a classic case of manufacturing the products through half automatic process, could be divided into detailed processes. These processes comprised of design, wafer-fabrication, package and test, we focus on wafer-fabrication as known FAB process. FAB process is the most critical and complex to produce a semiconductor IC chip [2]. FAB process could also be divided into each of the processes like generating, storing and processing. But, it is hard to execute the test on actual process because turnaround time of job is so long. The test * Corresponding Authors. Youngshin Han (hanys@sungkyul.ac.kr) and Jongsik Lee (jslee@inha.ac.kr) ISSN: ASTL Copyright 2016 SERSC

2 cost is expensive as well. Simulation Based Acquisition is a method of approach to complex systems using modeling and simulation [3]. This method can be used as a means to test the FAB process at low cost. We propose DEVS model for simulation based acquisition in FAB process of semiconductor manufacturing. This model, based on Discrete EVent system Specification (DEVS) formalism[4], describes the FAB process modular and visually according to discrete events. It enables us to execute simulation and lower cost for various tests on FAB process. 2 Related Works Simulation Based Acquisition, which is a method used in the weapon system research and development in the field of national defense, approaches the system using modeling and simulation. This method reduces the test cost and time. In FAB process, the first objective is to increase their productivity. Turn Around Time as known TAT[5], indicates how quickly while keeping the error rate below a certain level over the semiconductor process, is an index for the production in the industry. It is not easy to measure TAT since semiconductor has long production cycle, simulation based acquisition enables us to measure it. Fig. 1. DEVS Atomic Model The complex system could be specified in each module by using the DEVS formalism. DEVS model consists of the atomic model, coupled model, input functions and output functions, and so on. Fig. 1 shows the concept of DEVS atomic model. FAB process can be represented by the DEVS model because of its own properties. 74 Copyright 2016 SERSC

3 3 Component Modeling for FAB of Semiconductor Manufacturing In order to get data from simulation, FAB process should be designed based on DEVS formalism. As shown in Fig. 2, we define six components as module in FAB process. In this paper, we design a model which presents from 'Wafer Generating' to 'Lot Storing'. Fig. 2. Sequence Diagram for FAB of Semiconductor Manufacturing 3.1 Generator and Lot Maker Two components works in this process. Generator generates wafers sequentially and Lot Maker makes a lot which is composed of 25 wafers. Generator: It generates wafers sequentially and send them to Lot Maker. Lot Maker: It receives wafers and stores them. It also makes a lot which is composed of 25 wafers. 3.2 Stocker and CM for Lot Two components work in this process. Stocker receives lots and sends a status information to CM. CM updates status information of all stockers. Stocker: It enqueues received lots and send a queue status to CM. CM: It receives status information from all stockers and manages them. 3.3 Process for Lot One component works in this process. Process receives each time a lot and execute a unique process. A unique process includes detailed steps such as diffusion, photo, etch, deposition, clean, etc. Copyright 2016 SERSC 75

4 Process: It receives a lot and executes own process. It sends a lot to the stocker after the process is over. 3.4 Storage for Lot One component works in this process. Storage stores processed lots from all stockers. Storage: It stores processed lots from all stockers. 4 DEVS Model for FAB of Semiconductor Manufacturing In this paper, we propose DEVS model for simulation based acquisition in FAB process of semiconductor manufacturing. As shown in Fig. 3, our proposed model describes the process for FAB and consist of components as mentioned above. Fig. 3. DEVS Model for FAB of Semiconductor Manufacturing 4.1 Assumptions There are assumptions for our model. Lot Maker has wafers out of all limits. Storage has lots out of all limits. There is no delay in communication between CM and other components. There are four Process(s) for a unique process such as diffusion, photo, etc. 76 Copyright 2016 SERSC

5 Lot Maker, Stocker(s), Storage and CM have queues. 4.2 Wafer and Lot Making Generator and Lot Maker are atomic models and operate as follows. 1. Generator generates a wafer and send it to Lot Maker. 2. Lot Maker enqueues a wafer and counts the number of wafers. 3. Lot Maker makes a lot using 25 wafers. 4. When a lot is made, Lot Maker sends the lot to Stocker Lot Storing and Management All Stockers and CM constitute a couple model and operate as follows. 1. Stocker1 enqueues a lot and counts the number of lots. Also, Stocker1 sends the status of queue to CM. 2. CM confirm the status whether each process has a lot or not. CM orders the stocker to send a lot to process not having a lot. 3. The stocker dequeues a lot and sends a job to the process. 4.4 Lot Processing and Completion All Processes and Storage are atomic models and operate as follows. 1. A processed lot moves on to next stocker. This step repeats the third time because there are four processes. 2. Stocker4 sends a lot which processed through all processes to Storage. 3. Storage receives a lot and enqueue a lot for storing. Also, Storage counts the number of lots for estimating productivity. 5 Conclusion We proposed DEVS model for simulation based acquisition in FAB process of semiconductor manufacturing in this paper. As the model describes FAB process based on DEVS formalism, it enables that we to get data from simulation. Simulation based acquisition using our model is helpful to reduce the test cost and time in advanced equipment process like FAB process. Future work will concentrate on the simulation using our DEVS model. The simulation could improve the efficiency in actual FAB process. Copyright 2016 SERSC 77

6 Acknowledgements. This research was funded by the Ministry of Science, ICT and Future Planning (NRF-2015R1C1A2A ) and this work was supported by Defense Acquisition Program Administration and Agency for Defense Development under the contract UD140022PD, Korea. References 1. Hatch, N.W., Mowery, D.C.: Process Innovation and Learning by doing in Semiconductor Manufacturing. In: Management Science, vol. 44(11-part-1), pp (1998) 2. Yang, G.R., Jung, Y.H., Kim, D.H., Park, S.C.: Bottleneck Detection Framework using Simulation in a Wafer FAB. In: Transactions of the Society of CAD/CAM Engineers, vol. 19(3), pp (2014) 3. Cho, K.T., Shim, J.Y., Lee, Y.H., Lee, S.Y., Kim, S.H.: Development of Simulation Architecture Framework for Simulation Based Acquisition. In: Journal of the Korea Society for Simulation, vol. 19(3), pp (2010) 4. Zeigler, B.P., Vahie, S.: DEVS Formalism and Methodology: Unity of Conception/Diversity of Application. In: Proceedings of the 25th Conference on Winter Simulation, pp (1993) 5. Park, H., Kim, S., Kim, T., Kim, J., Park, Y., Eom, Y.I.: Resource-Aware Job Scheduling and Management System for Semiconductor Application. In: Advances in Computer Science and Ubiquitous Computing, pp (2015) 78 Copyright 2016 SERSC